From 6a9c4b81fa86841e96f62d9ec42bfc15dd341a2c Mon Sep 17 00:00:00 2001
From: "U-Thor\\Schakal" <Schakal@Thor.(none)>
Date: Wed, 10 Nov 2010 18:24:58 +0100
Subject: [PATCH] added rw-r port ram

---
 cpu/src/mem_pkg.vhd    | 27 ++++-----------------------
 cpu/src/rw_r_ram.vhd   | 23 +++++++++++++++++++++++
 cpu/src/rw_r_ram_b.vhd | 26 ++++++++++++++++++++++++++
 3 files changed, 53 insertions(+), 23 deletions(-)
 create mode 100644 cpu/src/rw_r_ram.vhd
 create mode 100644 cpu/src/rw_r_ram_b.vhd

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
index cba7fd6..72ecb58 100755
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -43,7 +43,7 @@ package mem_pkg is
 		);
 	end component r2_w_ram;
 	
-	component rw2_ram is
+	component rw_r_ram is
 	generic	(
 				ADDR_WIDTH : integer range 1 to integer'high;
 				DATA_WIDTH : integer range 1 to integer'high
@@ -52,33 +52,14 @@ package mem_pkg is
 		--System inputs
 			clk : in std_logic;
 		--Input
-			wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-			
-			wr_en : in std_logic;
-			data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-			
-		--Output
-			out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
-		);
-	end component rw2_ram;
-	
-	component rw_ram is
-	generic	(
-				ADDR_WIDTH : integer range 1 to integer'high;
-				DATA_WIDTH : integer range 1 to integer'high
-			);
-	port(
-		--System inputs
-			clk : in std_logic;
-		--Input
-			wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+			rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
 			
 			wr_en : in std_logic;
 			data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
 			
 		--Output
-			out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+			rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
 		);
-	end component rw_ram;
+	end component rw_r_ram;
 
 end package mem_pkg;
diff --git a/cpu/src/rw_r_ram.vhd b/cpu/src/rw_r_ram.vhd
new file mode 100644
index 0000000..0a4f06e
--- /dev/null
+++ b/cpu/src/rw_r_ram.vhd
@@ -0,0 +1,23 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity rw_r_ram is
+	generic	(
+				ADDR_WIDTH : integer range 1 to integer'high;
+				DATA_WIDTH : integer range 1 to integer'high
+			);
+	port(
+		--System inputs
+			clk : in std_logic;
+		--Input
+			rw_addr, rd_addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
+			
+			wr_en : in std_logic;
+			data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+			
+		--Output
+			rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
+		);
+		
+end entity rw_r_ram;
diff --git a/cpu/src/rw_r_ram_b.vhd b/cpu/src/rw_r_ram_b.vhd
new file mode 100644
index 0000000..e9dba7b
--- /dev/null
+++ b/cpu/src/rw_r_ram_b.vhd
@@ -0,0 +1,26 @@
+library ieee;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+architecture behaviour of rw_r_ram is
+
+	subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
+	type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
+	
+	signal ram : RAM_TYPE; --:= (others=> x"00");
+
+begin
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if wr_en = '1' then
+				ram(to_integer(UNSIGNED(rw_addr))) <= data_in;
+				rw_out <= data_in;
+			else
+				rw_out <= ram(to_integer(UNSIGNED(rw_addr)));
+			end if;
+				rd_out <= ram(to_integer(UNSIGNED(rd_addr)));
+		end if;
+	end process;
+end architecture behaviour;
-- 
2.25.1