From 59ba228f921169bb12347932237c7500ccd58b41 Mon Sep 17 00:00:00 2001 From: Richard Smith Date: Fri, 25 Aug 2006 05:01:30 +0000 Subject: [PATCH] - Added suport for enabling USB P4 on the olpc USB P4 is disabled by default and we need to setup the mux bits proper to make it work. This is the frame work for that. All thats needed is the right address values git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/cpu/amd/gx2def.h | 10 ++++--- src/mainboard/olpc/rev_a/Config.lb | 1 + src/southbridge/amd/cs5536/chip.h | 1 + src/southbridge/amd/cs5536/cs5536.c | 42 +++++++++++++++++++++++++++++ 4 files changed, 51 insertions(+), 3 deletions(-) diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 8e6465912..06f9a6372 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -731,10 +731,14 @@ /* */ /* USB2*/ /* */ -#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) -#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) -#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) +#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) +#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) +#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) +#define USB2_SB_GLD_MSR_OHCI_BASE ( MSR_SB_USB2 + 0x08) +#define USB2_SB_GLD_MSR_EHCI_BASE ( MSR_SB_USB2 + 0x09) +#define USB2_SB_GLD_MSR_DEVCTL_BASE ( MSR_SB_USB2 + 0x0A) +#define USB2_SB_GLD_MSR_UOC_BASE ( MSR_SB_USB2 + 0x0B) /* Option controller base */ /* */ /* ATA*/ diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb index 0ab8e1e3a..ff7fa6a3f 100644 --- a/src/mainboard/olpc/rev_a/Config.lb +++ b/src/mainboard/olpc/rev_a/Config.lb @@ -138,6 +138,7 @@ chip northbridge/amd/gx2 register "enable_gpio0_inta" = "1" register "enable_ide_nand_flash" = "1" register "enable_uarta" = "1" + register "enable_USBP4_host" = "1" register "audio_irq" = "5" register "usbf4_irq" = "10" register "usbf5_irq" = "10" diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index 1edb349ac..6bd87430f 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -12,6 +12,7 @@ struct southbridge_amd_cs5536_config { int enable_gpio0_inta; /* almost always will be true */ int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */ int enable_uarta; /* internal uarta interrupt enable */ + int enable_USBP4_host; /* Enable USB Port 4 as a host */ /* following are IRQ numbers for various southbridge resources. */ /* I have guessed at some things, as I still don't have an lspci from anyone */ int ide_irq; /* f.2 */ diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 6ab87fdbf..f4a292b49 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -152,6 +152,48 @@ static void southbridge_init(struct device *dev) outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); } + + if (sb->enable_USBP4_host) { + volatile unsigned long* uocmux; + unsigned long val; + + printk_err("Base 0x%08x\n",USB2_SB_GLD_MSR_CAP); + + msr = rdmsr(USB2_SB_GLD_MSR_CAP); + printk_err("CAP 0x%08x%08x\n", msr.hi,msr.lo); + + msr = rdmsr(USB2_SB_GLD_MSR_OHCI_BASE); + printk_err("OHCI base 0x%08x%08x\n", msr.hi,msr.lo); + + msr = rdmsr(USB2_SB_GLD_MSR_EHCI_BASE); + printk_err("EHCI base 0x%08x%08x\n", msr.hi,msr.lo); + + msr = rdmsr(USB2_SB_GLD_MSR_DEVCTL_BASE); + printk_err("DevCtl base 0x%08x%08x\n", msr.hi,msr.lo); + + msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE); + printk_err("Old UOC Base 0x%08x%08x\n", msr.hi,msr.lo); + msr.hi |= 0xa; + msr.lo |= 0xfe010000; + +#if 0 + wrmsr(USB2_SB_GLD_MSR_UOC_BASE, msr); + + msr = rdmsr(USB2_SB_GLD_MSR_UOC_BASE); + printk_err("New UOC Base 0x%08x%08x\n", msr.hi,msr.lo); + + uocmux = (unsigned long *)msr.lo+4; + val = *uocmux; + + printk_err("UOCMUX is 0x%lx\n",*val); + val &= ~(0xc0); + val |= 0x2; + + *uocmux = val; +#endif + + } + } -- 2.25.1