From 55a6e47160891aefa82c396b19b97e53ac1d7bf0 Mon Sep 17 00:00:00 2001 From: Vlad Brezae Date: Mon, 14 Dec 2015 01:58:02 +0200 Subject: [PATCH] [arm] Implement OP_BIGMUL --- mono/arch/arm/arm-codegen.h | 10 ++++++++++ mono/mini/mini-arm.c | 10 ++++------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/mono/arch/arm/arm-codegen.h b/mono/arch/arm/arm-codegen.h index 9f89a91d5f2..4cde34937b7 100644 --- a/mono/arch/arm/arm-codegen.h +++ b/mono/arch/arm/arm-codegen.h @@ -500,14 +500,24 @@ typedef struct { /* Rd := (Rm * Rs)[31:0]; 32 x 32 -> 32 */ #define ARM_MUL_COND(p, rd, rm, rs, cond) \ ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond)) +#define ARM_UMULL_COND(p, rdhi, rdlo, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_UMULL, rdhi, rm, rs, rdlo, 0, cond)) +#define ARM_SMULL_COND(p, rdhi, rdlo, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_SMULL, rdhi, rm, rs, rdlo, 0, cond)) #define ARM_MUL(p, rd, rm, rs) \ ARM_MUL_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_UMULL(p, rdhi, rdlo, rm, rs) \ + ARM_UMULL_COND(p, rdhi, rdlo, rm, rs, ARMCOND_AL) +#define ARM_SMULL(p, rdhi, rdlo, rm, rs) \ + ARM_SMULL_COND(p, rdhi, rdlo, rm, rs, ARMCOND_AL) #define ARM_MULS_COND(p, rd, rm, rs, cond) \ ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond)) #define ARM_MULS(p, rd, rm, rs) \ ARM_MULS_COND(p, rd, rm, rs, ARMCOND_AL) #define ARM_MUL_REG_REG(p, rd, rm, rs) ARM_MUL(p, rd, rm, rs) #define ARM_MULS_REG_REG(p, rd, rm, rs) ARM_MULS(p, rd, rm, rs) +#define ARM_UMULL_REG_REG(p, rdhi, rdlo, rm, rs) ARM_UMULL(p, rdhi, rdlo, rm, rs) +#define ARM_SMULL_REG_REG(p, rdhi, rdlo, rm, rs) ARM_SMULL(p, rdhi, rdlo, rm, rs) /* inline */ #define ARM_IASM_MUL_COND(rd, rm, rs, cond) \ diff --git a/mono/mini/mini-arm.c b/mono/mini/mini-arm.c index 108b4abd256..6983398027a 100644 --- a/mono/mini/mini-arm.c +++ b/mono/mini/mini-arm.c @@ -4442,14 +4442,12 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb) ARM_DMB (code, ARM_DMB_SY); break; } - /*case OP_BIGMUL: - ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2); - ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2); + case OP_BIGMUL: + ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2); break; case OP_BIGMUL_UN: - ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2); - ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2); - break;*/ + ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2); + break; case OP_STOREI1_MEMBASE_IMM: code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF); g_assert (arm_is_imm12 (ins->inst_offset)); -- 2.25.1