From 5fec3077bb50417d16f79f04e7fad2c643724ad8 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Wed, 12 May 2010 01:04:31 +0200 Subject: [PATCH] parser: alu als eigene instanz im parser --- spec/speck.tex | 1 + src/beh_parser_tb.vhd | 31 ------------------------------- src/parser.vhd | 33 ++++++++++++++++++++++++--------- 3 files changed, 25 insertions(+), 40 deletions(-) diff --git a/spec/speck.tex b/spec/speck.tex index 96cbd6b..c2e715f 100644 --- a/spec/speck.tex +++ b/spec/speck.tex @@ -619,6 +619,7 @@ jeweils im Modul Parser und History vertauscht. behandelt??) \item aussagekr\"aftigere Fehlermeldungen. \item ALU: signal \emph{opM} fuer restberechnung +\item Parser: Signale der ALU bleiben intern. \end{itemize} \end{document} diff --git a/src/beh_parser_tb.vhd b/src/beh_parser_tb.vhd index 663e1bd..732f364 100644 --- a/src/beh_parser_tb.vhd +++ b/src/beh_parser_tb.vhd @@ -13,12 +13,6 @@ architecture sim of beh_parser_tb is signal p_rw, p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic; signal p_read, p_write : hbyte; signal p_spalte : hspalte; - - -- alu - signal opcode : alu_ops; - signal op1, op2, op3, opM : csigned; - signal do_calc, calc_done, calc_error : std_logic; - --scanner signal do_it : std_logic; signal finished : std_logic; @@ -39,36 +33,11 @@ begin p_wdone => p_wdone, p_write => p_write, p_finished => p_finished, - -- ALU - opcode => opcode, - op1 => op1, - op2 => op2, - op3 => op3, - opM => opM, - do_calc => do_calc, - calc_done => calc_done, - calc_error => calc_error, - -- TODO: calc_error : in std_logic; -- Scanner do_it => do_it, finished => finished ); - instalu : entity work.alu(beh) - port map - ( - sys_clk => sys_clk, - sys_res_n => sys_res_n, - do_calc => do_calc, - calc_done => calc_done, - calc_error => calc_error, - op1 => op1, - op2 => op2, - op3 => op3, - opM => opM, - opcode => opcode - ); - process begin sys_clk <= '0'; diff --git a/src/parser.vhd b/src/parser.vhd index 1d75398..ec03fed 100644 --- a/src/parser.vhd +++ b/src/parser.vhd @@ -18,15 +18,6 @@ entity parser is p_wdone : in std_logic; p_write : out hbyte; p_finished : out std_logic; - -- ALU - opcode : out alu_ops; - op1 : out csigned; - op2 : out csigned; - op3 : in csigned; - opM : in csigned; - do_calc : out std_logic; - calc_done : in std_logic; - calc_error : in std_logic; -- Scanner do_it : in std_logic; finished : out std_logic @@ -59,7 +50,31 @@ architecture beh of parser is signal err_next, err_int : hstr_int; signal errc_next, errc_int : hstr_int; signal errc_tmp_next, errc_tmp_int : hstr_int; + -- ALU + signal opcode : alu_ops; + signal op1 : csigned; + signal op2 : csigned; + signal op3 : csigned; + signal opM : csigned; + signal do_calc : std_logic; + signal calc_done : std_logic; + signal calc_error : std_logic; begin + instalu : entity work.alu(beh) + port map + ( + sys_clk => sys_clk, + sys_res_n => sys_res_n, + do_calc => do_calc, + calc_done => calc_done, + calc_error => calc_error, + op1 => op1, + op2 => op2, + op3 => op3, + opM => opM, + opcode => opcode + ); + p_write <= p_write_int; p_rget <= p_rget_int; p_wtake <= p_wtake_int; -- 2.25.1