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Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
[coreboot.git] / src / northbridge / amd / amdmct / mct / mcttmrl.c
2010-10-01 Zheng BaoTrivial. Re-indent the code. blob | commitdiff | raw
2008-01-18 Stefan ReinauerPlease bear with me - another rename checkin. This... blob | commitdiff | raw | diff to current
2007-12-19 Marc JonesInitial AMD Barcelona support for rev Bx. blob | commitdiff | raw | diff to current
my coreboot WIP stuff (asus m5a99x-evo board)