From: Bernhard Urban <lewurm@gmail.com>
Date: Wed, 31 Mar 2010 18:34:34 +0000 (+0200)
Subject: alu: erster (schlechter) versuch -- sim haut auch halbwegs hin
X-Git-Tag: review_abgabe~31
X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=commitdiff_plain;h=f6b73bf4a050a6186bac25abf1cd173cd00c7e4f;p=hwmod.git

alu: erster (schlechter) versuch -- sim haut auch halbwegs hin
---

diff --git a/src/alu.vhd b/src/alu.vhd
new file mode 100644
index 0000000..e9db35b
--- /dev/null
+++ b/src/alu.vhd
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity alu is
+	port
+	(
+		sys_clk : in std_ulogic;
+		sys_res_n : in std_ulogic;
+		opcode : in alu_ops;
+		op1 : in signed(31 downto 0);
+		op2 : in signed(31 downto 0);
+		op3 : out signed(31 downto 0);
+		do_calc : in std_ulogic;
+		calc_done : out std_ulogic
+	);
+end entity alu;
+
+architecture beh of alu is
+	-- signal cnt_int, cnt_next : integer range 0 to CNT_MAX;
+	signal op3_next : signed (31 downto 0);
+begin
+	process(sys_clk, sys_res_n)
+	begin
+		if sys_res_n = '0' then
+			op3 <= (others => '0');
+		elsif rising_edge(sys_clk) then
+			op3 <= op3_next;
+		end if;
+	end process;
+
+	process(do_calc, opcode, op1, op2)
+	begin
+		case opcode is
+			when ADD => op3_next <= op1 + op2;
+			when SUB => op3_next <= op1 - op2;
+			when MUL => op3_next <= op1 * op2;
+			when DIV => op3_next <= op1 / op2;
+			when others => op3_next <= (others => '0');
+		end case;
+		--	calc_done <= '1';
+		--else
+		--	calc_done <= '0';
+		--end if;
+	end process;
+end architecture beh;
diff --git a/src/alu_tb.vhd b/src/alu_tb.vhd
new file mode 100644
index 0000000..576c382
--- /dev/null
+++ b/src/alu_tb.vhd
@@ -0,0 +1,72 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity alu_tb is
+	end entity alu_tb;
+
+architecture sim of alu_tb is
+	component alu is
+		port
+		(
+			sys_clk : in std_logic;
+			sys_res_n : in std_logic;
+			opcode : in alu_ops;
+			op1 : in signed(31 downto 0);
+			op2 : in signed(31 downto 0);
+			op3 : out signed(31 downto 0);
+			do_calc : in std_logic;
+			calc_done : out std_logic
+		);
+	end component alu;
+
+	signal sys_clk, sys_res_n, do_calc, calc_done : std_ulogic;
+	signal opcode : alu_ops;
+	signal op1, op2, op3, optmp : signed(31 downto 0);
+	signal stop : boolean := false;
+begin
+	bla : alu
+	port map
+	(
+		sys_clk => sys_clk,
+		sys_res_n => sys_res_n,
+		do_calc => do_calc,
+		calc_done => calc_done,
+		op1 => op1,
+		op2 => op2,
+		op3 => op3,
+		opcode => opcode
+	);
+
+	process
+	begin
+		sys_clk <= '0';
+		wait for 15 ns;
+		sys_clk <= '1';
+		if stop = true then
+			wait;
+		end if;
+		wait for 15 ns;
+	end process;
+
+	process
+	begin
+		sys_res_n <= '0';
+		wait for 100 ns;
+		sys_res_n <= '1';
+		wait for 200 ns;
+
+		op1(31 downto 0) <= (0 => '1', 1 => '1', 2 => '1', others => '0');
+		op2(31 downto 0) <= (0 => '1', 2 => '1', others => '0');
+		opcode <= ADD;
+		wait for 30ns;
+		do_calc <= '1';
+		wait for 300ns;
+		optmp <= op3;
+		wait for 400ns;
+
+		stop <= true;
+		wait;
+	end process;
+end architecture sim;
diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
new file mode 100644
index 0000000..f2f4871
--- /dev/null
+++ b/src/gen_pkg.vhd
@@ -0,0 +1,4 @@
+package gen_pkg is
+	type alu_ops is (NOP, SUB, ADD, MUL, DIV, DONE);
+end package gen_pkg;
+