From: Uwe Hermann Date: Fri, 24 Sep 2010 18:18:20 +0000 (+0000) Subject: Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure. X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=commitdiff_plain;h=b015d02a857b27a65a3ef52839361236645754d2;p=coreboot.git Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure. Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 5988b75cd..0fc2e43a6 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -52,6 +52,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -123,6 +128,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it8712f_enable_serial does not use its 1st parameter. */ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 1b3275599..9626efa08 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -52,6 +52,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/it8718f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -122,6 +127,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 707d7f2a7..d7f8cb9c4 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 182fab8a0..a3909f479 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -46,6 +46,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -117,8 +122,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); /* Pistachio used a FPGA to enable serial debug instead of a SIO - * and it doens't require any special setup. */ + * and it doesn't require any special setup. */ uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); post_code(0x03); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 70ba6a7e0..2971a7fc8 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 76c4414b7..2ee4e4ddb 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -176,6 +181,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sio_init(); w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index ddece4550..a0725eeb5 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8712f/it8712f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -139,6 +145,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */ uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 990b30d30..9e221fc94 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -56,6 +56,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -134,6 +140,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8718f_enable_serial(0, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index aadd51e97..56133accd 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8718f_enable_serial(0, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index aad813c70..38d94a60d 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -63,6 +63,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/fintek/f71859/f71859_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -141,6 +147,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 122c12a23..24302fe19 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -67,6 +67,11 @@ static int smbus_read_byte(u32 device, u32 address); #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -146,6 +151,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 9088a48da..f8976a946 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -54,6 +54,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -125,6 +130,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dev=PNP_DEV(0x2e, W83627DHG_SP1); w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 011e455b1..063c39581 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -130,6 +135,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index fd9db8fa5..ebbea1275 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -124,6 +129,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c index fe3df8e1c..723cc2d83 100644 --- a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c +++ b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include + #ifndef SB600_DEVN_BASE #define SB600_DEVN_BASE 0 @@ -27,6 +29,11 @@ #define EHCI_BAR 0xFEF00000 #define EHCI_DEBUG_OFFSET 0xE0 +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ +} + static void sb600_enable_usbdebug(u32 port) { set_debug_port(port); diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c index 771a43a44..746cc4306 100644 --- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c +++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include + #ifndef SB700_DEVN_BASE #define SB700_DEVN_BASE 0 @@ -27,6 +29,11 @@ #define EHCI_BAR 0xFEF00000 #define EHCI_DEBUG_OFFSET 0xE0 +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ +} + static void sb700_enable_usbdebug(u32 port) { set_debug_port(port);