From: Kevin O'Connor <kevin@koconnor.net>
Date: Wed, 19 Jan 2011 06:32:35 +0000 (+0000)
Subject: Now that the VIA code is run above 1Meg (like other boards), it should
X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=commitdiff_plain;h=5bb9fd6e4dae32f86a07676228034d3828820037;p=coreboot.git

Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg.  This reduces boot time by
about 1 second on epia-cn.

This patch also adds a MTRRphysMaskValid bit definition.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 1f0bed203..c3c1cb766 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -103,7 +103,7 @@ clear_fixed_var_mtrr_out:
 	movl	$MTRRphysMask_MSR(0), %ecx
 	/* This assumes we never access addresses above 2^36 in CAR. */
 	movl	$0x0000000f, %edx
-	movl	$(~(CacheSize - 1) | 0x800), %eax
+	movl	$(~(CacheSize - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
@@ -129,7 +129,7 @@ clear_fixed_var_mtrr_out:
 
 	movl	$MTRRphysMask_MSR(1), %ecx
 	movl	$0x0000000f, %edx
-	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 
 	/* Set the default memory type and enable fixed and variable MTRRs. */
@@ -219,54 +219,27 @@ testok:
 	movl	$(MTRRdefTypeEn), %eax
 	wrmsr
 
-	/* Enable caching for first 1M using variable MTRR. */
+	/* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	xorl	%edx, %edx
-	movl	$(0 | MTRR_TYPE_WRBACK), %eax
+	movl	$(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
 	wrmsr
 
-	/*
-	 * Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
-	 * If 1M cacheable, then when S3 resume, there is stange color on
-	 * screen for 2 sec. Suppose problem of a0000-dfffff and cache.
-	 * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
-	 */
-
 	movl	$MTRRphysMask_MSR(0), %ecx
 	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
-	movl	$((~((0 + 0x80000) - 1)) | 0x800), %eax
-	wrmsr
-
-	movl	$MTRRphysBase_MSR(1), %ecx
-	xorl	%edx, %edx
-	movl	$(0x80000 | MTRR_TYPE_WRBACK), %eax
-	wrmsr
-
-	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
-	movl	$((~((0 + 0x20000) - 1)) | 0x800), %eax
-	wrmsr
-
-	movl	$MTRRphysBase_MSR(2), %ecx
-	xorl	%edx, %edx
-	movl	$(0xc0000 | MTRR_TYPE_WRBACK), %eax
-	wrmsr
-
-	movl	$MTRRphysMask_MSR(2), %ecx
-	movl	$0x0000000f, %edx	/* AMD 40 bit 0xff */
-	movl	$((~(( 0 + 0x40000) - 1)) | 0x800), %eax
+	movl	$(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 
 	/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
-	movl	$MTRRphysBase_MSR(3), %ecx
+	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
 	movl	$REAL_XIP_ROM_BASE, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	wrmsr
 
-	movl	$MTRRphysMask_MSR(3), %ecx
+	movl	$MTRRphysMask_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 
 	enable_cache()
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 734734a77..8e7beea76 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -62,7 +62,7 @@ static void enable_var_mtrr(void)
 	msr_t msr;
 
 	msr = rdmsr(MTRRdefType_MSR);
-	msr.lo |= 0x800;
+	msr.lo |= MTRRdefTypeEn;
 	wrmsr(MTRRdefType_MSR, msr);
 }
 
@@ -115,7 +115,7 @@ static void set_var_mtrr(
 
 	/* Bit 32-35 of MTRRphysMask should be set to 1 */
 	base.lo |= type;
-	mask.lo |= 0x800;
+	mask.lo |= MTRRphysMaskValid;
 	wrmsr (MTRRphysBase_MSR(reg), base);
 	wrmsr (MTRRphysMask_MSR(reg), mask);
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 164d79af2..f9aadc58a 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -21,6 +21,8 @@
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
+#define MTRRphysMaskValid	(1 << 11)
+
 #define NUM_FIXED_RANGES 88
 #define MTRRfix64K_00000_MSR 0x250
 #define MTRRfix16K_80000_MSR 0x258