From: Bernhard Urban Date: Mon, 12 Apr 2010 16:23:00 +0000 (+0200) Subject: quartusskripte: angepasst fuer webedition und tilab (weil die webedition das fpga... X-Git-Tag: review_abgabe~10 X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=commitdiff_plain;h=58c98236e04103eb6bf45a71bb4600624db0e2eb;p=hwmod.git quartusskripte: angepasst fuer webedition und tilab (weil die webedition das fpga vom labor nicht unterstuetzt) --- diff --git a/quartus/linux.sh b/quartus/linux.sh deleted file mode 100755 index b3f2718..0000000 --- a/quartus/linux.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -unset LS_COLORS -mkdir -p calc -cd calc -quartus_sh -t ../project.tcl -cd .. diff --git a/quartus/linux_tilab.sh b/quartus/linux_tilab.sh new file mode 100755 index 0000000..ebed0db --- /dev/null +++ b/quartus/linux_tilab.sh @@ -0,0 +1,6 @@ +#!/bin/sh +unset LS_COLORS +mkdir -p calc +cd calc +quartus_sh -t ../project_tilab.tcl +cd .. diff --git a/quartus/linux_web.sh b/quartus/linux_web.sh new file mode 100755 index 0000000..47b6381 --- /dev/null +++ b/quartus/linux_web.sh @@ -0,0 +1,6 @@ +#!/bin/sh +unset LS_COLORS +mkdir -p calc +cd calc +quartus_sh -t ../project_web.tcl +cd .. diff --git a/quartus/project.tcl b/quartus/project.tcl deleted file mode 100755 index 5b368b7..0000000 --- a/quartus/project.tcl +++ /dev/null @@ -1,59 +0,0 @@ -package require ::quartus::project - -set need_to_close_project 0 -set make_assignments 1 - -# Check that the right project is open -if {[is_project_open]} { - if {[string compare $quartus(project) "calc"]} { - puts "Project calc is not open" - set make_assignments 0 - } -} else { - # Only open if not already open - if {[project_exists calc]} { - project_open -revision calc calc - } else { - project_new -revision calc calc - } - set need_to_close_project 1 -} - -# Make assignments -if {$make_assignments} { - set_global_assignment -name FAMILY Stratix - set_global_assignment -name DEVICE EP1S10F672C6 - set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga - set_global_assignment -name MISC_FILE "calc.dpf" - set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" - set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" - - #set_global_assignment -name TOP_LEVEL_ENTITY calc - set_global_assignment -name TOP_LEVEL_ENTITY alu - set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd - #set_global_assignment -name VHDL_FILE ../../src/calc.vhd - set_global_assignment -name VHDL_FILE ../../src/alu.vhd - - set_location_assignment PIN_N3 -to sys_clk - set_location_assignment PIN_AF17 -to sys_res_n - - set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk - set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk - - set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" - set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # Commit assignments - export_assignments - - # Close project - if {$need_to_close_project} { - project_close - } -} diff --git a/quartus/project_tilab.tcl b/quartus/project_tilab.tcl new file mode 100755 index 0000000..e303aa4 --- /dev/null +++ b/quartus/project_tilab.tcl @@ -0,0 +1,59 @@ +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "calc"]} { + puts "Project calc is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists calc]} { + project_open -revision calc calc + } else { + project_new -revision calc calc + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY Stratix + set_global_assignment -name DEVICE EP1S25F672C6 + set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + set_global_assignment -name MISC_FILE "calc.dpf" + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" + set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + + #set_global_assignment -name TOP_LEVEL_ENTITY calc + set_global_assignment -name TOP_LEVEL_ENTITY alu + set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd + #set_global_assignment -name VHDL_FILE ../../src/calc.vhd + set_global_assignment -name VHDL_FILE ../../src/alu.vhd + + set_location_assignment PIN_N3 -to sys_clk + set_location_assignment PIN_AF17 -to sys_res_n + + set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk + set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk + + set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" + set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/quartus/project_web.tcl b/quartus/project_web.tcl new file mode 100755 index 0000000..5b368b7 --- /dev/null +++ b/quartus/project_web.tcl @@ -0,0 +1,59 @@ +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "calc"]} { + puts "Project calc is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists calc]} { + project_open -revision calc calc + } else { + project_new -revision calc calc + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY Stratix + set_global_assignment -name DEVICE EP1S10F672C6 + set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)" + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + set_global_assignment -name MISC_FILE "calc.dpf" + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" + set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + + #set_global_assignment -name TOP_LEVEL_ENTITY calc + set_global_assignment -name TOP_LEVEL_ENTITY alu + set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd + #set_global_assignment -name VHDL_FILE ../../src/calc.vhd + set_global_assignment -name VHDL_FILE ../../src/alu.vhd + + set_location_assignment PIN_N3 -to sys_clk + set_location_assignment PIN_AF17 -to sys_res_n + + set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk + set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk + + set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" + set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} diff --git a/quartus/windows.cmd b/quartus/windows.cmd deleted file mode 100644 index 41938be..0000000 --- a/quartus/windows.cmd +++ /dev/null @@ -1,4 +0,0 @@ -md calc -cd calc -quartus_sh -t ..\project.tcl -cd .. diff --git a/quartus/windows_web.cmd b/quartus/windows_web.cmd new file mode 100644 index 0000000..7953412 --- /dev/null +++ b/quartus/windows_web.cmd @@ -0,0 +1,4 @@ +md calc +cd calc +quartus_sh -t ..\project_web.tcl +cd ..