From: twisti <none@none>
Date: Tue, 23 May 2006 08:51:33 +0000 (+0000)
Subject: * src/vm/jit/x86_64/codegen.c: Changed the code generator to produce
X-Git-Url: http://wien.tomnetworks.com/gitweb/?a=commitdiff_plain;h=3b252aa22dbab2d1c727cff85cc405e44af54d32;p=cacao.git

* src/vm/jit/x86_64/codegen.c: Changed the code generator to produce
RISC-like code. These are way too much changes to name them.
(createnativestub): Bugfix in argument saving.
* src/vm/jit/x86_64/codegen.h: Likewise.
* src/vm/jit/x86_64/emit.c: Likewise.
* src/vm/jit/x86_64/md-emit.h: Likewise.
---

diff --git a/src/vm/jit/x86_64/codegen.c b/src/vm/jit/x86_64/codegen.c
index 05552636c..b4a4910ba 100644
--- a/src/vm/jit/x86_64/codegen.c
+++ b/src/vm/jit/x86_64/codegen.c
@@ -30,7 +30,7 @@
    Changes: Christian Ullrich
             Edwin Steiner
 
-   $Id: codegen.c 4941 2006-05-23 08:25:14Z twisti $
+   $Id: codegen.c 4943 2006-05-23 08:51:33Z twisti $
 
 */
 
@@ -528,10 +528,8 @@ bool codegen(jitdata *jd)
 
 			case ICMD_CHECKNULL: /* ..., objectref  ==> ..., objectref        */
 
-				if (src->flags & INMEMORY)
-					M_CMP_IMM_MEMBASE(0, REG_SP, src->regoff * 8);
-				else
-					M_TEST(src->regoff);
+				s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+				M_TEST(s1);
 				M_BEQ(0);
 				codegen_add_nullpointerexception_ref(cd);
 				break;
@@ -634,7 +632,22 @@ bool codegen(jitdata *jd)
 			break;
 
 		case ICMD_FLOAD:      /* ...  ==> ..., content of local variable      */
-		case ICMD_DLOAD:      /* op1 = local variable                         */
+		                      /* op1 = local variable                         */
+
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
+  			if ((iptr->dst->varkind == LOCALVAR) &&
+  			    (iptr->dst->varnum == iptr->op1))
+    				break;
+			var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
+			if (var->flags & INMEMORY)
+				M_FLD(d, REG_SP, var->regoff * 8);
+			else
+				M_FLTMOVE(var->regoff, d);
+			emit_store(jd, iptr, iptr->dst, d);
+			break;
+
+		case ICMD_DLOAD:      /* ...  ==> ..., content of local variable      */
+		                      /* op1 = local variable                         */
 
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
   			if ((iptr->dst->varkind == LOCALVAR) &&
@@ -679,7 +692,24 @@ bool codegen(jitdata *jd)
 			break;
 
 		case ICMD_FSTORE:     /* ..., value  ==> ...                          */
-		case ICMD_DSTORE:     /* op1 = local variable                         */
+		                      /* op1 = local variable                         */
+
+			if ((src->varkind == LOCALVAR) &&
+			    (src->varnum == iptr->op1)) {
+				break;
+			}
+			var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
+			if (var->flags & INMEMORY) {
+				s1 = emit_load_s1(jd, iptr, src, REG_FTMP1);
+				M_FST(s1, REG_SP, var->regoff * 8);
+			} else {
+				s1 = emit_load_s1(jd, iptr, src, var->regoff);
+  				M_FLTMOVE(s1, var->regoff);
+			}
+			break;
+
+		case ICMD_DSTORE:     /* ..., value  ==> ...                          */
+		                      /* op1 = local variable                         */
 
 			if ((src->varkind == LOCALVAR) &&
 			    (src->varnum == iptr->op1)) {
@@ -757,91 +787,29 @@ bool codegen(jitdata *jd)
 
 		/* integer operations *************************************************/
 
-#define RISC_STYLE 1
-
 		case ICMD_INEG:       /* ..., value  ==> ..., - value                 */
 
-#if RISC_STYLE
 			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1); 
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
 			M_INTMOVE(s1, d);
 			M_INEG(d);
 			emit_store(jd, iptr, iptr->dst, d);
-#else
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if (src->flags & INMEMORY) {
-					if (src->regoff == iptr->dst->regoff)
-						M_INEG_MEMBASE(REG_SP, iptr->dst->regoff * 8);
-					else {
-						M_ILD(REG_ITMP1, REG_SP, src->regoff * 8);
-						M_INEG(REG_ITMP1);
-						M_IST(REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-					}
-
-				} else {
-					M_IST(src->regoff, REG_SP, iptr->dst->regoff * 8);
-					M_INEG_MEMBASE(REG_SP, iptr->dst->regoff * 8);
-				}
-
-			} else {
-				if (src->flags & INMEMORY) {
-					M_ILD(iptr->dst->regoff, REG_SP, src->regoff * 8);
-					M_INEG(iptr->dst->regoff);
-
-				} else {
-					M_INTMOVE(src->regoff, iptr->dst->regoff);
-					M_INEG(iptr->dst->regoff);
-				}
-			}
-#endif
 			break;
 
 		case ICMD_LNEG:       /* ..., value  ==> ..., - value                 */
 
-#if RISC_STYLE
 			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1); 
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
 			M_INTMOVE(s1, d);
 			M_LNEG(d);
 			emit_store(jd, iptr, iptr->dst, d);
-#else
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if (src->flags & INMEMORY) {
-					if (src->regoff == iptr->dst->regoff)
-						M_LNEG_MEMBASE(REG_SP, iptr->dst->regoff * 8);
-					else {
-						M_LLD(REG_ITMP1, REG_SP, src->regoff * 8);
-						M_LNEG(REG_ITMP1);
-						M_LST(REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-					}
-
-				} else {
-					M_LST(src->regoff, REG_SP, iptr->dst->regoff * 8);
-					M_LNEG_MEMBASE(REG_SP, iptr->dst->regoff * 8);
-				}
-
-			} else {
-				if (src->flags & INMEMORY) {
-					M_LLD(iptr->dst->regoff, REG_SP, src->regoff * 8);
-					M_LNEG(iptr->dst->regoff);
-
-				} else {
-					M_INTMOVE(src->regoff, iptr->dst->regoff);
-					M_LNEG(iptr->dst->regoff);
-				}
-			}
-#endif
 			break;
 
 		case ICMD_I2L:        /* ..., value  ==> ..., value                   */
 
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP3);
-			if (src->flags & INMEMORY)
-				M_ISEXT_MEMBASE(REG_SP, src->regoff * 8, d);
-			else
-				M_ISEXT(src->regoff, d);
+			M_ISEXT(s1, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -855,435 +823,213 @@ bool codegen(jitdata *jd)
 
 		case ICMD_INT2BYTE:   /* ..., value  ==> ..., value                   */
 
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP3);
-			if (src->flags & INMEMORY)
-				M_BSEXT_MEMBASE(REG_SP, src->regoff * 8, d);
-			else
-				M_BSEXT(src->regoff, d);
+			M_BSEXT(s1, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_INT2CHAR:   /* ..., value  ==> ..., value                   */
 
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP3);
-			if (src->flags & INMEMORY)
-				M_CZEXT_MEMBASE(REG_SP, src->regoff * 8, d);
-			else
-				M_CZEXT(src->regoff, d);
+			M_CZEXT(s1, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_INT2SHORT:  /* ..., value  ==> ..., value                   */
 
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP3);
-			if (src->flags & INMEMORY)
-				M_SSEXT_MEMBASE(REG_SP, src->regoff * 8, d);
-			else
-				M_SSEXT(src->regoff, d);
+			M_SSEXT(s1, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 
 		case ICMD_IADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 
-#if RISC_STYLE
 			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
 			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
-			if (s1 == d)
-				M_IADD(s2, d);
-			else if (s2 == d)
+			if (s2 == d)
 				M_IADD(s1, d);
 			else {
 				M_INTMOVE(s1, d);
 				M_IADD(s2, d);
 			}
 			emit_store(jd, iptr, iptr->dst, d);
-#else
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialu(cd, ALU_ADD, src, iptr);
-#endif
 			break;
 
 		case ICMD_IADDCONST:  /* ..., value  ==> ..., value + constant        */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialuconst(cd, ALU_ADD, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			M_IADD_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_lalu(cd, ALU_ADD, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_LADD(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_LADD(s2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LADDCONST:  /* ..., value  ==> ..., value + constant        */
 		                      /* val.l = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_laluconst(cd, ALU_ADD, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			if (IS_IMM32(iptr->val.l))
+				M_LADD_IMM(iptr->val.l, d);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LADD(REG_ITMP2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_ISUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					if (src->prev->regoff == iptr->dst->regoff) {
-						emit_movl_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
-						emit_alul_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-					} else {
-						emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-						emit_alul_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, REG_ITMP1);
-						emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-					}
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->prev->regoff, REG_ITMP1);
-					emit_alul_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, REG_ITMP1);
-					emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					if (src->prev->regoff == iptr->dst->regoff) {
-						emit_alul_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 8);
-
-					} else {
-						emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-						emit_alul_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
-						emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-					}
-
-				} else {
-					emit_movl_reg_membase(cd, src->prev->regoff, REG_SP, iptr->dst->regoff * 8);
-					emit_alul_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 8);
-				}
-
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d) {
+				M_INTMOVE(s1, REG_ITMP1);
+				M_ISUB(s2, REG_ITMP1);
+				M_INTMOVE(REG_ITMP1, d);
 			} else {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, d);
-					emit_alul_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, d);
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->prev->regoff, d);
-					emit_alul_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, d);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					/* workaround for reg alloc */
-					if (src->regoff == iptr->dst->regoff) {
-						emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-						emit_alul_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
-						M_INTMOVE(REG_ITMP1, d);
-
-					} else {
-						emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, d);
-						emit_alul_reg_reg(cd, ALU_SUB, src->regoff, d);
-					}
-
-				} else {
-					/* workaround for reg alloc */
-					if (src->regoff == iptr->dst->regoff) {
-						M_INTMOVE(src->prev->regoff, REG_ITMP1);
-						emit_alul_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
-						M_INTMOVE(REG_ITMP1, d);
-
-					} else {
-						M_INTMOVE(src->prev->regoff, d);
-						emit_alul_reg_reg(cd, ALU_SUB, src->regoff, d);
-					}
-				}
+				M_INTMOVE(s1, d);
+				M_ISUB(s2, d);
 			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_ISUBCONST:  /* ..., value  ==> ..., value + constant        */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialuconst(cd, ALU_SUB, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			M_ISUB_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					if (src->prev->regoff == iptr->dst->regoff) {
-						emit_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
-						emit_alu_reg_membase(cd, ALU_SUB, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-					} else {
-						emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-						emit_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, REG_ITMP1);
-						emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-					}
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->prev->regoff, REG_ITMP1);
-					emit_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, REG_ITMP1);
-					emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					if (src->prev->regoff == iptr->dst->regoff) {
-						emit_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 8);
-
-					} else {
-						emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-						emit_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
-						emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-					}
-
-				} else {
-					emit_mov_reg_membase(cd, src->prev->regoff, REG_SP, iptr->dst->regoff * 8);
-					emit_alu_reg_membase(cd, ALU_SUB, src->regoff, REG_SP, iptr->dst->regoff * 8);
-				}
-
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d) {
+				M_INTMOVE(s1, REG_ITMP1);
+				M_LSUB(s2, REG_ITMP1);
+				M_INTMOVE(REG_ITMP1, d);
 			} else {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, d);
-					emit_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, d);
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->prev->regoff, d);
-					emit_alu_membase_reg(cd, ALU_SUB, REG_SP, src->regoff * 8, d);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					/* workaround for reg alloc */
-					if (src->regoff == iptr->dst->regoff) {
-						emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-						emit_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
-						M_INTMOVE(REG_ITMP1, d);
-
-					} else {
-						emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, d);
-						emit_alu_reg_reg(cd, ALU_SUB, src->regoff, d);
-					}
-
-				} else {
-					/* workaround for reg alloc */
-					if (src->regoff == iptr->dst->regoff) {
-						M_INTMOVE(src->prev->regoff, REG_ITMP1);
-						emit_alu_reg_reg(cd, ALU_SUB, src->regoff, REG_ITMP1);
-						M_INTMOVE(REG_ITMP1, d);
-
-					} else {
-						M_INTMOVE(src->prev->regoff, d);
-						emit_alu_reg_reg(cd, ALU_SUB, src->regoff, d);
-					}
-				}
+				M_INTMOVE(s1, d);
+				M_LSUB(s2, d);
 			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LSUBCONST:  /* ..., value  ==> ..., value - constant        */
 		                      /* val.l = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_laluconst(cd, ALU_SUB, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			if (IS_IMM32(iptr->val.l))
+				M_LSUB_IMM(iptr->val.l, d);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LSUB(REG_ITMP2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-					emit_imull_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
-					emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					emit_movl_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
-					emit_imull_reg_reg(cd, src->prev->regoff, REG_ITMP1);
-					emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-					emit_imull_reg_reg(cd, src->regoff, REG_ITMP1);
-					emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else {
-					M_INTMOVE(src->prev->regoff, REG_ITMP1);
-					emit_imull_reg_reg(cd, src->regoff, REG_ITMP1);
-					emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-				}
-
-			} else {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, iptr->dst->regoff);
-					emit_imull_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->prev->regoff, iptr->dst->regoff);
-					emit_imull_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->regoff, iptr->dst->regoff);
-					emit_imull_membase_reg(cd, REG_SP, src->prev->regoff * 8, iptr->dst->regoff);
-
-				} else {
-					if (src->regoff == iptr->dst->regoff) {
-						emit_imull_reg_reg(cd, src->prev->regoff, iptr->dst->regoff);
-
-					} else {
-						M_INTMOVE(src->prev->regoff, iptr->dst->regoff);
-						emit_imull_reg_reg(cd, src->regoff, iptr->dst->regoff);
-					}
-				}
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_IMUL(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_IMUL(s2, d);
 			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IMULCONST:  /* ..., value  ==> ..., value * constant        */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if (src->flags & INMEMORY) {
-					emit_imull_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 8, REG_ITMP1);
-					emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else {
-					emit_imull_imm_reg_reg(cd, iptr->val.i, src->regoff, REG_ITMP1);
-					emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-				}
-
-			} else {
-				if (src->flags & INMEMORY) {
-					emit_imull_imm_membase_reg(cd, iptr->val.i, REG_SP, src->regoff * 8, iptr->dst->regoff);
-
-				} else {
-					if (iptr->val.i == 2) {
-						M_INTMOVE(src->regoff, iptr->dst->regoff);
-						emit_alul_reg_reg(cd, ALU_ADD, iptr->dst->regoff, iptr->dst->regoff);
-
-					} else {
-						emit_imull_imm_reg_reg(cd, iptr->val.i, src->regoff, iptr->dst->regoff);    /* 3 cycles */
-					}
-				}
-			}
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			if (iptr->val.i == 2) {
+				M_INTMOVE(s1, d);
+				M_ISLL_IMM(1, d);
+			} else
+				M_IMUL_IMM(s1, iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-					emit_imul_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
-					emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					emit_mov_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
-					emit_imul_reg_reg(cd, src->prev->regoff, REG_ITMP1);
-					emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, REG_ITMP1);
-					emit_imul_reg_reg(cd, src->regoff, REG_ITMP1);
-					emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-
-				} else {
-					emit_mov_reg_reg(cd, src->prev->regoff, REG_ITMP1);
-					emit_imul_reg_reg(cd, src->regoff, REG_ITMP1);
-					emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-				}
-
-			} else {
-				if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					emit_mov_membase_reg(cd, REG_SP, src->prev->regoff * 8, iptr->dst->regoff);
-					emit_imul_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
-
-				} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->prev->regoff, iptr->dst->regoff);
-					emit_imul_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
-
-				} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-					M_INTMOVE(src->regoff, iptr->dst->regoff);
-					emit_imul_membase_reg(cd, REG_SP, src->prev->regoff * 8, iptr->dst->regoff);
-
-				} else {
-					if (src->regoff == iptr->dst->regoff) {
-						emit_imul_reg_reg(cd, src->prev->regoff, iptr->dst->regoff);
-
-					} else {
-						M_INTMOVE(src->prev->regoff, iptr->dst->regoff);
-						emit_imul_reg_reg(cd, src->regoff, iptr->dst->regoff);
-					}
-				}
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_LMUL(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_LMUL(s2, d);
 			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LMULCONST:  /* ..., value  ==> ..., value * constant        */
 		                      /* val.l = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (iptr->dst->flags & INMEMORY) {
-				if (src->flags & INMEMORY) {
-					if (IS_IMM32(iptr->val.l)) {
-						emit_imul_imm_membase_reg(cd, iptr->val.l, REG_SP, src->regoff * 8, REG_ITMP1);
-
-					} else {
-						emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-						emit_imul_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP1);
-					}
-					emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-					
-				} else {
-					if (IS_IMM32(iptr->val.l)) {
-						emit_imul_imm_reg_reg(cd, iptr->val.l, src->regoff, REG_ITMP1);
-
-					} else {
-						emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-						emit_imul_reg_reg(cd, src->regoff, REG_ITMP1);
-					}
-					emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, iptr->dst->regoff * 8);
-				}
-
-			} else {
-				if (src->flags & INMEMORY) {
-					if (IS_IMM32(iptr->val.l)) {
-						emit_imul_imm_membase_reg(cd, iptr->val.l, REG_SP, src->regoff * 8, iptr->dst->regoff);
-
-					} else {
-						emit_mov_imm_reg(cd, iptr->val.l, iptr->dst->regoff);
-						emit_imul_membase_reg(cd, REG_SP, src->regoff * 8, iptr->dst->regoff);
-					}
-
-				} else {
-					/* should match in many cases */
-					if (iptr->val.l == 2) {
-						M_INTMOVE(src->regoff, iptr->dst->regoff);
-						emit_alul_reg_reg(cd, ALU_ADD, iptr->dst->regoff, iptr->dst->regoff);
-
-					} else {
-						if (IS_IMM32(iptr->val.l)) {
-							emit_imul_imm_reg_reg(cd, iptr->val.l, src->regoff, iptr->dst->regoff);    /* 4 cycles */
-
-						} else {
-							emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-							M_INTMOVE(src->regoff, iptr->dst->regoff);
-							emit_imul_reg_reg(cd, REG_ITMP1, iptr->dst->regoff);
-						}
-					}
-				}
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			if (IS_IMM32(iptr->val.l))
+				M_LMUL_IMM(s1, iptr->val.l, d);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_INTMOVE(s1, d);
+				M_LMUL(REG_ITMP2, d);
 			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
 
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-	        if (src->prev->flags & INMEMORY) {
-				emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, RAX);
-
-			} else {
+	        if (src->prev->flags & INMEMORY)
+				M_ILD(RAX, REG_SP, src->prev->regoff * 8);
+			else
 				M_INTMOVE(src->prev->regoff, RAX);
-			}
 			
-			if (src->flags & INMEMORY) {
-				emit_movl_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP3);
-
-			} else {
+			if (src->flags & INMEMORY)
+				M_ILD(REG_ITMP3, REG_SP, src->regoff * 8);
+			else
 				M_INTMOVE(src->regoff, REG_ITMP3);
+
+			if (checknull) {
+				M_ITEST(REG_ITMP3);
+				M_BEQ(0);
+				codegen_add_arithmeticexception_ref(cd);
 			}
-			gen_div_check(src);
 
 			emit_alul_imm_reg(cd, ALU_CMP, 0x80000000, RAX); /* check as described in jvm spec */
 			emit_jcc(cd, CC_NE, 4 + 6);
@@ -1308,21 +1054,23 @@ bool codegen(jitdata *jd)
 			break;
 
 		case ICMD_IREM:       /* ..., val1, val2  ==> ..., val1 % val2        */
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (src->prev->flags & INMEMORY) {
-				emit_movl_membase_reg(cd, REG_SP, src->prev->regoff * 8, RAX);
 
-			} else {
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
+			if (src->prev->flags & INMEMORY)
+				M_ILD(RAX, REG_SP, src->prev->regoff * 8);
+			else
 				M_INTMOVE(src->prev->regoff, RAX);
-			}
 			
-			if (src->flags & INMEMORY) {
-				emit_movl_membase_reg(cd, REG_SP, src->regoff * 8, REG_ITMP3);
-
-			} else {
+			if (src->flags & INMEMORY)
+				M_ILD(REG_ITMP3, REG_SP, src->regoff * 8);
+			else
 				M_INTMOVE(src->regoff, REG_ITMP3);
+
+			if (checknull) {
+				M_ITEST(REG_ITMP3);
+				M_BEQ(0);
+				codegen_add_arithmeticexception_ref(cd);
 			}
-			gen_div_check(src);
 
 			emit_mov_reg_reg(cd, RDX, REG_ITMP2); /* save %rdx, cause it's an argument register */
 
@@ -1384,26 +1132,27 @@ bool codegen(jitdata *jd)
 
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
 
-	        if (src->prev->flags & INMEMORY) {
+	        if (src->prev->flags & INMEMORY)
 				M_LLD(RAX, REG_SP, src->prev->regoff * 8);
-
-			} else {
+			else
 				M_INTMOVE(src->prev->regoff, RAX);
-			}
 			
-			if (src->flags & INMEMORY) {
+			if (src->flags & INMEMORY)
 				M_LLD(REG_ITMP3, REG_SP, src->regoff * 8);
-
-			} else {
+			else
 				M_INTMOVE(src->regoff, REG_ITMP3);
+
+			if (checknull) {
+				M_TEST(REG_ITMP3);
+				M_BEQ(0);
+				codegen_add_arithmeticexception_ref(cd);
 			}
-			gen_div_check(src);
 
 			/* check as described in jvm spec */
 			disp = dseg_adds8(cd, 0x8000000000000000LL);
-  			M_CMP_MEMBASE(RIP, -(((ptrint) cd->mcodeptr + 7) - (ptrint) cd->mcodebase) + disp, RAX);
+  			M_LCMP_MEMBASE(RIP, -(((ptrint) cd->mcodeptr + 7) - (ptrint) cd->mcodebase) + disp, RAX);
 			M_BNE(4 + 6);
-			M_CMP_IMM(-1, REG_ITMP3);                              /* 4 bytes */
+			M_LCMP_IMM(-1, REG_ITMP3);                              /* 4 bytes */
 			M_BEQ(3 + 2 + 3);                                      /* 6 bytes */
 
 			M_MOV(RDX, REG_ITMP2); /* save %rdx, cause it's an argument register */
@@ -1426,33 +1175,34 @@ bool codegen(jitdata *jd)
 		case ICMD_LREM:       /* ..., val1, val2  ==> ..., val1 % val2        */
 
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			if (src->prev->flags & INMEMORY) {
+			if (src->prev->flags & INMEMORY)
 				M_LLD(REG_ITMP1, REG_SP, src->prev->regoff * 8);
-
-			} else {
+			else
 				M_INTMOVE(src->prev->regoff, REG_ITMP1);
-			}
 			
-			if (src->flags & INMEMORY) {
+			if (src->flags & INMEMORY)
 				M_LLD(REG_ITMP3, REG_SP, src->regoff * 8);
-
-			} else {
+			else
 				M_INTMOVE(src->regoff, REG_ITMP3);
+
+			if (checknull) {
+				M_ITEST(REG_ITMP3);
+				M_BEQ(0);
+				codegen_add_arithmeticexception_ref(cd);
 			}
-			gen_div_check(src);
 
 			M_MOV(RDX, REG_ITMP2); /* save %rdx, cause it's an argument register */
 
 			/* check as described in jvm spec */
 			disp = dseg_adds8(cd, 0x8000000000000000LL);
-  			M_CMP_MEMBASE(RIP, -(((ptrint) cd->mcodeptr + 7) - (ptrint) cd->mcodebase) + disp, REG_ITMP1);
+  			M_LCMP_MEMBASE(RIP, -(((ptrint) cd->mcodeptr + 7) - (ptrint) cd->mcodebase) + disp, REG_ITMP1);
 			M_BNE(3 + 4 + 6);
 
 #if 0
 			emit_alul_reg_reg(cd, ALU_XOR, RDX, RDX);         /* 2 bytes */
 #endif
-			M_XOR(RDX, RDX);                                       /* 3 bytes */
-			M_CMP_IMM(-1, REG_ITMP3);                              /* 4 bytes */
+			M_LXOR(RDX, RDX);                                      /* 3 bytes */
+			M_LCMP_IMM(-1, REG_ITMP3);                              /* 4 bytes */
 			M_BEQ(2 + 3);                                          /* 6 bytes */
 
   			emit_cqto(cd);
@@ -1509,8 +1259,11 @@ bool codegen(jitdata *jd)
 		case ICMD_ISHLCONST:  /* ..., value  ==> ..., value << constant       */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ishiftconst(cd, SHIFT_SHL, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			M_ISLL_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_ISHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
@@ -1522,8 +1275,11 @@ bool codegen(jitdata *jd)
 		case ICMD_ISHRCONST:  /* ..., value  ==> ..., value >> constant       */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ishiftconst(cd, SHIFT_SAR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			M_INTMOVE(s1, d);
+			M_ISRA_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
@@ -1535,8 +1291,11 @@ bool codegen(jitdata *jd)
 		case ICMD_IUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ishiftconst(cd, SHIFT_SHR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			M_INTMOVE(s1, d);
+			M_ISRL_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LSHL:       /* ..., val1, val2  ==> ..., val1 << val2       */
@@ -1548,8 +1307,11 @@ bool codegen(jitdata *jd)
         case ICMD_LSHLCONST:  /* ..., value  ==> ..., value << constant       */
  			                  /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_lshiftconst(cd, SHIFT_SHL, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			M_LSLL_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LSHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
@@ -1561,8 +1323,11 @@ bool codegen(jitdata *jd)
 		case ICMD_LSHRCONST:  /* ..., value  ==> ..., value >> constant       */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_lshiftconst(cd, SHIFT_SAR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			M_INTMOVE(s1, d);
+			M_LSRA_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
@@ -1574,119 +1339,190 @@ bool codegen(jitdata *jd)
   		case ICMD_LUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
   		                      /* val.l = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_lshiftconst(cd, SHIFT_SHR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			M_INTMOVE(s1, d);
+			M_LSRL_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IAND:       /* ..., val1, val2  ==> ..., val1 & val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialu(cd, ALU_AND, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_IAND(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_IAND(s2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IANDCONST:  /* ..., value  ==> ..., value & constant        */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialuconst(cd, ALU_AND, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			M_IAND_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LAND:       /* ..., val1, val2  ==> ..., val1 & val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_lalu(cd, ALU_AND, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_LAND(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_LAND(s2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LANDCONST:  /* ..., value  ==> ..., value & constant        */
 		                      /* val.l = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_laluconst(cd, ALU_AND, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			if (IS_IMM32(iptr->val.l))
+				M_LAND_IMM(iptr->val.l, d);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LAND(REG_ITMP2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IOR:        /* ..., val1, val2  ==> ..., val1 | val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialu(cd, ALU_OR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_IOR(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_IOR(s2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IORCONST:   /* ..., value  ==> ..., value | constant        */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialuconst(cd, ALU_OR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			M_IOR_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LOR:        /* ..., val1, val2  ==> ..., val1 | val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_lalu(cd, ALU_OR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_LOR(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_LOR(s2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LORCONST:   /* ..., value  ==> ..., value | constant        */
 		                      /* val.l = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_laluconst(cd, ALU_OR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			if (IS_IMM32(iptr->val.l))
+				M_LOR_IMM(iptr->val.l, d);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LOR(REG_ITMP2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IXOR:       /* ..., val1, val2  ==> ..., val1 ^ val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialu(cd, ALU_XOR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_IXOR(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_IXOR(s2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_IXORCONST:  /* ..., value  ==> ..., value ^ constant        */
 		                      /* val.i = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_ialuconst(cd, ALU_XOR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			M_IXOR_IMM(iptr->val.i, d);
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LXOR:       /* ..., val1, val2  ==> ..., val1 ^ val2        */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_lalu(cd, ALU_XOR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+			if (s2 == d)
+				M_LXOR(s1, d);
+			else {
+				M_INTMOVE(s1, d);
+				M_LXOR(s2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_LXORCONST:  /* ..., value  ==> ..., value ^ constant        */
 		                      /* val.l = constant                             */
 
-			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_NULL);
-			emit_laluconst(cd, ALU_XOR, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
+			M_INTMOVE(s1, d);
+			if (IS_IMM32(iptr->val.l))
+				M_LXOR_IMM(iptr->val.l, d);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LXOR(REG_ITMP2, d);
+			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 
 		case ICMD_IINC:       /* ..., value  ==> ..., value + constant        */
 		                      /* op1 = variable, val.i = constant             */
 
-			/* using inc and dec is definitely faster than add -- tested      */
-			/* with sieve                                                     */
-
 			var = &(rd->locals[iptr->op1][TYPE_INT]);
-			d = var->regoff;
 			if (var->flags & INMEMORY) {
-				if (iptr->val.i == 1) {
-					emit_incl_membase(cd, REG_SP, d * 8);
- 
-				} else if (iptr->val.i == -1) {
-					emit_decl_membase(cd, REG_SP, d * 8);
+				s1 = REG_ITMP1;
+				M_ILD(s1, REG_SP, var->regoff * 8);
+			} else
+				s1 = var->regoff;
 
-				} else {
-					emit_alul_imm_membase(cd, ALU_ADD, iptr->val.i, REG_SP, d * 8);
-				}
+			/* Using inc and dec is not faster than add (tested with
+			   sieve). */
 
-			} else {
-				if (iptr->val.i == 1) {
-					emit_incl_reg(cd, d);
- 
-				} else if (iptr->val.i == -1) {
-					emit_decl_reg(cd, d);
+			M_IADD_IMM(iptr->val.i, s1);
 
-				} else {
-					emit_alul_imm_reg(cd, ALU_ADD, iptr->val.i, d);
-				}
-			}
+			if (var->flags & INMEMORY)
+				M_IST(s1, REG_SP, var->regoff * 8);
 			break;
 
 
@@ -1719,13 +1555,11 @@ bool codegen(jitdata *jd)
 			s1 = emit_load_s1(jd, iptr, src->prev, REG_FTMP1);
 			s2 = emit_load_s2(jd, iptr, src, REG_FTMP2);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3);
-			if (s1 == d) {
-				emit_addss_reg_reg(cd, s2, d);
-			} else if (s2 == d) {
-				emit_addss_reg_reg(cd, s1, d);
-			} else {
+			if (s2 == d)
+				M_FADD(s1, d);
+			else {
 				M_FLTMOVE(s1, d);
-				emit_addss_reg_reg(cd, s2, d);
+				M_FADD(s2, d);
 			}
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1735,13 +1569,11 @@ bool codegen(jitdata *jd)
 			s1 = emit_load_s1(jd, iptr, src->prev, REG_FTMP1);
 			s2 = emit_load_s2(jd, iptr, src, REG_FTMP2);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3);
-			if (s1 == d) {
-				emit_addsd_reg_reg(cd, s2, d);
-			} else if (s2 == d) {
-				emit_addsd_reg_reg(cd, s1, d);
-			} else {
+			if (s2 == d)
+				M_DADD(s1, d);
+			else {
 				M_FLTMOVE(s1, d);
-				emit_addsd_reg_reg(cd, s2, d);
+				M_DADD(s2, d);
 			}
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1756,7 +1588,7 @@ bool codegen(jitdata *jd)
 				s2 = REG_FTMP2;
 			}
 			M_FLTMOVE(s1, d);
-			emit_subss_reg_reg(cd, s2, d);
+			M_FSUB(s2, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -1770,7 +1602,7 @@ bool codegen(jitdata *jd)
 				s2 = REG_FTMP2;
 			}
 			M_FLTMOVE(s1, d);
-			emit_subsd_reg_reg(cd, s2, d);
+			M_DSUB(s2, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -1779,13 +1611,11 @@ bool codegen(jitdata *jd)
 			s1 = emit_load_s1(jd, iptr, src->prev, REG_FTMP1);
 			s2 = emit_load_s2(jd, iptr, src, REG_FTMP2);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3);
-			if (s1 == d) {
-				emit_mulss_reg_reg(cd, s2, d);
-			} else if (s2 == d) {
-				emit_mulss_reg_reg(cd, s1, d);
-			} else {
+			if (s2 == d)
+				M_FMUL(s1, d);
+			else {
 				M_FLTMOVE(s1, d);
-				emit_mulss_reg_reg(cd, s2, d);
+				M_FMUL(s2, d);
 			}
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1795,13 +1625,11 @@ bool codegen(jitdata *jd)
 			s1 = emit_load_s1(jd, iptr, src->prev, REG_FTMP1);
 			s2 = emit_load_s2(jd, iptr, src, REG_FTMP2);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3);
-			if (s1 == d) {
-				emit_mulsd_reg_reg(cd, s2, d);
-			} else if (s2 == d) {
-				emit_mulsd_reg_reg(cd, s1, d);
-			} else {
+			if (s2 == d)
+				M_DMUL(s1, d);
+			else {
 				M_FLTMOVE(s1, d);
-				emit_mulsd_reg_reg(cd, s2, d);
+				M_DMUL(s2, d);
 			}
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1816,7 +1644,7 @@ bool codegen(jitdata *jd)
 				s2 = REG_FTMP2;
 			}
 			M_FLTMOVE(s1, d);
-			emit_divss_reg_reg(cd, s2, d);
+			M_FDIV(s2, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -1830,7 +1658,7 @@ bool codegen(jitdata *jd)
 				s2 = REG_FTMP2;
 			}
 			M_FLTMOVE(s1, d);
-			emit_divsd_reg_reg(cd, s2, d);
+			M_DDIV(s2, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -1838,7 +1666,7 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
-			emit_cvtsi2ss_reg_reg(cd, s1, d);
+			M_CVTIF(s1, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -1846,7 +1674,7 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
-			emit_cvtsi2sd_reg_reg(cd, s1, d);
+			M_CVTID(s1, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -1854,7 +1682,7 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
-			emit_cvtsi2ssq_reg_reg(cd, s1, d);
+			M_CVTLF(s1, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
 			
@@ -1862,7 +1690,7 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
-			emit_cvtsi2sdq_reg_reg(cd, s1, d);
+			M_CVTLD(s1, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
 			
@@ -1870,13 +1698,14 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_FTMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-			emit_cvttss2si_reg_reg(cd, s1, d);
-			emit_alul_imm_reg(cd, ALU_CMP, 0x80000000, d);    /* corner cases */
-			a = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 + ((REG_RESULT == d) ? 0 : 3);
-			emit_jcc(cd, CC_NE, a);
+			M_CVTFI(s1, d);
+			M_ICMP_IMM(0x80000000, d);                        /* corner cases */
+			disp = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 +
+				((REG_RESULT == d) ? 0 : 3);
+			M_BNE(disp);
 			M_FLTMOVE(s1, REG_FTMP1);
-			emit_mov_imm_reg(cd, (ptrint) asm_builtin_f2i, REG_ITMP2);
-			emit_call_reg(cd, REG_ITMP2);
+			M_MOV_IMM(asm_builtin_f2i, REG_ITMP2);
+			M_CALL(REG_ITMP2);
 			M_INTMOVE(REG_RESULT, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1885,13 +1714,14 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_FTMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-			emit_cvttsd2si_reg_reg(cd, s1, d);
-			emit_alul_imm_reg(cd, ALU_CMP, 0x80000000, d);    /* corner cases */
-			a = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 + ((REG_RESULT == d) ? 0 : 3);
-			emit_jcc(cd, CC_NE, a);
+			M_CVTDI(s1, d);
+			M_ICMP_IMM(0x80000000, d);                        /* corner cases */
+			disp = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 +
+				((REG_RESULT == d) ? 0 : 3);
+			M_BNE(disp);
 			M_FLTMOVE(s1, REG_FTMP1);
-			emit_mov_imm_reg(cd, (ptrint) asm_builtin_d2i, REG_ITMP2);
-			emit_call_reg(cd, REG_ITMP2);
+			M_MOV_IMM(asm_builtin_d2i, REG_ITMP2);
+			M_CALL(REG_ITMP2);
 			M_INTMOVE(REG_RESULT, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1900,14 +1730,15 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_FTMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-			emit_cvttss2siq_reg_reg(cd, s1, d);
-			emit_mov_imm_reg(cd, 0x8000000000000000, REG_ITMP2);
-			emit_alu_reg_reg(cd, ALU_CMP, REG_ITMP2, d);     /* corner cases */
-			a = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 + ((REG_RESULT == d) ? 0 : 3);
-			emit_jcc(cd, CC_NE, a);
+			M_CVTFL(s1, d);
+			M_MOV_IMM(0x8000000000000000, REG_ITMP2);
+			M_LCMP(REG_ITMP2, d);                             /* corner cases */
+			disp = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 +
+				((REG_RESULT == d) ? 0 : 3);
+			M_BNE(disp);
 			M_FLTMOVE(s1, REG_FTMP1);
-			emit_mov_imm_reg(cd, (ptrint) asm_builtin_f2l, REG_ITMP2);
-			emit_call_reg(cd, REG_ITMP2);
+			M_MOV_IMM(asm_builtin_f2l, REG_ITMP2);
+			M_CALL(REG_ITMP2);
 			M_INTMOVE(REG_RESULT, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1916,14 +1747,15 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_FTMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-			emit_cvttsd2siq_reg_reg(cd, s1, d);
-			emit_mov_imm_reg(cd, 0x8000000000000000, REG_ITMP2);
-			emit_alu_reg_reg(cd, ALU_CMP, REG_ITMP2, d);     /* corner cases */
-			a = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 + ((REG_RESULT == d) ? 0 : 3);
-			emit_jcc(cd, CC_NE, a);
+			M_CVTDL(s1, d);
+			M_MOV_IMM(0x8000000000000000, REG_ITMP2);
+			M_LCMP(REG_ITMP2, d);                             /* corner cases */
+			disp = ((s1 == REG_FTMP1) ? 0 : 5) + 10 + 3 +
+				((REG_RESULT == d) ? 0 : 3);
+			M_BNE(disp);
 			M_FLTMOVE(s1, REG_FTMP1);
-			emit_mov_imm_reg(cd, (ptrint) asm_builtin_d2l, REG_ITMP2);
-			emit_call_reg(cd, REG_ITMP2);
+			M_MOV_IMM(asm_builtin_d2l, REG_ITMP2);
+			M_CALL(REG_ITMP2);
 			M_INTMOVE(REG_RESULT, d);
   			emit_store(jd, iptr, iptr->dst, d);
 			break;
@@ -1932,7 +1764,7 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_FTMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3);
-			emit_cvtss2sd_reg_reg(cd, s1, d);
+			M_CVTFD(s1, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -1940,7 +1772,7 @@ bool codegen(jitdata *jd)
 
 			s1 = emit_load_s1(jd, iptr, src, REG_FTMP1);
 			d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP3);
-			emit_cvtsd2ss_reg_reg(cd, s1, d);
+			M_CVTDF(s1, d);
 			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
@@ -2345,32 +2177,29 @@ bool codegen(jitdata *jd)
 			/* This approach is much faster than moving the field
 			   address inline into a register. */
 
-  			M_ALD(REG_ITMP2, RIP, -(((ptrint) cd->mcodeptr + 7) -
+  			M_ALD(REG_ITMP1, RIP, -(((ptrint) cd->mcodeptr + 7) -
 									(ptrint) cd->mcodebase) + disp);
 
 			switch (iptr->op1) {
 			case TYPE_INT:
-				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-				M_ILD(d, REG_ITMP2, 0);
-				emit_store(jd, iptr, iptr->dst, d);
+				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+				M_ILD(d, REG_ITMP1, 0);
 				break;
 			case TYPE_LNG:
 			case TYPE_ADR:
-				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-				M_LLD(d, REG_ITMP2, 0);
-				emit_store(jd, iptr, iptr->dst, d);
+				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP2);
+				M_LLD(d, REG_ITMP1, 0);
 				break;
 			case TYPE_FLT:
-				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-				emit_movss_membase_reg(cd, REG_ITMP2, 0, d);
-				emit_store(jd, iptr, iptr->dst, d);
+				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
+				M_FLD(d, REG_ITMP1, 0);
 				break;
 			case TYPE_DBL:				
-				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
-				emit_movsd_membase_reg(cd, REG_ITMP2, 0, d);
-				emit_store(jd, iptr, iptr->dst, d);
+				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
+				M_DLD(d, REG_ITMP1, 0);
 				break;
 			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_PUTSTATIC:  /* ..., value  ==> ...                          */
@@ -2411,26 +2240,26 @@ bool codegen(jitdata *jd)
 			/* This approach is much faster than moving the field
 			   address inline into a register. */
 
-  			M_ALD(REG_ITMP2, RIP, -(((ptrint) cd->mcodeptr + 7) -
+  			M_ALD(REG_ITMP1, RIP, -(((ptrint) cd->mcodeptr + 7) -
 									(ptrint) cd->mcodebase) + disp);
 
 			switch (iptr->op1) {
 			case TYPE_INT:
-				s2 = emit_load_s2(jd, iptr, src, REG_ITMP1);
-				M_IST(s2, REG_ITMP2, 0);
+				s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+				M_IST(s2, REG_ITMP1, 0);
 				break;
 			case TYPE_LNG:
 			case TYPE_ADR:
-				s2 = emit_load_s2(jd, iptr, src, REG_ITMP1);
-				M_LST(s2, REG_ITMP2, 0);
+				s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+				M_LST(s2, REG_ITMP1, 0);
 				break;
 			case TYPE_FLT:
 				s2 = emit_load_s2(jd, iptr, src, REG_FTMP1);
-				emit_movss_reg_membase(cd, s2, REG_ITMP2, 0);
+				M_FST(s2, REG_ITMP1, 0);
 				break;
 			case TYPE_DBL:
 				s2 = emit_load_s2(jd, iptr, src, REG_FTMP1);
-				emit_movsd_reg_membase(cd, s2, REG_ITMP2, 0);
+				M_DST(s2, REG_ITMP1, 0);
 				break;
 			}
 			break;
@@ -2486,9 +2315,9 @@ bool codegen(jitdata *jd)
 			case TYPE_LNG:
 			case TYPE_ADR:
 			case TYPE_DBL:
-				if (IS_IMM32(iptr->val.l)) {
+				if (IS_IMM32(iptr->val.l))
 					M_LST_IMM32(iptr->val.l, REG_ITMP1, 0);
-				} else {
+				else {
 					M_IST_IMM(iptr->val.l, REG_ITMP1, 0);
 					M_IST_IMM(iptr->val.l >> 32, REG_ITMP1, 4);
 				}
@@ -2516,33 +2345,29 @@ bool codegen(jitdata *jd)
 
 				disp = 0;
 
-			} else {
+			} else
 				disp = INSTRUCTION_RESOLVED_FIELDINFO(iptr)->offset;
-			}
 
 			switch (iptr->op1) {
 			case TYPE_INT:
 				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
 				M_ILD32(d, s1, disp);
-				emit_store(jd, iptr, iptr->dst, d);
 				break;
 			case TYPE_LNG:
 			case TYPE_ADR:
 				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_ITMP1);
 				M_LLD32(d, s1, disp);
-				emit_store(jd, iptr, iptr->dst, d);
 				break;
 			case TYPE_FLT:
 				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
-				emit_movss_membase32_reg(cd, s1, disp, d);
-				emit_store(jd, iptr, iptr->dst, d);
+				M_FLD32(d, s1, disp);
 				break;
 			case TYPE_DBL:				
 				d = codegen_reg_of_var(rd, iptr->opc, iptr->dst, REG_FTMP1);
-				emit_movsd_membase32_reg(cd, s1, disp, d);
-				emit_store(jd, iptr, iptr->dst, d);
+				M_DLD32(d, s1, disp);
 				break;
 			}
+			emit_store(jd, iptr, iptr->dst, d);
 			break;
 
 		case ICMD_PUTFIELD:   /* ..., objectref, value  ==> ...               */
@@ -2551,11 +2376,10 @@ bool codegen(jitdata *jd)
 			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
 			gen_nullptr_check(s1);
 
-			if (IS_INT_LNG_TYPE(iptr->op1)) {
+			if (IS_INT_LNG_TYPE(iptr->op1))
 				s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
-			} else {
+			else
 				s2 = emit_load_s2(jd, iptr, src, REG_FTMP2);
-			}
 
 			if (INSTRUCTION_IS_UNRESOLVED(iptr)) {
 /* 				PROFILE_CYCLE_STOP; */
@@ -2571,9 +2395,8 @@ bool codegen(jitdata *jd)
 
 				disp = 0;
 
-			} else {
+			} else
 				disp = INSTRUCTION_RESOLVED_FIELDINFO(iptr)->offset;
-			}
 
 			switch (iptr->op1) {
 			case TYPE_INT:
@@ -2584,10 +2407,10 @@ bool codegen(jitdata *jd)
 				M_LST32(s2, s1, disp);
 				break;
 			case TYPE_FLT:
-				emit_movss_reg_membase32(cd, s2, s1, disp);
+				M_FST32(s2, s1, disp);
 				break;
 			case TYPE_DBL:
-				emit_movsd_reg_membase32(cd, s2, s1, disp);
+				M_DST32(s2, s1, disp);
 				break;
 			}
 			break;
@@ -2614,9 +2437,8 @@ bool codegen(jitdata *jd)
 
 				disp = 0;
 
-			} else {
+			} else
 				disp = INSTRUCTION_RESOLVED_FIELDINFO(iptr + 1)->offset;
-			}
 
 			switch (iptr->op1) {
 			case TYPE_INT:
@@ -2688,186 +2510,277 @@ bool codegen(jitdata *jd)
 		case ICMD_IFNULL:       /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc                     */
 
-			if (src->flags & INMEMORY)
-				M_CMP_IMM_MEMBASE(0, REG_SP, src->regoff * 8);
-			else
-				M_TEST(src->regoff);
-
-			/* If the conditional branch is part of an if-converted
-			   block, don't generate the actual branch. */
-
-			if ((iptr->opc & ICMD_CONDITION_MASK) == 0) {
-				M_BEQ(0);
-				codegen_addreference(cd, (basicblock *) iptr->target);
-			}
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			M_TEST(s1);
+			M_BEQ(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IFNONNULL:    /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc                     */
 
-			if (src->flags & INMEMORY)
-				M_CMP_IMM_MEMBASE(0, REG_SP, src->regoff * 8);
-			else
-				M_TEST(src->regoff);
-
-			/* If the conditional branch is part of an if-converted
-			   block, don't generate the actual branch. */
-
-			if ((iptr->opc & ICMD_CONDITION_MASK) == 0) {
-				M_BNE(0);
-				codegen_addreference(cd, (basicblock *) iptr->target);
-			}
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			M_TEST(s1);
+			M_BNE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IFEQ:         /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.i = constant   */
 
-			emit_ifcc(cd, CC_E, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			M_ICMP_IMM(iptr->val.i, s1);
+			M_BEQ(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IFLT:         /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.i = constant   */
 
-#if RISC_STYLE
 			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 			M_ICMP_IMM(iptr->val.i, s1);
 			M_BLT(0);
 			codegen_addreference(cd, (basicblock *) iptr->target);
-#else
-			emit_ifcc(cd, CC_L, src, iptr);
-#endif
 			break;
 
 		case ICMD_IFLE:         /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.i = constant   */
 
-			emit_ifcc(cd, CC_LE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			M_ICMP_IMM(iptr->val.i, s1);
+			M_BLE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IFNE:         /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.i = constant   */
 
-			emit_ifcc(cd, CC_NE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			M_ICMP_IMM(iptr->val.i, s1);
+			M_BNE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IFGT:         /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.i = constant   */
 
-			emit_ifcc(cd, CC_G, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			M_ICMP_IMM(iptr->val.i, s1);
+			M_BGT(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IFGE:         /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.i = constant   */
 
-			emit_ifcc(cd, CC_GE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			M_ICMP_IMM(iptr->val.i, s1);
+			M_BGE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LEQ:       /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.l = constant   */
 
-			emit_if_lcc(cd, CC_E, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			if (IS_IMM32(iptr->val.l))
+				M_LCMP_IMM(iptr->val.l, s1);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LCMP(REG_ITMP2, s1);
+			}
+			M_BEQ(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LLT:       /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.l = constant   */
 
-			emit_if_lcc(cd, CC_L, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			if (IS_IMM32(iptr->val.l))
+				M_LCMP_IMM(iptr->val.l, s1);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LCMP(REG_ITMP2, s1);
+			}
+			M_BLT(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LLE:       /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.l = constant   */
 
-			emit_if_lcc(cd, CC_LE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			if (IS_IMM32(iptr->val.l))
+				M_LCMP_IMM(iptr->val.l, s1);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LCMP(REG_ITMP2, s1);
+			}
+			M_BLE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LNE:       /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.l = constant   */
 
-			emit_if_lcc(cd, CC_NE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			if (IS_IMM32(iptr->val.l))
+				M_LCMP_IMM(iptr->val.l, s1);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LCMP(REG_ITMP2, s1);
+			}
+			M_BNE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LGT:       /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.l = constant   */
 
-			emit_if_lcc(cd, CC_G, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			if (IS_IMM32(iptr->val.l))
+				M_LCMP_IMM(iptr->val.l, s1);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LCMP(REG_ITMP2, s1);
+			}
+			M_BGT(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LGE:       /* ..., value ==> ...                         */
 		                        /* op1 = target JavaVM pc, val.l = constant   */
 
-			emit_if_lcc(cd, CC_GE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+			if (IS_IMM32(iptr->val.l))
+				M_LCMP_IMM(iptr->val.l, s1);
+			else {
+				M_MOV_IMM(iptr->val.l, REG_ITMP2);
+				M_LCMP(REG_ITMP2, s1);
+			}
+			M_BGE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_ICMPEQ:    /* ..., value, value ==> ...                  */
 		                        /* op1 = target JavaVM pc                     */
 
-			emit_if_icmpcc(cd, CC_E, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_ICMP(s2, s1);
+			M_BEQ(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LCMPEQ:    /* ..., value, value ==> ...                  */
 		case ICMD_IF_ACMPEQ:    /* op1 = target JavaVM pc                     */
 
-			emit_if_lcmpcc(cd, CC_E, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_LCMP(s2, s1);
+			M_BEQ(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_ICMPNE:    /* ..., value, value ==> ...                  */
 		                        /* op1 = target JavaVM pc                     */
 
-			emit_if_icmpcc(cd, CC_NE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_ICMP(s2, s1);
+			M_BNE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LCMPNE:    /* ..., value, value ==> ...                  */
 		case ICMD_IF_ACMPNE:    /* op1 = target JavaVM pc                     */
 
-			emit_if_lcmpcc(cd, CC_NE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_LCMP(s2, s1);
+			M_BNE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_ICMPLT:    /* ..., value, value ==> ...                  */
 		                        /* op1 = target JavaVM pc                     */
 
-			emit_if_icmpcc(cd, CC_L, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_ICMP(s2, s1);
+			M_BLT(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LCMPLT:    /* ..., value, value ==> ...                  */
 	                            /* op1 = target JavaVM pc                     */
 
-			emit_if_lcmpcc(cd, CC_L, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_LCMP(s2, s1);
+			M_BLT(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_ICMPGT:    /* ..., value, value ==> ...                  */
 		                        /* op1 = target JavaVM pc                     */
 
-			emit_if_icmpcc(cd, CC_G, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_ICMP(s2, s1);
+			M_BGT(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LCMPGT:    /* ..., value, value ==> ...                  */
                                 /* op1 = target JavaVM pc                     */
 
-			emit_if_lcmpcc(cd, CC_G, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_LCMP(s2, s1);
+			M_BGT(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_ICMPLE:    /* ..., value, value ==> ...                  */
 		                        /* op1 = target JavaVM pc                     */
 
-			emit_if_icmpcc(cd, CC_LE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_ICMP(s2, s1);
+			M_BLE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LCMPLE:    /* ..., value, value ==> ...                  */
 		                        /* op1 = target JavaVM pc                     */
 
-			emit_if_lcmpcc(cd, CC_LE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_LCMP(s2, s1);
+			M_BLE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_ICMPGE:    /* ..., value, value ==> ...                  */
 		                        /* op1 = target JavaVM pc                     */
 
-			emit_if_icmpcc(cd, CC_GE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_ICMP(s2, s1);
+			M_BGE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		case ICMD_IF_LCMPGE:    /* ..., value, value ==> ...                  */
 	                            /* op1 = target JavaVM pc                     */
 
-			emit_if_lcmpcc(cd, CC_GE, src, iptr);
+			s1 = emit_load_s1(jd, iptr, src->prev, REG_ITMP1);
+			s2 = emit_load_s2(jd, iptr, src, REG_ITMP2);
+			M_LCMP(s2, s1);
+			M_BGE(0);
+			codegen_addreference(cd, (basicblock *) iptr->target);
 			break;
 
 		/* (value xx 0) ? IFxx_ICONST : ELSE_ICONST                           */
@@ -3063,14 +2976,15 @@ nowperformreturn:
 
 				s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
 				M_INTMOVE(s1, REG_ITMP1);
-				if (l != 0) {
-					emit_alul_imm_reg(cd, ALU_SUB, l, REG_ITMP1);
-				}
+
+				if (l != 0)
+					M_ISUB_IMM(l, REG_ITMP1);
+
 				i = i - l + 1;
 
                 /* range check */
-				emit_alul_imm_reg(cd, ALU_CMP, i - 1, REG_ITMP1);
-				emit_jcc(cd, CC_A, 0);
+				M_ICMP_IMM(i - 1, REG_ITMP1);
+				M_BA(0);
 
 				codegen_addreference(cd, (basicblock *) tptr[0]);
 
@@ -3090,7 +3004,7 @@ nowperformreturn:
 				M_MOV_IMM(0, REG_ITMP2);
 				dseg_adddata(cd);
 				emit_mov_memindex_reg(cd, -(cd->dseglen), REG_ITMP2, REG_ITMP1, 3, REG_ITMP1);
-				emit_jmp_reg(cd, REG_ITMP1);
+				M_JMP(REG_ITMP1);
 			}
 			break;
 
@@ -3107,18 +3021,19 @@ nowperformreturn:
 				i = s4ptr[1];                          /* count    */
 			
 				MCODECHECK(8 + ((7 + 6) * i) + 5);
-				s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);    /* reg compare should always be faster */
+				s1 = emit_load_s1(jd, iptr, src, REG_ITMP1);
+
 				while (--i >= 0) {
 					s4ptr += 2;
 					++tptr;
 
 					val = s4ptr[0];
-					emit_alul_imm_reg(cd, ALU_CMP, val, s1);
-					emit_jcc(cd, CC_E, 0);
+					M_ICMP_IMM(val, s1);
+					M_BEQ(0);
 					codegen_addreference(cd, (basicblock *) tptr[0]);
 				}
 
-				emit_jmp_imm(cd, 0);
+				M_JMP_IMM(0);
 			
 				tptr = (void **) iptr->target;
 				codegen_addreference(cd, (basicblock *) tptr[0]);
@@ -3176,7 +3091,11 @@ gen_method:
 						M_FLTMOVE(d, s1);
 					} else {
 						d = emit_load_s1(jd, iptr, src, REG_FTMP1);
-						M_DST(d, REG_SP, md->params[s3].regoff * 8);
+
+						if (IS_2_WORD_TYPE(src->type))
+							M_DST(d, REG_SP, md->params[s3].regoff * 8);
+						else
+							M_FST(d, REG_SP, md->params[s3].regoff * 8);
 					}
 				}
 			}
@@ -3507,7 +3426,7 @@ gen_method:
 #if defined(ENABLE_THREADS)
 					codegen_threadcritstop(cd, cd->mcodeptr - cd->mcodebase);
 #endif
-					M_CMP(REG_ITMP3, REG_ITMP2);
+					M_LCMP(REG_ITMP3, REG_ITMP2);
 					M_BA(0);         /* (u) REG_ITMP1 > (u) REG_ITMP2 -> jump */
 					codegen_add_classcastexception_ref(cd);
 				}
@@ -4122,13 +4041,18 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd)
 	if (opt_verbosecall) {
 		/* save integer and float argument registers */
 
-		for (i = 0, j = 0; i < md->paramcount && j < INT_ARG_CNT; i++)
-			if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
-				M_LST(rd->argintregs[j++], REG_SP, (1 + i) * 8);
+		for (i = 0, j = 1; i < md->paramcount; i++) {
+			if (!md->params[i].inmemory) {
+				s1 = md->params[i].regoff;
+
+				if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
+					M_LST(rd->argintregs[s1], REG_SP, j * 8);
+				else
+					M_DST(rd->argfltregs[s1], REG_SP, j * 8);
 
-		for (i = 0, j = 0; i < md->paramcount && j < FLT_ARG_CNT; i++)
-			if (IS_FLT_DBL_TYPE(md->paramtypes[i].type))
-				M_DST(rd->argfltregs[j++], REG_SP, (1 + INT_ARG_CNT + i) * 8);
+				j++;
+			}
+		}
 
 		/* show integer hex code for float arguments */
 
@@ -4152,13 +4076,18 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd)
 
 		/* restore integer and float argument registers */
 
-		for (i = 0, j = 0; i < md->paramcount && j < INT_ARG_CNT; i++)
-			if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
-				M_LLD(rd->argintregs[j++], REG_SP, (1 + i) * 8);
+		for (i = 0, j = 1; i < md->paramcount; i++) {
+			if (!md->params[i].inmemory) {
+				s1 = md->params[i].regoff;
+
+				if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
+					M_LLD(rd->argintregs[s1], REG_SP, j * 8);
+				else
+					M_DLD(rd->argfltregs[s1], REG_SP, j * 8);
 
-		for (i = 0, j = 0; i < md->paramcount && j < FLT_ARG_CNT; i++)
-			if (IS_FLT_DBL_TYPE(md->paramtypes[i].type))
-				M_DLD(rd->argfltregs[j++], REG_SP, (1 + INT_ARG_CNT + i) * 8);
+				j++;
+			}
+		}
 	}
 #endif /* !defined(NDEBUG) */
 
@@ -4179,13 +4108,18 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd)
 
 	/* save integer and float argument registers */
 
-	for (i = 0, j = 0; i < md->paramcount && j < INT_ARG_CNT; i++)
-		if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
-			M_LST(rd->argintregs[j++], REG_SP, i * 8);
+	for (i = 0, j = 0; i < md->paramcount; i++) {
+		if (!md->params[i].inmemory) {
+			s1 = md->params[i].regoff;
+
+			if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
+				M_LST(rd->argintregs[s1], REG_SP, j * 8);
+			else
+				M_DST(rd->argfltregs[s1], REG_SP, j * 8);
 
-	for (i = 0, j = 0; i < md->paramcount && j < FLT_ARG_CNT; i++)
-		if (IS_FLT_DBL_TYPE(md->paramtypes[i].type))
-			M_DST(rd->argfltregs[j++], REG_SP, (INT_ARG_CNT + i) * 8);
+			j++;
+		}
+	}
 
 	M_AST(REG_ITMP3, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT) * 8);
 
@@ -4200,13 +4134,18 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd)
 
 	/* restore integer and float argument registers */
 
-	for (i = 0, j = 0; i < md->paramcount && j < INT_ARG_CNT; i++)
-		if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
-			M_LLD(rd->argintregs[j++], REG_SP, i * 8);
+	for (i = 0, j = 0; i < md->paramcount; i++) {
+		if (!md->params[i].inmemory) {
+			s1 = md->params[i].regoff;
 
-	for (i = 0, j = 0; i < md->paramcount && j < FLT_ARG_CNT; i++)
-		if (IS_FLT_DBL_TYPE(md->paramtypes[i].type))
-			M_DLD(rd->argfltregs[j++], REG_SP, (INT_ARG_CNT + i) * 8);
+			if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
+				M_LLD(rd->argintregs[s1], REG_SP, j * 8);
+			else
+				M_DLD(rd->argfltregs[s1], REG_SP, j * 8);
+
+			j++;
+		}
+	}
 
 	M_ALD(REG_ITMP3, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT) * 8);
 
@@ -4243,8 +4182,14 @@ u1 *createnativestub(functionptr f, jitdata *jd, methoddesc *nmd)
 			if (md->params[i].inmemory) {
 				s1 = md->params[i].regoff + stackframesize + 1;   /* + 1 (RA) */
 				s2 = nmd->params[j].regoff;
-				M_DLD(REG_FTMP1, REG_SP, s1 * 8);
-				M_DST(REG_FTMP1, REG_SP, s2 * 8);
+
+				if (IS_2_WORD_TYPE(t)) {
+					M_DLD(REG_FTMP1, REG_SP, s1 * 8);
+					M_DST(REG_FTMP1, REG_SP, s2 * 8);
+				} else {
+					M_FLD(REG_FTMP1, REG_SP, s1 * 8);
+					M_FST(REG_FTMP1, REG_SP, s2 * 8);
+				}
 			}
 		}
 	}
diff --git a/src/vm/jit/x86_64/codegen.h b/src/vm/jit/x86_64/codegen.h
index 1be675c64..9657b1b67 100644
--- a/src/vm/jit/x86_64/codegen.h
+++ b/src/vm/jit/x86_64/codegen.h
@@ -29,7 +29,7 @@
 
    Changes:
 
-   $Id: codegen.h 4941 2006-05-23 08:25:14Z twisti $
+   $Id: codegen.h 4943 2006-05-23 08:51:33Z twisti $
 
 */
 
@@ -76,24 +76,13 @@
 
 #define gen_bound_check \
     if (checkbounds) { \
-        M_ICMP_MEMBASE(s1, OFFSET(java_arrayheader, size), s2); \
+        M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));\
+        M_ICMP(REG_ITMP3, s2); \
         M_BAE(0); \
         codegen_add_arrayindexoutofboundsexception_ref(cd, s2); \
     }
 
 
-#define gen_div_check(v) \
-    if (checknull) { \
-        if ((v)->flags & INMEMORY) { \
-            M_CMP_IMM_MEMBASE(0, REG_SP, src->regoff * 8); \
-        } else { \
-            M_TEST(src->regoff); \
-        } \
-        M_BEQ(0); \
-        codegen_add_arithmeticexception_ref(cd); \
-    }
-
-
 /* MCODECHECK(icnt) */
 
 #define MCODECHECK(icnt) \
@@ -187,19 +176,23 @@
 #define M_LST32_IMM32(a,b,disp) emit_mov_imm_membase32(cd, (a), (b), (disp))
 
 #define M_IADD(a,b)             emit_alul_reg_reg(cd, ALU_ADD, (a), (b))
-#define M_IADD_IMM(a,b)         emit_alul_reg_reg(cd, ALU_ADD, (a), (b))
+#define M_ISUB(a,b)             emit_alul_reg_reg(cd, ALU_SUB, (a), (b))
+#define M_IMUL(a,b)             emit_imull_reg_reg(cd, (a), (b))
+
+#define M_IADD_IMM(a,b)         emit_alul_imm_reg(cd, ALU_ADD, (a), (b))
+#define M_ISUB_IMM(a,b)         emit_alul_imm_reg(cd, ALU_SUB, (a), (b))
+#define M_IMUL_IMM(a,b,c)       emit_imull_imm_reg_reg(cd, (b), (a), (c))
 
 #define M_LADD(a,b)             emit_alu_reg_reg(cd, ALU_ADD, (a), (b))
-#define M_LADD_IMM(a,b)         emit_alu_imm_reg(cd, ALU_ADD, (a), (b))
 #define M_LSUB(a,b)             emit_alu_reg_reg(cd, ALU_SUB, (a), (b))
-#define M_LSUB_IMM(a,b)         emit_alu_imm_reg(cd, ALU_SUB, (a), (b))
+#define M_LMUL(a,b)             emit_imul_reg_reg(cd, (a), (b))
 
-#define M_IINC_MEMBASE(a,b)     emit_incl_membase(cd, (a), (b))
+#define M_LADD_IMM(a,b)         emit_alu_imm_reg(cd, ALU_ADD, (a), (b))
+#define M_LSUB_IMM(a,b)         emit_alu_imm_reg(cd, ALU_SUB, (a), (b))
+#define M_LMUL_IMM(a,b,c)       emit_imul_imm_reg_reg(cd, (b), (a), (c))
 
-#define M_IADD_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_ADD, (a), (b), (c))
-#define M_IADC_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_ADC, (a), (b), (c))
-#define M_ISUB_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_SUB, (a), (b), (c))
-#define M_ISBB_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_SBB, (a), (b), (c))
+#define M_IINC(a)               emit_incl_reg(cd, (a))
+#define M_IDEC(a)               emit_decl_reg(cd, (a))
 
 #define M_ALD(a,b,disp)         M_LLD(a,b,disp)
 #define M_ALD32(a,b,disp)       M_LLD32(a,b,disp)
@@ -222,35 +215,43 @@
 #define M_INEG(a)               emit_negl_reg(cd, (a))
 #define M_LNEG(a)               emit_neg_reg(cd, (a))
 
-#define M_INEG_MEMBASE(a,b)     emit_negl_membase(cd, (a), (b))
-#define M_LNEG_MEMBASE(a,b)     emit_neg_membase(cd, (a), (b))
-
-#define M_AND(a,b)              emit_alu_reg_reg(cd, ALU_AND, (a), (b))
-#define M_XOR(a,b)              emit_alu_reg_reg(cd, ALU_XOR, (a), (b))
-
 #define M_IAND(a,b)             emit_alul_reg_reg(cd, ALU_AND, (a), (b))
-#define M_IAND_IMM(a,b)         emit_alul_imm_reg(cd, ALU_AND, (a), (b))
+#define M_IOR(a,b)              emit_alul_reg_reg(cd, ALU_OR, (a), (b))
 #define M_IXOR(a,b)             emit_alul_reg_reg(cd, ALU_XOR, (a), (b))
 
+#define M_IAND_IMM(a,b)         emit_alul_imm_reg(cd, ALU_AND, (a), (b))
+#define M_IOR_IMM(a,b)          emit_alul_imm_reg(cd, ALU_OR, (a), (b))
+#define M_IXOR_IMM(a,b)         emit_alul_imm_reg(cd, ALU_XOR, (a), (b))
+
+#define M_LAND(a,b)             emit_alu_reg_reg(cd, ALU_AND, (a), (b))
+#define M_LOR(a,b)              emit_alu_reg_reg(cd, ALU_OR, (a), (b))
+#define M_LXOR(a,b)             emit_alu_reg_reg(cd, ALU_XOR, (a), (b))
+
+#define M_LAND_IMM(a,b)         emit_alu_imm_reg(cd, ALU_AND, (a), (b))
+#define M_LOR_IMM(a,b)          emit_alu_imm_reg(cd, ALU_OR, (a), (b))
+#define M_LXOR_IMM(a,b)         emit_alu_imm_reg(cd, ALU_XOR, (a), (b))
+
 #define M_BSEXT(a,b)            emit_movsbq_reg_reg(cd, (a), (b))
 #define M_SSEXT(a,b)            emit_movswq_reg_reg(cd, (a), (b))
 #define M_ISEXT(a,b)            emit_movslq_reg_reg(cd, (a), (b))
 
 #define M_CZEXT(a,b)            emit_movzwq_reg_reg(cd, (a), (b))
 
-#define M_BSEXT_MEMBASE(a,disp,b) emit_movsbq_membase_reg(cd, (a), (disp), (b))
-#define M_SSEXT_MEMBASE(a,disp,b) emit_movswq_membase_reg(cd, (a), (disp), (b))
-#define M_ISEXT_MEMBASE(a,disp,b) emit_movslq_membase_reg(cd, (a), (disp), (b))
+#define M_ISLL_IMM(a,b)         emit_shiftl_imm_reg(cd, SHIFT_SHL, (a), (b))
+#define M_ISRA_IMM(a,b)         emit_shiftl_imm_reg(cd, SHIFT_SAR, (a), (b))
+#define M_ISRL_IMM(a,b)         emit_shiftl_imm_reg(cd, SHIFT_SHR, (a), (b))
 
-#define M_CZEXT_MEMBASE(a,disp,b) emit_movzwq_membase_reg(cd, (a), (disp), (b))
+#define M_LSLL_IMM(a,b)         emit_shift_imm_reg(cd, SHIFT_SHL, (a), (b))
+#define M_LSRA_IMM(a,b)         emit_shift_imm_reg(cd, SHIFT_SAR, (a), (b))
+#define M_LSRL_IMM(a,b)         emit_shift_imm_reg(cd, SHIFT_SHR, (a), (b))
 
 #define M_TEST(a)               emit_test_reg_reg(cd, (a), (a))
 #define M_ITEST(a)              emit_testl_reg_reg(cd, (a), (a))
 
-#define M_CMP(a,b)              emit_alu_reg_reg(cd, ALU_CMP, (a), (b))
-#define M_CMP_IMM(a,b)          emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
-#define M_CMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
-#define M_CMP_MEMBASE(a,b,c)    emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
+#define M_LCMP(a,b)             emit_alu_reg_reg(cd, ALU_CMP, (a), (b))
+#define M_LCMP_IMM(a,b)         emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
+#define M_LCMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
+#define M_LCMP_MEMBASE(a,b,c)   emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
 
 #define M_ICMP(a,b)             emit_alul_reg_reg(cd, ALU_CMP, (a), (b))
 #define M_ICMP_IMM(a,b)         emit_alul_imm_reg(cd, ALU_CMP, (a), (b))
@@ -261,6 +262,8 @@
 #define M_BNE(disp)             emit_jcc(cd, CC_NE, (disp))
 #define M_BLT(disp)             emit_jcc(cd, CC_L, (disp))
 #define M_BLE(disp)             emit_jcc(cd, CC_LE, (disp))
+#define M_BGE(disp)             emit_jcc(cd, CC_GE, (disp))
+#define M_BGT(disp)             emit_jcc(cd, CC_G, (disp))
 #define M_BAE(disp)             emit_jcc(cd, CC_AE, (disp))
 #define M_BA(disp)              emit_jcc(cd, CC_A, (disp))
 
@@ -294,25 +297,55 @@
 
 #define M_NOP                   emit_nop(cd)
 
-#define M_CLR(a)                M_XOR(a,a)
+#define M_CLR(a)                M_LXOR(a,a)
+
+
+#define M_FLD(a,b,disp)         emit_movss_membase_reg(cd, (b), (disp), (a))
+#define M_DLD(a,b,disp)         emit_movsd_membase_reg(cd, (b), (disp), (a))
+
+#define M_FLD32(a,b,disp)       emit_movss_membase32_reg(cd, (b), (disp), (a))
+#define M_DLD32(a,b,disp)       emit_movsd_membase32_reg(cd, (b), (disp), (a))
+
+#define M_FST(a,b,disp)         emit_movss_reg_membase(cd, (a), (b), (disp))
+#define M_DST(a,b,disp)         emit_movsd_reg_membase(cd, (a), (b), (disp))
 
+#define M_FST32(a,b,disp)       emit_movss_reg_membase32(cd, (a), (b), (disp))
+#define M_DST32(a,b,disp)       emit_movsd_reg_membase32(cd, (a), (b), (disp))
 
-#if 0
-#define M_FLD(a,b,c)            emit_movlps_membase_reg(cd, (a), (b), (c))
-#define M_DLD(a,b,c)            emit_movlpd_membase_reg(cd, (a), (b), (c))
+#define M_FADD(a,b)             emit_addss_reg_reg(cd, (a), (b))
+#define M_DADD(a,b)             emit_addsd_reg_reg(cd, (a), (b))
+#define M_FSUB(a,b)             emit_subss_reg_reg(cd, (a), (b))
+#define M_DSUB(a,b)             emit_subsd_reg_reg(cd, (a), (b))
+#define M_FMUL(a,b)             emit_mulss_reg_reg(cd, (a), (b))
+#define M_DMUL(a,b)             emit_mulsd_reg_reg(cd, (a), (b))
+#define M_FDIV(a,b)             emit_divss_reg_reg(cd, (a), (b))
+#define M_DDIV(a,b)             emit_divsd_reg_reg(cd, (a), (b))
 
-#define M_FST(a,b,c)            emit_movlps_reg_membase(cd, (a), (b), (c))
-#define M_DST(a,b,c)            emit_movlpd_reg_membase(cd, (a), (b), (c))
-#endif
+#define M_CVTIF(a,b)            emit_cvtsi2ss_reg_reg(cd, (a), (b))
+#define M_CVTID(a,b)            emit_cvtsi2sd_reg_reg(cd, (a), (b))
+#define M_CVTLF(a,b)            emit_cvtsi2ssq_reg_reg(cd, (a), (b))
+#define M_CVTLD(a,b)            emit_cvtsi2sdq_reg_reg(cd, (a), (b))
+#define M_CVTFI(a,b)            emit_cvttss2si_reg_reg(cd, (a), (b))
+#define M_CVTDI(a,b)            emit_cvttsd2si_reg_reg(cd, (a), (b))
+#define M_CVTFL(a,b)            emit_cvttss2siq_reg_reg(cd, (a), (b))
+#define M_CVTDL(a,b)            emit_cvttsd2siq_reg_reg(cd, (a), (b))
 
-#define M_DLD(a,b,disp)         emit_movq_membase_reg(cd, (b), (disp), (a))
-#define M_DST(a,b,disp)         emit_movq_reg_membase(cd, (a), (b), (disp))
+#define M_CVTFD(a,b)            emit_cvtss2sd_reg_reg(cd, (a), (b))
+#define M_CVTDF(a,b)            emit_cvtsd2ss_reg_reg(cd, (a), (b))
 
 
 /* system instructions ********************************************************/
 
 #define M_RDTSC                 emit_rdtsc(cd)
 
+#define M_IINC_MEMBASE(a,b)     emit_incl_membase(cd, (a), (b))
+
+#define M_IADD_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_ADD, (a), (b), (c))
+#define M_IADC_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_ADC, (a), (b), (c))
+#define M_ISUB_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_SUB, (a), (b), (c))
+#define M_ISBB_MEMBASE(a,b,c)   emit_alul_reg_membase(cd, ALU_SBB, (a), (b), (c))
+
+
 #define PROFILE_CYCLE_START \
     do { \
         if (opt_prof) { \
diff --git a/src/vm/jit/x86_64/emit.c b/src/vm/jit/x86_64/emit.c
index 17b2cd5a4..b56c0e33c 100644
--- a/src/vm/jit/x86_64/emit.c
+++ b/src/vm/jit/x86_64/emit.c
@@ -28,7 +28,7 @@
 
    Changes:
 
-   $Id: emit.c 4941 2006-05-23 08:25:14Z twisti $
+   $Id: emit.c 4943 2006-05-23 08:51:33Z twisti $
 
 */
 
@@ -68,7 +68,10 @@ s4 emit_load_s1(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
 		disp = src->regoff * 8;
 
 		if (IS_FLT_DBL_TYPE(src->type)) {
-			M_DLD(tempreg, REG_SP, disp);
+			if (IS_2_WORD_TYPE(src->type))
+				M_DLD(tempreg, REG_SP, disp);
+			else
+				M_FLD(tempreg, REG_SP, disp);
 
 		} else {
 			if (IS_INT_TYPE(src->type))
@@ -107,7 +110,10 @@ s4 emit_load_s2(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
 		disp = src->regoff * 8;
 
 		if (IS_FLT_DBL_TYPE(src->type)) {
-			M_DLD(tempreg, REG_SP, disp);
+			if (IS_2_WORD_TYPE(src->type))
+				M_DLD(tempreg, REG_SP, disp);
+			else
+				M_FLD(tempreg, REG_SP, disp);
 
 		} else {
 			if (IS_INT_TYPE(src->type))
@@ -146,7 +152,10 @@ s4 emit_load_s3(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
 		disp = src->regoff * 8;
 
 		if (IS_FLT_DBL_TYPE(src->type)) {
-			M_DLD(tempreg, REG_SP, disp);
+			if (IS_2_WORD_TYPE(src->type))
+				M_DLD(tempreg, REG_SP, disp);
+			else
+				M_FLD(tempreg, REG_SP, disp);
 
 		} else {
 			if (IS_INT_TYPE(src->type))
@@ -211,9 +220,13 @@ void emit_store(jitdata *jd, instruction *iptr, stackptr dst, s4 d)
 
 		disp = dst->regoff * 8;
 
-		if (IS_FLT_DBL_TYPE(dst->type))
-			M_DST(d, REG_SP, disp);
-		else
+		if (IS_FLT_DBL_TYPE(dst->type)) {
+			if (IS_2_WORD_TYPE(dst->type))
+				M_DST(d, REG_SP, disp);
+			else
+				M_FST(d, REG_SP, disp);
+
+		} else
 			M_LST(d, REG_SP, disp);
 	}
 }
@@ -280,290 +293,44 @@ void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
 
 /* code generation functions **************************************************/
 
-void emit_ialu(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr)
+static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
 {
-	s4 s1 = src->prev->regoff;
-	s4 s2 = src->regoff;
-	s4 d = iptr->dst->regoff;
-
-	if (iptr->dst->flags & INMEMORY) {
-		if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			if (s2 == d) {
-				emit_movl_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-				emit_alul_reg_membase(cd, alu_op, REG_ITMP1, REG_SP, d * 8);
-
-			} else if (s1 == d) {
-				emit_movl_membase_reg(cd, REG_SP, s2 * 8, REG_ITMP1);
-				emit_alul_reg_membase(cd, alu_op, REG_ITMP1, REG_SP, d * 8);
-
-			} else {
-				emit_movl_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-				emit_alul_membase_reg(cd, alu_op, REG_SP, s2 * 8, REG_ITMP1);
-				emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
-
-		} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-			if (s2 == d) {
-				emit_alul_reg_membase(cd, alu_op, s1, REG_SP, d * 8);
-
-			} else {
-				emit_movl_membase_reg(cd, REG_SP, s2 * 8, REG_ITMP1);
-				emit_alul_reg_reg(cd, alu_op, s1, REG_ITMP1);
-				emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
+	if ((basereg == REG_SP) || (basereg == R12)) {
+		if (disp == 0) {
+			emit_address_byte(0, dreg, REG_SP);
+			emit_address_byte(0, REG_SP, REG_SP);
 
-		} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			if (s1 == d) {
-				emit_alul_reg_membase(cd, alu_op, s2, REG_SP, d * 8);
-						
-			} else {
-				emit_movl_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-				emit_alul_reg_reg(cd, alu_op, s2, REG_ITMP1);
-				emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
+		} else if (IS_IMM8(disp)) {
+			emit_address_byte(1, dreg, REG_SP);
+			emit_address_byte(0, REG_SP, REG_SP);
+			emit_imm8(disp);
 
 		} else {
-			emit_movl_reg_membase(cd, s1, REG_SP, d * 8);
-			emit_alul_reg_membase(cd, alu_op, s2, REG_SP, d * 8);
+			emit_address_byte(2, dreg, REG_SP);
+			emit_address_byte(0, REG_SP, REG_SP);
+			emit_imm32(disp);
 		}
 
-	} else {
-		if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			emit_movl_membase_reg(cd, REG_SP, s1 * 8, d);
-			emit_alul_membase_reg(cd, alu_op, REG_SP, s2 * 8, d);
-
-		} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-			M_INTMOVE(s1, d);
-			emit_alul_membase_reg(cd, alu_op, REG_SP, s2 * 8, d);
-
-		} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			M_INTMOVE(s2, d);
-			emit_alul_membase_reg(cd, alu_op, REG_SP, s1 * 8, d);
-
-		} else {
-			if (s2 == d) {
-				emit_alul_reg_reg(cd, alu_op, s1, d);
-
-			} else {
-				M_INTMOVE(s1, d);
-				emit_alul_reg_reg(cd, alu_op, s2, d);
-			}
-		}
-	}
-}
-
+	} else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
+		emit_address_byte(0,(dreg),(basereg));
 
-void emit_lalu(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr)
-{
-	s4 s1 = src->prev->regoff;
-	s4 s2 = src->regoff;
-	s4 d = iptr->dst->regoff;
-
-	if (iptr->dst->flags & INMEMORY) {
-		if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			if (s2 == d) {
-				emit_mov_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-				emit_alu_reg_membase(cd, alu_op, REG_ITMP1, REG_SP, d * 8);
-
-			} else if (s1 == d) {
-				emit_mov_membase_reg(cd, REG_SP, s2 * 8, REG_ITMP1);
-				emit_alu_reg_membase(cd, alu_op, REG_ITMP1, REG_SP, d * 8);
-
-			} else {
-				emit_mov_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-				emit_alu_membase_reg(cd, alu_op, REG_SP, s2 * 8, REG_ITMP1);
-				emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
-
-		} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-			if (s2 == d) {
-				emit_alu_reg_membase(cd, alu_op, s1, REG_SP, d * 8);
-
-			} else {
-				emit_mov_membase_reg(cd, REG_SP, s2 * 8, REG_ITMP1);
-				emit_alu_reg_reg(cd, alu_op, s1, REG_ITMP1);
-				emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
-
-		} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			if (s1 == d) {
-				emit_alu_reg_membase(cd, alu_op, s2, REG_SP, d * 8);
-						
-			} else {
-				emit_mov_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-				emit_alu_reg_reg(cd, alu_op, s2, REG_ITMP1);
-				emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
-
-		} else {
-			emit_mov_reg_membase(cd, s1, REG_SP, d * 8);
-			emit_alu_reg_membase(cd, alu_op, s2, REG_SP, d * 8);
-		}
+	} else if ((basereg) == RIP) {
+		emit_address_byte(0, dreg, RBP);
+		emit_imm32(disp);
 
 	} else {
-		if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			emit_mov_membase_reg(cd, REG_SP, s1 * 8, d);
-			emit_alu_membase_reg(cd, alu_op, REG_SP, s2 * 8, d);
-
-		} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-			M_INTMOVE(s1, d);
-			emit_alu_membase_reg(cd, alu_op, REG_SP, s2 * 8, d);
-
-		} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-			M_INTMOVE(s2, d);
-			emit_alu_membase_reg(cd, alu_op, REG_SP, s1 * 8, d);
+		if (IS_IMM8(disp)) {
+			emit_address_byte(1, dreg, basereg);
+			emit_imm8(disp);
 
 		} else {
-			if (s2 == d) {
-				emit_alu_reg_reg(cd, alu_op, s1, d);
-
-			} else {
-				M_INTMOVE(s1, d);
-				emit_alu_reg_reg(cd, alu_op, s2, d);
-			}
+			emit_address_byte(2, dreg, basereg);
+			emit_imm32(disp);
 		}
 	}
 }
 
 
-void emit_ialuconst(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr)
-{
-	s4 s1 = src->regoff;
-	s4 d = iptr->dst->regoff;
-
-	if (iptr->dst->flags & INMEMORY) {
-		if (src->flags & INMEMORY) {
-			if (s1 == d) {
-				emit_alul_imm_membase(cd, alu_op, iptr->val.i, REG_SP, d * 8);
-
-			} else {
-				emit_movl_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-				emit_alul_imm_reg(cd, alu_op, iptr->val.i, REG_ITMP1);
-				emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
-
-		} else {
-			emit_movl_reg_membase(cd, s1, REG_SP, d * 8);
-			emit_alul_imm_membase(cd, alu_op, iptr->val.i, REG_SP, d * 8);
-		}
-
-	} else {
-		if (src->flags & INMEMORY) {
-			emit_movl_membase_reg(cd, REG_SP, s1 * 8, d);
-			emit_alul_imm_reg(cd, alu_op, iptr->val.i, d);
-
-		} else {
-#if 0
-			M_INTMOVE(s1, d);
-			emit_alul_imm_reg(cd, alu_op, iptr->val.i, d);
-#else
-			/* lea addition optimization */
-
-			if ((alu_op == ALU_ADD) && (s1 != d)) {
-				M_ILEA(s1, iptr->val.i, d);
-
-			} else {
-				M_INTMOVE(s1, d);
-				emit_alul_imm_reg(cd, alu_op, iptr->val.i, d);
-			}
-#endif
-		}
-	}
-}
-
-
-void emit_laluconst(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr)
-{
-	s4 s1 = src->regoff;
-	s4 d = iptr->dst->regoff;
-
-	if (iptr->dst->flags & INMEMORY) {
-		if (src->flags & INMEMORY) {
-			if (s1 == d) {
-				if (IS_IMM32(iptr->val.l)) {
-					emit_alu_imm_membase(cd, alu_op, iptr->val.l, REG_SP, d * 8);
-
-				} else {
-					emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-					emit_alu_reg_membase(cd, alu_op, REG_ITMP1, REG_SP, d * 8);
-				}
-
-			} else {
-				emit_mov_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-
-				if (IS_IMM32(iptr->val.l)) {
-					emit_alu_imm_reg(cd, alu_op, iptr->val.l, REG_ITMP1);
-
-				} else {
-					emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP2);
-					emit_alu_reg_reg(cd, alu_op, REG_ITMP2, REG_ITMP1);
-				}
-				emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-			}
-
-		} else {
-			emit_mov_reg_membase(cd, s1, REG_SP, d * 8);
-
-			if (IS_IMM32(iptr->val.l)) {
-				emit_alu_imm_membase(cd, alu_op, iptr->val.l, REG_SP, d * 8);
-
-			} else {
-				emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-				emit_alu_reg_membase(cd, alu_op, REG_ITMP1, REG_SP, d * 8);
-			}
-		}
-
-	} else {
-#if 0
-		if (src->flags & INMEMORY) {
-			emit_mov_membase_reg(cd, REG_SP, s1 * 8, d);
-
-		} else {
-			M_INTMOVE(s1, d);
-		}
-
-		if (IS_IMM32(iptr->val.l)) {
-			emit_alu_imm_reg(cd, alu_op, iptr->val.l, d);
-
-		} else {
-			emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-			emit_alu_reg_reg(cd, alu_op, REG_ITMP1, d);
-		}
-#else
-		if (src->flags & INMEMORY) {
-			emit_mov_membase_reg(cd, REG_SP, s1 * 8, d);
-
-			if (IS_IMM32(iptr->val.l)) {
-				emit_alu_imm_reg(cd, alu_op, iptr->val.l, d);
-
-			} else {
-				emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-				emit_alu_reg_reg(cd, alu_op, REG_ITMP1, d);
-			}
-
-		} else {
-			if (IS_IMM32(iptr->val.l)) {
-				/* lea addition optimization */
-
-				if ((alu_op == ALU_ADD) && (s1 != d)) {
-					M_LLEA(s1, iptr->val.l, d);
-
-				} else {
-					M_INTMOVE(s1, d);
-					emit_alu_imm_reg(cd, alu_op, iptr->val.l, d);
-				}
-
-			} else {
-				M_INTMOVE(s1, d);
-				emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-				emit_alu_reg_reg(cd, alu_op, REG_ITMP1, d);
-			}
-		}
-#endif
-	}
-}
-
-
 void emit_ishift(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr)
 {
 	s4 s1 = src->prev->regoff;
@@ -796,179 +563,6 @@ void emit_lshift(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr)
 }
 
 
-void emit_ishiftconst(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr)
-{
-	s4 s1 = src->regoff;
-	s4 d = iptr->dst->regoff;
-
-	if ((src->flags & INMEMORY) && (iptr->dst->flags & INMEMORY)) {
-		if (s1 == d) {
-			emit_shiftl_imm_membase(cd, shift_op, iptr->val.i, REG_SP, d * 8);
-
-		} else {
-			emit_movl_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-			emit_shiftl_imm_reg(cd, shift_op, iptr->val.i, REG_ITMP1);
-			emit_movl_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-		}
-
-	} else if ((src->flags & INMEMORY) && !(iptr->dst->flags & INMEMORY)) {
-		emit_movl_membase_reg(cd, REG_SP, s1 * 8, d);
-		emit_shiftl_imm_reg(cd, shift_op, iptr->val.i, d);
-				
-	} else if (!(src->flags & INMEMORY) && (iptr->dst->flags & INMEMORY)) {
-		emit_movl_reg_membase(cd, s1, REG_SP, d * 8);
-		emit_shiftl_imm_membase(cd, shift_op, iptr->val.i, REG_SP, d * 8);
-
-	} else {
-		M_INTMOVE(s1, d);
-		emit_shiftl_imm_reg(cd, shift_op, iptr->val.i, d);
-	}
-}
-
-
-void emit_lshiftconst(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr)
-{
-	s4 s1 = src->regoff;
-	s4 d = iptr->dst->regoff;
-
-	if ((src->flags & INMEMORY) && (iptr->dst->flags & INMEMORY)) {
-		if (s1 == d) {
-			emit_shift_imm_membase(cd, shift_op, iptr->val.i, REG_SP, d * 8);
-
-		} else {
-			emit_mov_membase_reg(cd, REG_SP, s1 * 8, REG_ITMP1);
-			emit_shift_imm_reg(cd, shift_op, iptr->val.i, REG_ITMP1);
-			emit_mov_reg_membase(cd, REG_ITMP1, REG_SP, d * 8);
-		}
-
-	} else if ((src->flags & INMEMORY) && !(iptr->dst->flags & INMEMORY)) {
-		emit_mov_membase_reg(cd, REG_SP, s1 * 8, d);
-		emit_shift_imm_reg(cd, shift_op, iptr->val.i, d);
-				
-	} else if (!(src->flags & INMEMORY) && (iptr->dst->flags & INMEMORY)) {
-		emit_mov_reg_membase(cd, s1, REG_SP, d * 8);
-		emit_shift_imm_membase(cd, shift_op, iptr->val.i, REG_SP, d * 8);
-
-	} else {
-		M_INTMOVE(s1, d);
-		emit_shift_imm_reg(cd, shift_op, iptr->val.i, d);
-	}
-}
-
-
-void emit_ifcc(codegendata *cd, s4 if_op, stackptr src, instruction *iptr)
-{
-	if (src->flags & INMEMORY)
-		M_ICMP_IMM_MEMBASE(iptr->val.i, REG_SP, src->regoff * 8);
-	else {
-		if (iptr->val.i == 0)
-			M_ITEST(src->regoff);
-		else
-			M_ICMP_IMM(iptr->val.i, src->regoff);
-	}
-
-	/* If the conditional branch is part of an if-converted block,
-	   don't generate the actual branch. */
-
-	if ((iptr->opc & ICMD_CONDITION_MASK) == 0) {
-		emit_jcc(cd, if_op, 0);
-		codegen_addreference(cd, (basicblock *) iptr->target);
-	}
-}
-
-
-void emit_if_lcc(codegendata *cd, s4 if_op, stackptr src, instruction *iptr)
-{
-	s4 s1 = src->regoff;
-
-	if (src->flags & INMEMORY) {
-		if (IS_IMM32(iptr->val.l)) {
-			emit_alu_imm_membase(cd, ALU_CMP, iptr->val.l, REG_SP, s1 * 8);
-
-		} else {
-			emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-			emit_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, s1 * 8);
-		}
-
-	} else {
-		if (iptr->val.l == 0) {
-			emit_test_reg_reg(cd, s1, s1);
-
-		} else {
-			if (IS_IMM32(iptr->val.l)) {
-				emit_alu_imm_reg(cd, ALU_CMP, iptr->val.l, s1);
-
-			} else {
-				emit_mov_imm_reg(cd, iptr->val.l, REG_ITMP1);
-				emit_alu_reg_reg(cd, ALU_CMP, REG_ITMP1, s1);
-			}
-		}
-	}
-	emit_jcc(cd, if_op, 0);
-	codegen_addreference(cd, (basicblock *) iptr->target);
-}
-
-
-/* emit_if_icmpcc **************************************************************
-
-   Generate ICMD_IF_ICMPxx instructions.
-
-*******************************************************************************/
-
-void emit_if_icmpcc(codegendata *cd, s4 if_op, stackptr src,
-						   instruction *iptr)
-{
-	s4 s1 = src->prev->regoff;
-	s4 s2 = src->regoff;
-
-	if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-		emit_movl_membase_reg(cd, REG_SP, s2 * 8, REG_ITMP1);
-		emit_alul_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, s1 * 8);
-
-	} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-		emit_alul_membase_reg(cd, ALU_CMP, REG_SP, s2 * 8, s1);
-
-	} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-		emit_alul_reg_membase(cd, ALU_CMP, s2, REG_SP, s1 * 8);
-
-	} else {
-		emit_alul_reg_reg(cd, ALU_CMP, s2, s1);
-	}
-
-	
-	/* If the conditional branch is part of an if-converted block,
-	   don't generate the actual branch. */
-
-	if ((iptr->opc & ICMD_CONDITION_MASK) == 0) {
-		emit_jcc(cd, if_op, 0);
-		codegen_addreference(cd, (basicblock *) iptr->target);
-	}
-}
-
-
-void emit_if_lcmpcc(codegendata *cd, s4 if_op, stackptr src, instruction *iptr)
-{
-	s4 s1 = src->prev->regoff;
-	s4 s2 = src->regoff;
-
-	if ((src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-		emit_mov_membase_reg(cd, REG_SP, s2 * 8, REG_ITMP1);
-		emit_alu_reg_membase(cd, ALU_CMP, REG_ITMP1, REG_SP, s1 * 8);
-
-	} else if ((src->flags & INMEMORY) && !(src->prev->flags & INMEMORY)) {
-		emit_alu_membase_reg(cd, ALU_CMP, REG_SP, s2 * 8, s1);
-
-	} else if (!(src->flags & INMEMORY) && (src->prev->flags & INMEMORY)) {
-		emit_alu_reg_membase(cd, ALU_CMP, s2, REG_SP, s1 * 8);
-
-	} else {
-		emit_alu_reg_reg(cd, ALU_CMP, s2, s1);
-	}
-	emit_jcc(cd, if_op, 0);
-	codegen_addreference(cd, (basicblock *) iptr->target);
-}
-
-
 /* low-level code emitter functions *******************************************/
 
 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
@@ -1005,7 +599,7 @@ void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
 	emit_rex(1,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x8b;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -1024,7 +618,7 @@ void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
 {
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x8b;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -1041,7 +635,7 @@ void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
 	emit_rex(1,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x89;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -1055,7 +649,7 @@ void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x89;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -1114,7 +708,7 @@ void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 ind
 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
 	emit_rex(1,0,0,(basereg));
 	*(cd->mcodeptr++) = 0xc7;
-	emit_membase((basereg),(disp),0);
+	emit_membase(cd, (basereg),(disp),0);
 	emit_imm32((imm));
 }
 
@@ -1130,7 +724,7 @@ void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
 	emit_rex(0,0,0,(basereg));
 	*(cd->mcodeptr++) = 0xc7;
-	emit_membase((basereg),(disp),0);
+	emit_membase(cd, (basereg),(disp),0);
 	emit_imm32((imm));
 }
 
@@ -1145,7 +739,8 @@ void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
 }
 
 
-void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
+void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
+{
 	emit_rex(1,(dreg),0,(reg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0xbe;
@@ -1154,15 +749,8 @@ void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
 }
 
 
-void emit_movsbq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
-	emit_rex(1,(dreg),0,(basereg));
-	*(cd->mcodeptr++) = 0x0f;
-	*(cd->mcodeptr++) = 0xbe;
-	emit_membase((basereg),(disp),(dreg));
-}
-
-
-void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
+void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
+{
 	emit_rex(1,(dreg),0,(reg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0xbf;
@@ -1171,15 +759,8 @@ void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
 }
 
 
-void emit_movswq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
-	emit_rex(1,(dreg),0,(basereg));
-	*(cd->mcodeptr++) = 0x0f;
-	*(cd->mcodeptr++) = 0xbf;
-	emit_membase((basereg),(disp),(dreg));
-}
-
-
-void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
+void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
+{
 	emit_rex(1,(dreg),0,(reg));
 	*(cd->mcodeptr++) = 0x63;
 	/* XXX: why do reg and dreg have to be exchanged */
@@ -1187,14 +768,8 @@ void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
 }
 
 
-void emit_movslq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
-	emit_rex(1,(dreg),0,(basereg));
-	*(cd->mcodeptr++) = 0x63;
-	emit_membase((basereg),(disp),(dreg));
-}
-
-
-void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
+void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
+{
 	emit_rex(1,(dreg),0,(reg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0xb7;
@@ -1203,14 +778,6 @@ void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
 }
 
 
-void emit_movzwq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
-	emit_rex(1,(dreg),0,(basereg));
-	*(cd->mcodeptr++) = 0x0f;
-	*(cd->mcodeptr++) = 0xb7;
-	emit_membase((basereg),(disp),(dreg));
-}
-
-
 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
 	emit_rex(1,(reg),(indexreg),(basereg));
 	*(cd->mcodeptr++) = 0x0f;
@@ -1291,31 +858,35 @@ void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
 }
 
 
-void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp) {
+void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
+{
 	emit_rex(1,(reg),0,(basereg));
 	*(cd->mcodeptr++) = (((opc)) << 3) + 1;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
-void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp) {
+void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
+{
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = (((opc)) << 3) + 1;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
-void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg) {
+void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
+{
 	emit_rex(1,(reg),0,(basereg));
 	*(cd->mcodeptr++) = (((opc)) << 3) + 3;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
-void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg) {
+void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
+{
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = (((opc)) << 3) + 3;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -1361,12 +932,12 @@ void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp)
 	if (IS_IMM8(imm)) {
 		emit_rex(1,(basereg),0,0);
 		*(cd->mcodeptr++) = 0x83;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 		emit_imm8((imm));
 	} else {
 		emit_rex(1,(basereg),0,0);
 		*(cd->mcodeptr++) = 0x81;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 		emit_imm32((imm));
 	}
 }
@@ -1376,12 +947,12 @@ void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp)
 	if (IS_IMM8(imm)) {
 		emit_rex(0,(basereg),0,0);
 		*(cd->mcodeptr++) = 0x83;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 		emit_imm8((imm));
 	} else {
 		emit_rex(0,(basereg),0,0);
 		*(cd->mcodeptr++) = 0x81;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 		emit_imm32((imm));
 	}
 }
@@ -1426,80 +997,26 @@ void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
 	emit_rex(1,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x8d;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x8d;
-	emit_membase((basereg),(disp),(reg));
-}
-
-
-
-/*
- * inc, dec operations
- */
-void emit_inc_reg(codegendata *cd, s8 reg) {
-	emit_rex(1,0,0,(reg));
-	*(cd->mcodeptr++) = 0xff;
-	emit_reg(0,(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
-void emit_incl_reg(codegendata *cd, s8 reg) {
-	emit_rex(0,0,0,(reg));
-	*(cd->mcodeptr++) = 0xff;
-	emit_reg(0,(reg));
-}
-
-
-void emit_inc_membase(codegendata *cd, s8 basereg, s8 disp)
-{
-	emit_rex(1,0,0,(basereg));
-	*(cd->mcodeptr++) = 0xff;
-	emit_membase((basereg),(disp),0);
-}
-
 
 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
 {
 	emit_rex(0,0,0,(basereg));
 	*(cd->mcodeptr++) = 0xff;
-	emit_membase((basereg),(disp),0);
+	emit_membase(cd, (basereg),(disp),0);
 }
 
 
-void emit_dec_reg(codegendata *cd, s8 reg) {
-	emit_rex(1,0,0,(reg));
-	*(cd->mcodeptr++) = 0xff;
-	emit_reg(1,(reg));
-}
-
-        
-void emit_decl_reg(codegendata *cd, s8 reg) {
-	emit_rex(0,0,0,(reg));
-	*(cd->mcodeptr++) = 0xff;
-	emit_reg(1,(reg));
-}
-
-        
-void emit_dec_membase(codegendata *cd, s8 basereg, s8 disp) {
-	emit_rex(1,(basereg),0,0);
-	*(cd->mcodeptr++) = 0xff;
-	emit_membase((basereg),(disp),1);
-}
-
-
-void emit_decl_membase(codegendata *cd, s8 basereg, s8 disp) {
-	emit_rex(0,(basereg),0,0);
-	*(cd->mcodeptr++) = 0xff;
-	emit_membase((basereg),(disp),1);
-}
-
-
-
 
 void emit_cltd(codegendata *cd) {
     *(cd->mcodeptr++) = 0x99;
@@ -1533,7 +1050,7 @@ void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(1,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0xaf;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -1541,7 +1058,7 @@ void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0xaf;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -1594,12 +1111,12 @@ void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8
 	if (IS_IMM8((imm))) {
 		emit_rex(1,(dreg),0,(basereg));
 		*(cd->mcodeptr++) = 0x6b;
-		emit_membase((basereg),(disp),(dreg));
+		emit_membase(cd, (basereg),(disp),(dreg));
 		emit_imm8((imm));
 	} else {
 		emit_rex(1,(dreg),0,(basereg));
 		*(cd->mcodeptr++) = 0x69;
-		emit_membase((basereg),(disp),(dreg));
+		emit_membase(cd, (basereg),(disp),(dreg));
 		emit_imm32((imm));
 	}
 }
@@ -1609,12 +1126,12 @@ void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8
 	if (IS_IMM8((imm))) {
 		emit_rex(0,(dreg),0,(basereg));
 		*(cd->mcodeptr++) = 0x6b;
-		emit_membase((basereg),(disp),(dreg));
+		emit_membase(cd, (basereg),(disp),(dreg));
 		emit_imm8((imm));
 	} else {
 		emit_rex(0,(dreg),0,(basereg));
 		*(cd->mcodeptr++) = 0x69;
-		emit_membase((basereg),(disp),(dreg));
+		emit_membase(cd, (basereg),(disp),(dreg));
 		emit_imm32((imm));
 	}
 }
@@ -1661,14 +1178,14 @@ void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
 	emit_rex(1,0,0,(basereg));
 	*(cd->mcodeptr++) = 0xd3;
-	emit_membase((basereg),(disp),(opc));
+	emit_membase(cd, (basereg),(disp),(opc));
 }
 
 
 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
 	emit_rex(0,0,0,(basereg));
 	*(cd->mcodeptr++) = 0xd3;
-	emit_membase((basereg),(disp),(opc));
+	emit_membase(cd, (basereg),(disp),(opc));
 }
 
 
@@ -1704,11 +1221,11 @@ void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp
 	if ((imm) == 1) {
 		emit_rex(1,0,0,(basereg));
 		*(cd->mcodeptr++) = 0xd1;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 	} else {
 		emit_rex(1,0,0,(basereg));
 		*(cd->mcodeptr++) = 0xc1;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 		emit_imm8((imm));
 	}
 }
@@ -1718,11 +1235,11 @@ void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 dis
 	if ((imm) == 1) {
 		emit_rex(0,0,0,(basereg));
 		*(cd->mcodeptr++) = 0xd1;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 	} else {
 		emit_rex(0,0,0,(basereg));
 		*(cd->mcodeptr++) = 0xc1;
-		emit_membase((basereg),(disp),(opc));
+		emit_membase(cd, (basereg),(disp),(opc));
 		emit_imm8((imm));
 	}
 }
@@ -1771,7 +1288,7 @@ void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
 	*(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = (0x90 + (opc));
-	emit_membase((basereg),(disp),0);
+	emit_membase(cd, (basereg),(disp),0);
 }
 
 
@@ -1794,34 +1311,22 @@ void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
 
 
 
-void emit_neg_reg(codegendata *cd, s8 reg) {
+void emit_neg_reg(codegendata *cd, s8 reg)
+{
 	emit_rex(1,0,0,(reg));
 	*(cd->mcodeptr++) = 0xf7;
 	emit_reg(3,(reg));
 }
 
 
-void emit_negl_reg(codegendata *cd, s8 reg) {
+void emit_negl_reg(codegendata *cd, s8 reg)
+{
 	emit_rex(0,0,0,(reg));
 	*(cd->mcodeptr++) = 0xf7;
 	emit_reg(3,(reg));
 }
 
 
-void emit_neg_membase(codegendata *cd, s8 basereg, s8 disp) {
-	emit_rex(1,0,0,(basereg));
-	*(cd->mcodeptr++) = 0xf7;
-	emit_membase((basereg),(disp),3);
-}
-
-
-void emit_negl_membase(codegendata *cd, s8 basereg, s8 disp) {
-	emit_rex(0,0,0,(basereg));
-	*(cd->mcodeptr++) = 0xf7;
-	emit_membase((basereg),(disp),3);
-}
-
-
 void emit_push_reg(codegendata *cd, s8 reg) {
 	emit_rex(0,0,0,(reg));
 	*(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
@@ -2029,7 +1534,7 @@ void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x7e;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -2047,7 +1552,7 @@ void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(1,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x6e;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -2056,7 +1561,7 @@ void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x6e;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -2083,7 +1588,7 @@ void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0xd6;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -2092,7 +1597,7 @@ void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x7e;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -2119,7 +1624,7 @@ void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x11;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -2139,7 +1644,7 @@ void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
 	emit_rex(0,(reg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x11;
-	emit_membase((basereg),(disp),(reg));
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -2159,7 +1664,7 @@ void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x10;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -2174,11 +1679,21 @@ void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 }
 
 
-void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
+void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
+{
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x12;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
+}
+
+
+void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
+{
+	emit_rex(0,(reg),0,(basereg));
+	*(cd->mcodeptr++) = 0x0f;
+	*(cd->mcodeptr++) = 0x13;
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -2187,7 +1702,7 @@ void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x10;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -2202,12 +1717,23 @@ void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 }
 
 
-void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
+void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
+{
 	*(cd->mcodeptr++) = 0x66;
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x12;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
+}
+
+
+void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
+{
+	*(cd->mcodeptr++) = 0x66;
+	emit_rex(0,(reg),0,(basereg));
+	*(cd->mcodeptr++) = 0x0f;
+	*(cd->mcodeptr++) = 0x13;
+	emit_membase(cd, (basereg),(disp),(reg));
 }
 
 
@@ -2312,7 +1838,7 @@ void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x57;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
@@ -2330,7 +1856,7 @@ void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
 	emit_rex(0,(dreg),0,(basereg));
 	*(cd->mcodeptr++) = 0x0f;
 	*(cd->mcodeptr++) = 0x57;
-	emit_membase((basereg),(disp),(dreg));
+	emit_membase(cd, (basereg),(disp),(dreg));
 }
 
 
diff --git a/src/vm/jit/x86_64/md-emit.h b/src/vm/jit/x86_64/md-emit.h
index 202ddb786..63ee41dde 100644
--- a/src/vm/jit/x86_64/md-emit.h
+++ b/src/vm/jit/x86_64/md-emit.h
@@ -28,7 +28,7 @@
 
    Changes:
 
-   $Id: md-emit.h 4853 2006-04-27 12:33:20Z twisti $
+   $Id: md-emit.h 4943 2006-05-23 08:51:33Z twisti $
 
 */
 
@@ -143,44 +143,6 @@ typedef union {
     } while (0)
 
 
-#define emit_membase(basereg,disp,dreg) \
-    do { \
-        if ((basereg) == REG_SP || (basereg) == R12) { \
-            if ((disp) == 0) { \
-                emit_address_byte(0,(dreg),REG_SP); \
-                emit_address_byte(0,REG_SP,REG_SP); \
-            } else if (IS_IMM8((disp))) { \
-                emit_address_byte(1,(dreg),REG_SP); \
-                emit_address_byte(0,REG_SP,REG_SP); \
-                emit_imm8((disp)); \
-            } else { \
-                emit_address_byte(2,(dreg),REG_SP); \
-                emit_address_byte(0,REG_SP,REG_SP); \
-                emit_imm32((disp)); \
-            } \
-            break; \
-        } \
-        if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
-            emit_address_byte(0,(dreg),(basereg)); \
-            break; \
-        } \
-        \
-        if ((basereg) == RIP) { \
-            emit_address_byte(0,(dreg),RBP); \
-            emit_imm32((disp)); \
-            break; \
-        } \
-        \
-        if (IS_IMM8((disp))) { \
-            emit_address_byte(1,(dreg),(basereg)); \
-            emit_imm8((disp)); \
-        } else { \
-            emit_address_byte(2,(dreg),(basereg)); \
-            emit_imm32((disp)); \
-        } \
-    } while (0)
-
-
 #define emit_membase32(basereg,disp,dreg) \
     do { \
         if ((basereg) == REG_SP || (basereg) == R12) { \
@@ -264,18 +226,8 @@ void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d);
 
 /* code generation prototypes */
 
-void emit_ialu(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr);
-void emit_lalu(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr);
-void emit_ialuconst(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr);
-void emit_laluconst(codegendata *cd, s4 alu_op, stackptr src, instruction *iptr);
 void emit_ishift(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr);
 void emit_lshift(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr);
-void emit_ishiftconst(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr);
-void emit_lshiftconst(codegendata *cd, s4 shift_op, stackptr src, instruction *iptr);
-void emit_ifcc(codegendata *cd, s4 if_op, stackptr src, instruction *iptr);
-void emit_if_lcc(codegendata *cd, s4 if_op, stackptr src, instruction *iptr);
-void emit_if_icmpcc(codegendata *cd, s4 if_op, stackptr src, instruction *iptr);
-void emit_if_lcmpcc(codegendata *cd, s4 if_op, stackptr src, instruction *iptr);
 
 
 /* integer instructions */
@@ -334,14 +286,9 @@ void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg);
 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg);
 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg);
 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg);
-void emit_inc_reg(codegendata *cd, s8 reg);
-void emit_incl_reg(codegendata *cd, s8 reg);
-void emit_inc_membase(codegendata *cd, s8 basereg, s8 disp);
+
 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp);
-void emit_dec_reg(codegendata *cd, s8 reg);
-void emit_decl_reg(codegendata *cd, s8 reg);
-void emit_dec_membase(codegendata *cd, s8 basereg, s8 disp);
-void emit_decl_membase(codegendata *cd, s8 basereg, s8 disp);
+
 void emit_cltd(codegendata *cd);
 void emit_cqto(codegendata *cd);
 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg);
@@ -420,9 +367,11 @@ void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp);
 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg);
 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg);
 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg);
+void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp);
 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg);
 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg);
 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg);
+void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp);
 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale);
 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale);
 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg);