Use Intel Core code for eagleheights CAR init, not Intel Core 2, as

any of the CPUs might be used.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/intel/eagleheights/Config.lb b/src/mainboard/intel/eagleheights/Config.lb
index 8346682908d66f8856e9731a0060498d3e7a6062..ea76cad821496ad625fda75e560d7ca069c17acb 100644 (file)
--- a/src/mainboard/intel/eagleheights/Config.lb
+++ b/src/mainboard/intel/eagleheights/Config.lb
@@ -109,7 +109,8 @@ ldscript /arch/i386/lib/id.lds
 ##
 ## Setup Cache-As-Ram
 ##
-mainboardinit cpu/intel/model_6fx/cache_as_ram.inc
+## Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
+mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
 
 ###
 ### This is the early phase of coreboot startup

diff --git a/src/mainboard/intel/eagleheights/Makefile.inc b/src/mainboard/intel/eagleheights/Makefile.inc
index 4f4d38c6ec059ec3e6c0f1d0f317914854e6fa8f..38ee2af977709e476eca05eec8303c45f0a404ee 100644 (file)
--- a/src/mainboard/intel/eagleheights/Makefile.inc
+++ b/src/mainboard/intel/eagleheights/Makefile.inc
@@ -14,6 +14,7 @@ crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
 crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
 crt0-y += ../../../../src/arch/i386/lib/id.inc
+# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
 crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
 crt0-y += auto.inc
 

diff --git a/src/mainboard/intel/eagleheights/auto.c b/src/mainboard/intel/eagleheights/auto.c
index f28e1e7bbbc71529128f16ba619556052f4cf238..2dce5bb6c343a8d499a49efca6e321aff867d5ce 100644 (file)
--- a/src/mainboard/intel/eagleheights/auto.c
+++ b/src/mainboard/intel/eagleheights/auto.c
@@ -238,4 +238,5 @@ void real_main(unsigned long bist)
        sdram_initialize(ARRAY_SIZE(mch), mch);
 }
 
-#include "cpu/intel/model_6fx/cache_as_ram_disable.c"
+/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
+#include "cpu/intel/model_6ex/cache_as_ram_disable.c"