int ide0_enable:1;
int ide1_enable:1;
+
/* 1 = 80-pin cable */
int ide0_80pin_cable:1;
int ide1_80pin_cable:1;
for (i = 0; i < 256; i += 16) {
printk_debug("%02x: ", i);
for (j = 0; j < 16; j++) {
- printk_debug("%02x ",
- pci_read_config8(dev, i + j));
+ printk_debug("%02x ", pci_read_config8(dev, i + j));
}
printk_debug("\n");
}
static void vt8237r_enable(struct device *dev)
{
struct southbridge_via_vt8237r_config *sb =
- (struct southbridge_via_vt8237r_config *) dev->chip_info;
+ (struct southbridge_via_vt8237r_config *)dev->chip_info;
pci_write_config8(dev, 0x50, sb->fn_ctrl_lo);
pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
#ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
#define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H
-/* Static resources for the VT8237R southbridge. */
+/* Static resources for the VT8237R southbridge */
-#define VT8237R_APIC_ID 0x2
-#define VT8237R_ACPI_IO_BASE 0x500
-#define VT8237R_SMBUS_IO_BASE 0x400
+#define VT8237R_APIC_ID 0x2
+#define VT8237R_ACPI_IO_BASE 0x500
+#define VT8237R_SMBUS_IO_BASE 0x400
/* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */
-#define VT8237R_ACPI_IRQ 0x9
-#define VT8237R_HPET_ADDR 0xfed00000ULL
-#define VT8237R_APIC_BASE 0xfec00000ULL
+#define VT8237R_ACPI_IRQ 0x9
+#define VT8237R_HPET_ADDR 0xfed00000ULL
+#define VT8237R_APIC_BASE 0xfec00000ULL
-/* IDE specific defines */
-#define IDE_CS 0x40
-#define IDE_CONF_I 0x41
-#define IDE_CONF_II 0x42
-#define IDE_CONF_FIFO 0x43
-#define IDE_MISC_I 0x44
-#define IDE_MISC_II 0x45
-#define IDE_UDMA 0x50
+/* IDE */
+#define IDE_CS 0x40
+#define IDE_CONF_I 0x41
+#define IDE_CONF_II 0x42
+#define IDE_CONF_FIFO 0x43
+#define IDE_MISC_I 0x44
+#define IDE_MISC_II 0x45
+#define IDE_UDMA 0x50
-/* SMBus specific */
+/* SMBus */
#define VT8237R_POWER_WELL 0x94
#define VT8237R_SMBUS_IO_BASE_REG 0xd0
#define VT8237R_SMBUS_HOST_CONF 0xd2
-#define SMBHSTSTAT (VT8237R_SMBUS_IO_BASE + 0x0)
-#define SMBSLVSTAT (VT8237R_SMBUS_IO_BASE + 0x1)
-#define SMBHSTCTL (VT8237R_SMBUS_IO_BASE + 0x2)
-#define SMBHSTCMD (VT8237R_SMBUS_IO_BASE + 0x3)
-#define SMBXMITADD (VT8237R_SMBUS_IO_BASE + 0x4)
-#define SMBHSTDAT0 (VT8237R_SMBUS_IO_BASE + 0x5)
+#define SMBHSTSTAT (VT8237R_SMBUS_IO_BASE + 0x0)
+#define SMBSLVSTAT (VT8237R_SMBUS_IO_BASE + 0x1)
+#define SMBHSTCTL (VT8237R_SMBUS_IO_BASE + 0x2)
+#define SMBHSTCMD (VT8237R_SMBUS_IO_BASE + 0x3)
+#define SMBXMITADD (VT8237R_SMBUS_IO_BASE + 0x4)
+#define SMBHSTDAT0 (VT8237R_SMBUS_IO_BASE + 0x5)
-#define HOST_RESET 0xff
+#define HOST_RESET 0xff
/* 1 in the 0 bit of SMBHSTADD states to READ. */
-#define READ_CMD 0x01
-#define SMBUS_TIMEOUT (100 * 1000 * 10)
-#define I2C_TRANS_CMD 0x40
-#define CLOCK_SLAVE_ADDRESS 0x69
+#define READ_CMD 0x01
+#define SMBUS_TIMEOUT (100 * 1000 * 10)
+#define I2C_TRANS_CMD 0x40
+#define CLOCK_SLAVE_ADDRESS 0x69
#if DEBUG_SMBUS == 1
#define PRINT_DEBUG(x) print_debug(x)
dump_south(dev);
}
-static struct device_operations bridge_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .enable = bridge_enable,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = 0,
+static const struct device_operations bridge_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .enable = bridge_enable,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = 0,
};
-static struct pci_driver northbridge_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
+static const struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
};
/**
* Print an error, should it occur. If no error, just exit.
*
- * @param host_status The data returned on the host status register after a
- * transaction is processed.
+ * @param host_status The data returned on the host status register after
+ * a transaction is processed.
* @param loops The number of times a transaction was attempted.
*/
static void smbus_print_error(u8 host_status, int loops)
{
/* Check if there actually was an error. */
if ((host_status == 0x00 || host_status == 0x40 ||
- host_status == 0x42) && (loops < SMBUS_TIMEOUT))
+ host_status == 0x42) && (loops < SMBUS_TIMEOUT))
return;
if (loops >= SMBUS_TIMEOUT)
if (host_status & (1 << 2))
print_err("Device error\r\n");
if (host_status & (1 << 1))
- print_debug("Interrupt/SMI# Completed Successfully\r\n");
+ print_debug("Interrupt/SMI# completed successfully\r\n");
if (host_status & (1 << 0))
print_err("Host busy\r\n");
}
/**
- * Wait for the smbus to become ready to process the next transaction
+ * Wait for the SMBus to become ready to process the next transaction.
*/
static void smbus_wait_until_ready(void)
{
/* Yes, this is a mess, but it's the easiest way to do it. */
while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
++loops;
+
smbus_print_error(inb(SMBHSTSTAT), loops);
}
/**
- * Reset and take ownership of the smbus
+ * Reset and take ownership of the SMBus.
*/
static void smbus_reset(void)
{
outb(HOST_RESET, SMBHSTSTAT);
+
/* Datasheet says we have to read it to take ownership of SMBus. */
inb(SMBHSTSTAT);
}
/**
- * Read a byte from the smbus
+ * Read a byte from the SMBus.
*
- * @param dimm The address location of the dimm on the smbus
- * @param offset The offset the data is located at
+ * @param dimm The address location of the DIMM on the SMBus.
+ * @param offset The offset the data is located at.
*/
u8 smbus_read_byte(u8 dimm, u8 offset)
{
PRINT_DEBUG("\r\n");
smbus_reset();
+
/* Clear host data port. */
outb(0x00, SMBHSTDAT0);
SMBUS_DELAY();
dimm |= 1;
outb(dimm, SMBXMITADD);
outb(offset, SMBHSTCMD);
+
/* Start transaction, byte data read. */
outb(0x48, SMBHSTCTL);
-
SMBUS_DELAY();
-
smbus_wait_until_ready();
val = inb(SMBHSTDAT0);
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Power Management Controller not found\r\n");
+ die("Power management controller not found\r\n");
/* 7 = SMBus Clock from RTC 32.768KHz
* 5 = Internal PLL reset from susp
*/
pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0);
- /* Enable SMBus */
+ /* Enable SMBus. */
pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG,
- VT8237R_SMBUS_IO_BASE | 0x1);
+ VT8237R_SMBUS_IO_BASE | 0x1);
- /* SMBus Host Configuration, enable */
+ /* SMBus Host Configuration, enable. */
pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01);
/* Make it work for I/O. */
}
/**
- * A fixup for some systems that need time for the smbus to "warm up". This is
- * needed on some vt823x based systems, where the smbus spurts out bad data for
- * a short time after power on. This has been seen on the Via Epia-series and
+ * A fixup for some systems that need time for the SMBus to "warm up". This is
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for
+ * a short time after power on. This has been seen on the VIA Epia series and
* Jetway J7F2-series. It reads the ID byte from SMBus, looking for
* known-good data from a slot/address. Exits on either good data or a timeout.
*
- * This should probably go into some global file, but one would need to be
- * created just for it. If some other chip needs/wants it, we can worry about it
- * then.
+ * TODO: This should probably go into some global file, but one would need to
+ * be created just for it. If some other chip needs/wants it, we can
+ * worry about it then.
*
- * @param ctrl The memory controller and smbus addresses
+ * @param ctrl The memory controller and SMBus addresses.
*/
void smbus_fixup(const struct mem_controller *ctrl)
{
ram_slots = ARRAY_SIZE(ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup thinks there are no ram slots!\r\n");
+ print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
return;
}
-
- PRINT_DEBUG("Waiting for smbus to warm up");
-
- /* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for the
- * ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
- * vt8237r has only been seen on DDR and DDR2 based systems, so far */
- for(i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
- (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++)
- {
- if (current_slot > ram_slots) current_slot = 0;
- result = smbus_read_byte(ctrl->channel0[current_slot],
- SPD_MEMORY_TYPE);
+
+ PRINT_DEBUG("Waiting for SMBus to warm up");
+
+ /*
+ * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
+ * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
+ * VT8237R has only been seen on DDR and DDR2 based systems, so far.
+ */
+ for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
+ (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
+
+ if (current_slot > ram_slots)
+ current_slot = 0;
+
+ result = smbus_read_byte(ctrl->channel0[current_slot],
+ SPD_MEMORY_TYPE);
current_slot++;
PRINT_DEBUG(".");
}
- if (i >= SMBUS_TIMEOUT) print_err("SMBus timed out while warming up\r\n");
- else PRINT_DEBUG("Done\r\n");
+
+ if (i >= SMBUS_TIMEOUT)
+ print_err("SMBus timed out while warming up\r\n");
+ else
+ PRINT_DEBUG("Done\r\n");
}
static void ide_init(struct device *dev)
{
struct southbridge_via_vt8237r_config *sb =
- (struct southbridge_via_vt8237r_config *) dev->chip_info;
+ (struct southbridge_via_vt8237r_config *)dev->chip_info;
u8 enables;
u32 cablesel;
/* Enable only compatibility mode. */
enables = pci_read_config8(dev, IDE_CONF_II);
enables &= ~0xc0;
- pci_write_config8(dev,IDE_CONF_II, enables);
+ pci_write_config8(dev, IDE_CONF_II, enables);
enables = pci_read_config8(dev, IDE_CONF_II);
printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
/* Cable guy... */
cablesel = pci_read_config32(dev, IDE_UDMA);
- cablesel &= ~((1 << 28) | (1 << 20) | (1 <<12) | (1 << 4));
+ cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
cablesel |= (sb->ide0_80pin_cable << 28) |
(sb->ide0_80pin_cable << 20) |
(sb->ide1_80pin_cable << 12) |
pci_write_config32(dev, IDE_UDMA, cablesel);
}
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .enable = 0,
- .ops_pci = 0,
+static const struct device_operations ide_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ide_init,
+ .enable = 0,
+ .ops_pci = 0,
};
-static struct pci_driver northbridge_driver __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_82C586_1,
+static const struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &ide_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_82C586_1,
};
/* All delivered to CPU0. */
ioapic_table[0].value_high = (lapicid()) << (56 - 32);
- l = (unsigned long *) ioapic_base;
+ l = (unsigned long *)ioapic_base;
/* Set APIC to FSB message bus. */
l[0] = 0x3;
init_keyboard(dev);
}
-static struct device_operations vt8237r_lpc_ops = {
- .read_resources = vt8237r_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = vt8237r_enable_resources,
- .init = &southbridge_init,
- .scan_bus = scan_static_bus,
+static const struct device_operations vt8237r_lpc_ops = {
+ .read_resources = vt8237r_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = vt8237r_enable_resources,
+ .init = &southbridge_init,
+ .scan_bus = scan_static_bus,
};
-static struct pci_driver lpc_driver __pci_driver = {
- .ops = &vt8237r_lpc_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VT8237R_LPC,
+static const struct pci_driver lpc_driver __pci_driver = {
+ .ops = &vt8237r_lpc_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VT8237R_LPC,
};
pci_write_config8(dev, SATA_MISC_CTRL, reg);
}
-static struct device_operations sata_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = sata_init,
- .enable = 0,
- .ops_pci = 0,
+static const struct device_operations sata_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sata_init,
+ .enable = 0,
+ .ops_pci = 0,
};
-static struct pci_driver northbridge_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_VT6420_SATA,
+static const struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VT6420_SATA,
};
projects / coreboot.git / commitdiff