adjust options

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/targets/embeddedplanet/ep405pc/Config.lb b/targets/embeddedplanet/ep405pc/Config.lb
index 837867139d104e14e7c35b6fa70bd4ecadf36560..5ee911b92bac7623ca96d21a9a21f6b5cc262083 100644 (file)
--- a/targets/embeddedplanet/ep405pc/Config.lb
+++ b/targets/embeddedplanet/ep405pc/Config.lb
@@ -5,19 +5,24 @@ loadoptions
 
 target ep405pc
 
-uses ARCH CROSS_COMPILE 
+uses ARCH 
+uses CPU_OPT
+uses CROSS_COMPILE 
 uses HAVE_OPTION_TABLE
-uses CONFIG_SANDPOINT_ALTIMUS 
 uses CONFIG_COMPRESS 
+uses CONFIG_CHIP_CONFIGURE
 uses NO_POST
 uses CONFIG_IDE_STREAM 
+uses CONFIG_SYS_CLK_FREQ
 uses IDE_BOOT_DRIVE
 uses USE_ELF_BOOT 
 uses IDE_SWAB IDE_OFFSET 
 uses ROM_SIZE ROM_IMAGE_SIZE 
 uses ROM_SECTION_SIZE 
 uses ROM_SECTION_OFFSET 
+uses _RESET
 uses _ROMBASE
+uses _RAMBASE
 uses CACHE_RAM_BASE 
 uses CACHE_RAM_SIZE 
 uses STACK_SIZE HEAP_SIZE
@@ -25,6 +30,9 @@ uses MAINBOARD
 uses MAINBOARD_PART_NUMBER 
 uses MAINBOARD_VENDOR
 
+## Enable PPC405 instructions
+option CPU_OPT="-Wa,-m405"
+
 ## use a cross compiler
 option CROSS_COMPILE="powerpc-eabi-"
 
@@ -71,14 +79,19 @@ option ROM_SECTION_SIZE=ROM_SIZE
 option ROM_SECTION_OFFSET=0
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
-## 
-option _ROMBASE=0xfff00000
+## System clock
+##
+option CONFIG_SYS_CLK_FREQ=33
 
 romimage "normal"
+       ## Reset vector address
+       option _RESET=0xfffffffc
+
+       ## linuxBIOS ROM start address
+       option _ROMBASE=0xfff00000
+
        ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
        option ROM_IMAGE_SIZE=49152
-       option CONFIG_SANDPOINT_ALTIMUS=1
 
        mainboard embeddedplanet/ep405pc
 end

diff --git a/targets/motorola/sandpoint/Config.lb b/targets/motorola/sandpoint/Config.lb
index 83841063688b046d6bb3ca7eb3017d1a4a514887..d7dff1b2ae1b92857a980cf70c83ee6e43b50a4f 100644 (file)
--- a/targets/motorola/sandpoint/Config.lb
+++ b/targets/motorola/sandpoint/Config.lb
@@ -21,6 +21,7 @@ uses IDE_SWAB IDE_OFFSET
 uses ROM_SIZE ROM_IMAGE_SIZE 
 uses ROM_SECTION_SIZE 
 uses ROM_SECTION_OFFSET 
+uses _RESET
 uses _ROMBASE
 uses _RAMBASE
 uses CACHE_RAM_BASE 
@@ -31,8 +32,8 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 
 ## use a cross compiler
-#option CROSS_COMPILE="powerpc-eabi-"
-option CROSS_COMPILE="ppc_74xx-"
+option CROSS_COMPILE="powerpc-eabi-"
+#option CROSS_COMPILE="ppc_74xx-"
 
 ## Use chip configuration
 option CONFIG_CHIP_CONFIGURE=1
@@ -56,9 +57,6 @@ option IDE_OFFSET=0
 
 option ROM_SIZE=1048576
 
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x00100000
-
 ## For the trick of using cache as ram
 ## put the fake ram location at this address
 option CACHE_RAM_BASE=0x00200000
@@ -80,13 +78,18 @@ option HEAP_SIZE=0x10000
 option ROM_SECTION_SIZE=ROM_SIZE
 option ROM_SECTION_OFFSET=0
 
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-## 
-option _ROMBASE=0xfff00000
-
 # Sandpoint Demo Board
 romimage "normal"
+       ## Sandpoint reset vector
+       option _RESET=0xfff00100
+
+       ## Start of linuxBIOS in the boot rom
+       ## = _RESET + exeception vector table size
+       option _ROMBASE=0xfff03100
+
+       ## LinuxBIOS C code runs at this location in RAM
+       option _RAMBASE=0x00100000
+
        ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
        option ROM_IMAGE_SIZE=49152
        option CONFIG_SANDPOINT_ALTIMUS=1