Replace clear_memory with memset.

Replace set_init_ram_access with the call to set_var_mtrr.
Remove unused #include statments.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c
deleted file mode 100644 (file)
index 624e0fe..0000000
--- a/src/cpu/amd/car/clear_init_ram.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* by yhlu 6.2005 */
-/* be warned, this file will be used core 0/node 0 only */
-
-static void __attribute__((noinline)) clear_init_ram(void)
-{
-       // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
-       // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
-       // so noline clear_init_ram
-
-#if CONFIG_HAVE_ACPI_RESUME == 1
-       /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
-       clear_memory( CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
-#else
-        clear_memory(0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
-#endif
-}
-
-/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
-static void set_init_ram_access(void)
-{
-       set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
-}
-

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 5c085cd6d8b9dc1aa6e68bf37cef506b4981f83d..10194b96598c84588eb501a34a326624661d1396 100644 (file)
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -3,8 +3,6 @@
  */
 #include "cpu/amd/car/disable_cache_as_ram.c"
 
-#include "cpu/amd/car/clear_init_ram.c"
-
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
         printk_debug("%s%08x\r\n", strval, val);
@@ -64,7 +62,8 @@ static void post_cache_as_ram(void)
         #error "You need to set CONFIG_RAMTOP greater than 1M"
 #endif
        
-       set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
+       /* So we can access RAM from [1M, CONFIG_RAMTOP) */
+       set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
        print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
@@ -94,7 +93,12 @@ static void post_cache_as_ram(void)
        disable_cache_as_ram_bsp();  
 
         print_debug("Clearing initial memory region: ");
-        clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
+#if CONFIG_HAVE_ACPI_RESUME == 1
+       /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
+       memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
+#else
+        memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
+#endif
         print_debug("Done\r\n");
 
 //     dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);

diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 822e362a742d40ef85710f5aca6104b87ff884a3..c43887f380b568214b0baccc3e7d4fa6c746f3b9 100644 (file)
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -421,7 +421,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
                 */
                //wait_till_sysinfo_in_ram();
 
-               set_init_ram_access();
+               set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 
                STOP_CAR_AND_CPU();
                printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);

diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index daf3eceaa4e0a92bb74e0f3b1b53ed0696f5c328..6ef1f42471391f8822f9d2021820c16c8a725632 100644 (file)
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -34,7 +34,6 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/mem.h>
 #include <cpu/amd/quadcore.h>
 #include <cpu/amd/model_10xxx_msr.h>
 

diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 483399c0c0e93f93b9d3a07d8a9814db95b386ee..510c803ca9d0f515543cfece78dfce128252b740 100644 (file)
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -317,7 +317,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
                                print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid);
                        }
                         lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
-                        set_init_ram_access();
+                       set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
        #if CONFIG_MEM_TRAIN_SEQ == 1
                        train_ram_on_node(id.nodeid, id.coreid, sysinfo,
                                          (unsigned) STOP_CAR_AND_CPU);

diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 2d72618448b2b1accf36599326f4b69a41e28d3f..b4a981bcb37bfe0ea3dd0c7249f81f95f01216b8 100644 (file)
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -24,7 +24,6 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/mem.h>
 
 #include <cpu/amd/dualcore.h>
 
@@ -238,7 +237,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
 
                 /* clear memory 2M (limitk - basek) */
                 addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
-                clear_memory(addr, size);
+                memset(addr, size, 0);
 }
 
 static void init_ecc_memory(unsigned node_id)

diff --git a/src/include/cpu/x86/mem.h b/src/include/cpu/x86/mem.h
deleted file mode 100644 (file)
index 530c653..0000000
--- a/src/include/cpu/x86/mem.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef CPU_X86_MEM_H
-#define CPU_X86_MEM_H
-
-/* Optimized generic x86 assembly for clearing memory */
-static inline void clear_memory(void *addr, unsigned long size)
-{
-        asm volatile(
-                "cld \n\t"
-                "rep; stosl\n\t"
-                : /* No outputs */
-                : "a" (0), "D" (addr), "c" (size>>2)
-                );
-
-}
-
-#endif /* CPU_X86_MEM_H */

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 82a404b50be4e5358245ab95fff44d559a45f376..0546a6ddf3b6ae6883ab231958da2351797aaa3a 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -130,7 +130,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"
 
-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index f19147f11810c4aa785f789d2fd4373bd69b3b03..60a1e14f1db18bcb17b47bbe33694595c7cecb8a 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -110,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"
 
-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 4ebc47f6a03003a0ed46946ee38bb3e65058fc15..9d870f0c8d14168248b4b0a7c3982504e27dbb13 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -108,7 +108,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"
 
-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 749527fce97f5163aa61e40be7a66cf8b03044a2..1a19a146489c571bbc8b6ace9bc3baa8876c9702 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -108,7 +108,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"
 
-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 45d0d9401ae6448488f217d86894473af7869bf6..337750b66e4676751bf272f6d687d55d1321db3d 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -110,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "northbridge/amd/amdht/ht_wrapper.c"
 
-#include "include/cpu/x86/mem.h"
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"

diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 22b672f0e9f159fdec86fc4575477766209f8a30..0e27a169919cc9e8fa8dcfe0aa059ae608c2f4c8 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -4,7 +4,6 @@
        2005.02 yhlu add E0 memory hole support
 */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <stdlib.h>

diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index aaf60a85a1bb8e0c6e2035f5448f0436df63641d..601c035dd8851794a05025eaaf8fd4360b85ffc3 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -20,7 +20,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/tsc.h>

diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 27ed477d9a309fbaaffa9fb89bb8af0eb35f0531..bb4ebbdfe37d1fa81a0ae55793598f5fdb91ec15 100644 (file)
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -18,7 +18,6 @@
  *
  */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <stdlib.h>

diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 313dc0f9304c0839100cb747335101574e0bf33f..4aaa26480dd744d90a57fe4e076bbaa6942e9501 100644 (file)
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -18,7 +18,6 @@
  *
  */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <stdlib.h>

diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 5aa4d9ded6286bac6e8138232b40cd99e10ed268..76475ce235eaa962b6815e8c6424dba6ce16c0b0 100644 (file)
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -19,7 +19,6 @@
  *
  */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <stdlib.h>

diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 5e51361898f853ca1553cb35596a9600a4aab918..9ad778bf13d0297e8d6cdf3e121ed97fb84e59f3 100644 (file)
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -19,7 +19,6 @@
  *
  */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include "raminit_ep80579.h"

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index f65ccfaf42765eb74691e43a9720741d02b26b07..3f73549eb68a0953428eab7c1bbcaf3580e066ba 100644 (file)
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -17,7 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/mem.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <spd.h>