action "cp $< $@"
end
+makerule clean
+ action "rm -f linuxbios.* *~"
+ action "rm -f linuxbios"
+ action "rm -f ldscript.ld"
+ action "rm -f a.out *.s *.l *.o *.E *.inc"
+ action "rm -f TAGS tags romcc*"
+ action "rm -f docipl buildrom* chips.c *chip.c linuxbios_ram* linuxbios_pay*"
+ action "rm -f build_opt_tbl* nrv2b* option_table.c"
+end
+
dir init
dir lib
dir boot
-/*kernel/include/sys/as_archppc970.h, epos_code, epos_1.0 8/25/04 15:33:07*/
-/*----------------------------------------------------------------------------+
-| COPYRIGHT I B M CORPORATION 2003
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-| US Government Users Restricted Rights - Use, duplication or
-| disclosure restricted by GSA ADP Schedule Contract with
-| IBM Corp.
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| EPOS
-| Author: Maciej P. Tyrlik
-| Component: Include file.
-| File: sys/as_archppc970.h
-| Purpose: Assembler include file for PPC970 processor.
-| Changes:
-| Date: Comment:
-| ----- --------
-| 13-Oct-03 Created MPT
-+----------------------------------------------------------------------------*/
-
-#ifndef _PPC970_H_
-#define _PPC970_H_
-
-/*----------------------------------------------------------------------------+
-| When timers are running based on CPU speed this is the timer to CPU frequency
-| ratio.
-+----------------------------------------------------------------------------*/
-#define PPC970_TB_RATIO 8
-
-/*----------------------------------------------------------------------------+
-| Cache line size.
-+----------------------------------------------------------------------------*/
-#define CACHE_LINE_SIZE_L1 128
-#define CACHE_LINE_SIZE_L2 128
-
-/*----------------------------------------------------------------------------+
-| SLB size.
-+----------------------------------------------------------------------------*/
-#define SLB_SIZE 64
-
-/*----------------------------------------------------------------------------+
-| TLB size.
-+----------------------------------------------------------------------------*/
-#define TLB_SIZE 1024
-
-/*----------------------------------------------------------------------------+
-| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64)
-| sprg0 (64), sprg1 (64), sprg2 (64), sprg3 (64), pvr (32) tblr (64), tbur (32)
-| registers are defined in as_archppc.h.
-+----------------------------------------------------------------------------*/
-#define SPR_ACCR 0x001D /* 64-bit read/write $*/
-#define SPR_ASR 0x0118 /* 64-bit read/write, write hypervisor only */
-#define SPR_DABR 0x03F5 /* 64-bit read/write, write hypervisor only */
-#define SPR_DABRX 0x03F7 /* 64-bit read/write, write hypervisor only */
-#define SPR_DAR 0x0013 /* 64-bit read/write */
-#define SPR_DEC 0x0016 /* 32-bit read/write */
-#define SPR_DSISR 0x0012 /* 32-bit read/write */
-#define SPR_HDEC 0x0136 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID0 0x03F0 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID1 0x03F1 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID4 0x03F4 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID5 0x03F6 /* 64-bit read/write, write hypervisor only */
-#define SPR_HIOR 0x0137 /* 64-bit read/write */
-#define SPR_HSPRG0 0x0130 /* 64-bit read/write, write hypervisor only */
-#define SPR_HSPRG1 0x0131 /* 64-bit read/write, write hypervisor only */
-#define SPR_HSRR0 0x013A /* 64-bit read/write, write hypervisor only */
-#define SPR_HSRR1 0x013B /* 64-bit read/write, write hypervisor only */
-#define SPR_IMC 0x030F /* 64-bit read/write */
-#define SPR_MMCR0 0x031B /* 64-bit read/write */
-#define SPR_MMCR1 0x031E /* 64-bit read/write */
-#define SPR_MMCRA 0x0312 /* 64-bit read/write */
-#define SPR_PIR 0x03FF /* 32-bit read */
-#define SPR_PMC1 0x0313 /* 32-bit read/write */
-#define SPR_PMC2 0x0314 /* 32-bit read/write */
-#define SPR_PMC3 0x0315 /* 32-bit read/write */
-#define SPR_PMC4 0x0316 /* 32-bit read/write */
-#define SPR_PMC5 0x0317 /* 32-bit read/write */
-#define SPR_PMC6 0x0318 /* 32-bit read/write */
-#define SPR_PMC7 0x0319 /* 32-bit read/write */
-#define SPR_PMC8 0x031A /* 32-bit read/write */
-#define SPR_SCOMC 0x0114 /* 64-bit read/write, write hypervisor only */
-#define SPR_SCOMD 0x0115 /* 64-bit read/write, write hypervisor only */
-#define SPR_SDAR 0x031D /* 64-bit read/write */
-#define SPR_SDR1 0x0019 /* 64-bit read/write, write hypervisor only */
-#define SPR_SIAR 0x031C /* 64-bit read/write */
-#define SPR_TBL_WRITE 0x011C /* 32-bit write */
-#define SPR_TBU_WRITE 0x011D /* 32-bit write */
-#define SPR_TRACE 0x03FE /* 64-bit read $*/
-#define SPR_TRIG0 0x03D0 /* 64-bit write */
-#define SPR_TRIG1 0x03D1 /* 64-bit write */
-#define SPR_TRIG2 0x03D2 /* 64-bit write */
-#define SPR_VRSAVE 0x0100 /* 64-bit read/write $*/
-
-/*----------------------------------------------------------------------------+
-| Vector status and control register is accessed using the mfvscr and mtvscr
-| instructions.
-+----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------+
-| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
-| register bits are defined in as_archppc.h. This is a 64-bit register.
-+----------------------------------------------------------------------------*/
-#define MSR_SF 0x8000000000000000 /* 64/32 bit mode indicator */
-#define MSR_HV 0x1000000000000000 /* hypervisor mode */
-#define MSR_VMX 0x0000000002000000 /* vmx unit available */
-#define MSR_POW 0x0000000000040000 /* power management enable */
-#define MSR_SE 0x0000000000000400 /* single step */
-#define MSR_BE 0x0000000000000200 /* branch trace */
-#define MSR_IS 0x0000000000000020 /* instruction address space */
-#define MSR_DS 0x0000000000000010 /* data address space */
-#define MSR_PM 0x0000000000000004 /* performance monitor */
-#define MSR_RI 0x0000000000000002 /* recoverable interrupt */
-
-/*----------------------------------------------------------------------------+
-| HID0 bits.
-+----------------------------------------------------------------------------*/
-#define HID0_ONEPPC 0x8000000000000000
-#define HID0_SINGLE 0x4000000000000000
-#define HID0_ISYNC_SC 0x2000000000000000
-#define HID0_SERIAL_G 0x1000000000000000
-#define HID0_DEEP_NAP 0x0100000000000000
-#define HID0_NAP 0x0040000000000000
-#define HID0_DPM 0x0010000000000000
-#define HID0_TR_GR 0x0004000000000000
-#define HID0_TR_DIS 0x0002000000000000
-#define HID0_NHR 0x0001000000000000
-#define HID0_INORDER 0x0000800000000000
-#define HID0_ENH_TR 0x0000400000000000
-#define HID0_TB_CTRL 0x0000200000000000
-#define HID0_EXT_TB_EN 0x0000100000000000
-#define HID0_CIABR_EN 0x0000020000000000
-#define HID0_HDEC_EN 0x0000010000000000
-#define HID0_EB_THERM 0x0000008000000000
-#define HID0_EN_ATTN 0x0000000100000000
-#define HID0_EN_MAC 0x0000000080000000
-
-/*----------------------------------------------------------------------------+
-| HID1 bits.
-+----------------------------------------------------------------------------*/
-#define HID1_BHT_PM 0xE000000000000000
-#define HID1_BHT_STATIC 0x0000000000000000
-#define HID1_BHT_GLOBAL 0x4000000000000000
-#define HID1_BHT_LOCAL 0x8000000000000000
-#define HID1_BHT_GL_LO 0xC000000000000000
-#define HID1_BHT_GL_CO 0x6000000000000000
-#define HID1_BHT_FULL 0xE000000000000000
-#define HID1_EN_LS 0x1000000000000000
-#define HID1_EN_CC 0x0800000000000000
-#define HID1_EN_IC 0x0400000000000000
-#define HID1_PF_MASK 0x0180000000000000
-#define HID1_PF_NSA 0x0080000000000000
-#define HID1_PF_NSA_P 0x0100000000000000
-#define HID1_PF_DIS 0x0180000000000000
-#define HID1_EN_ICBI 0x0040000000000000
-#define HID1_EN_IF_CACH 0x0020000000000000
-#define HID1_EN_IC_REC 0x0010000000000000
-#define HID1_EN_ID_REC 0x0008000000000000
-#define HID1_EN_ER_REC 0x0004000000000000
-#define HID1_IC_PE 0x0002000000000000
-#define HID1_ICD0_PE 0x0001000000000000
-#define HID1_ICD1_PE 0x0000800000000000
-#define HID1_IER_PE 0x0000400000000000
-#define HID1_EN_SP_ITW 0x0000200000000000
-#define HID1_S_CHICKEN 0x0000100000000000
-
-/*----------------------------------------------------------------------------+
-| HID4 bits.
-+----------------------------------------------------------------------------*/
-#define HID4_LPES0 0x8000000000000000
-#define HID4_RMLR12_MSK 0x6000000000000000
-#define HID4_LPID25_MSK 0x1E00000000000000
-#define HID4_RMOR_MASK 0x01FFFE0000000000
-#define HID4_RM_CI 0x0000010000000000
-#define HID4_FORCE_AI 0x0000008000000000
-#define HID4_DIS_PERF 0x0000004000000000
-#define HID4_RES_PERF 0x0000002000000000
-#define HID4_EN_SP_DTW 0x0000001000000000
-#define HID4_L1DC_FLSH 0x0000000800000000
-#define HID4_D_DERAT_P1 0x0000000400000000
-#define HID4_D_DERAT_P2 0x0000000200000000
-#define HID4_D_DERAT_G 0x0000000100000000
-#define HID4_D_DERAT_S1 0x0000000040000000
-#define HID4_D_DERAT_S2 0x0000000080000000
-#define HID4_DC_TP_S1 0x0000000020000000
-#define HID4_DC_TP_S2 0x0000000010000000
-#define HID4_DC_TP_GEN 0x0000000008000000
-#define HID4_DC_SET1 0x0000000004000000
-#define HID4_DC_SET2 0x0000000002000000
-#define HID4_DC_DP_S1 0x0000000001000000
-#define HID4_DC_DP_S2 0x0000000000800000
-#define HID4_DC_DP_GEN 0x0000000000400000
-#define HID4_R_TAG1P_CH 0x0000000000200000
-#define HID4_R_TAG2P_CH 0x0000000000100000
-#define HID4_TLB_PC1 0x0000000000080000
-#define HID4_TLB_PC2 0x0000000000040000
-#define HID4_TLB_PC3 0x0000000000020000
-#define HID4_TLB_PC4 0x0000000000010000
-#define HID4_TLB_P_GEN 0x0000000000008000
-#define HID4_TLB_SET1 0x0000000000003800
-#define HID4_TLB_SET2 0x0000000000005800
-#define HID4_TLB_SET3 0x0000000000006800
-#define HID4_TLB_SET4 0x0000000000007000
-#define HID4_DIS_SLBPC 0x0000000000000400
-#define HID4_DIS_SLBPG 0x0000000000000200
-#define HID4_MCK_INJ 0x0000000000000100
-#define HID4_DIS_STFWD 0x0000000000000080
-#define HID4_LPES1 0x0000000000000040
-#define HID4_RMLR0_MSK 0x0000000000000020
-#define HID4_DIS_SPLARX 0x0000000000000008
-#define HID4_LP_PG_EN 0x0000000000000004
-#define HID4_LPID01_MSK 0x0000000000000003
-
-/*----------------------------------------------------------------------------+
-| HID5 bits.
-+----------------------------------------------------------------------------*/
-#define HID5_HRMOR_MASK 0x00000000FFFF0000
-#define HID5_DC_MCK 0x0000000000002000
-#define HID5_DIS_PWRSAV 0x0000000000001000
-#define HID5_FORCE_G 0x0000000000000800
-#define HID5_DC_REPL 0x0000000000000400
-#define HID5_HWR_STMS 0x0000000000000200
-#define HID5_DST_NOOP 0x0000000000000100
-#define HID5_DCBZ_SIZE 0x0000000000000080
-#define HID5_DCBZ32_ILL 0x0000000000000040
-#define HID5_TLB_MAP 0x0000000000000020
-#define HID5_IMQ_PORT 0x0000000000000010
-#define HID5_LMP_SIZE0 0x0000000000000008
-#define HID5_DPFLOOD 0x0000000000000004
-#define HID5_TCH_NOP 0x0000000000000002
-#define HID5_LMP_SIZE1 0x0000000000000001
-
-/*----------------------------------------------------------------------------+
-| Specific SRR1 bit definitions for Machine Check.
-+----------------------------------------------------------------------------*/
-#define SRR1_IFU_UNREC 0x0000000000200000
-#define SRR1_LOAD_STORE 0x0000000000100000
-#define SRR1_SLB_PARITY 0x0000000000040000
-#define SRR1_TLB_PARITY 0x0000000000080000
-#define SRR1_ITLB_RELOA 0x00000000000C0000
-#define SRR1_RI 0x0000000000000002
-
-#endif /* _PPC970_H_ */
+/************ ppc970fx_board.h ****************/\r
+\r
+#ifndef _ppc970_h_\r
+#define _ppc970_h_\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Processor Version Register (PVR) values\r
++----------------------------------------------------------------------------*/\r
+#define PVR_970 0x0039 /* 970 any revision*/\r
+#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */\r
+#define PVR_970FX 0x003C /* 970FX any revision*/\r
+#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */\r
+#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */\r
+#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */\r
+#define PVR_RESERVED 0x000000F0 /* reserved nibble */\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Supported platforms.\r
++----------------------------------------------------------------------------*/\r
+#define PLATFORM_EVB_LITE 3\r
+#define PLATFORM_EVB_FINAL 4\r
+\r
+/*----------------------------------------------------------------------------+\r
+| When timers are running based on CPU speed this is the timer to CPU frequency\r
+| ratio.\r
++----------------------------------------------------------------------------*/\r
+#define PPC970_TB_RATIO 8\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Cache line size.\r
++----------------------------------------------------------------------------*/\r
+#define CACHE_LINE_SIZE_L1 128\r
+#define CACHE_LINE_SIZE_L2 128\r
+\r
+/*----------------------------------------------------------------------------+\r
+| SLB size.\r
++----------------------------------------------------------------------------*/\r
+#define SLB_SIZE 64\r
+\r
+/*----------------------------------------------------------------------------+\r
+| TLB size.\r
++----------------------------------------------------------------------------*/\r
+#define TLB_SIZE 1024\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Partial memory map.\r
++----------------------------------------------------------------------------*/\r
+#define SDRAM_BASE 0x0000000000000000UL\r
+#define SDRAM_SIZE 0x0000000080000000UL\r
+#define IO_BASE 0x0000000080000000UL\r
+#define IO_SIZE 0x0000000080000000UL\r
+#define PCI_BUS_MEM_BASE 0x0000000080000000UL\r
+#define PCI_BUS_MEM_SIZE 0x0000000070000000UL\r
+#define PCI0_BASE 0x00000000F0000000UL\r
+#define PCI0_SIZE 0x0000000002000000UL\r
+#define HT1_BASE 0x00000000F2000000UL\r
+#define HT1_SIZE 0x0000000003000000UL\r
+#define PPC925_BASE 0x00000000F8000000UL\r
+#define PPC925_SIZE 0x0000000001000000UL\r
+#define SB_IOAPIC_BASE 0x00000000FEC00000UL\r
+#define BOOT_BASE 0x00000000FF000000UL\r
+#define BOOT_BASE_AS 0x00000000FF000000\r
+#define BOOT_END 0x00000000FFFFFFFFUL\r
+#define FLASH_BASE_INTEL 0x00000000FF800000UL\r
+#define FLASH_BASE_INTEL_AS 0x00000000FF800000\r
+#define FLASH_BASE_AMD 0x00000000FFF00000UL\r
+#define FLASH_BASE_AMD_AS 0x00000000FFF00000\r
+#define SDRAM_UPPER_BASE 0x0000000100000000UL\r
+#define SDRAM_UPPER_SIZE 0x0000000F00000000UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| BOOT_STACK_ADDR is data used for stack before SDRAM is available. This data\r
+| will be written to memory after the SDRAM is initialized. All values here\r
+| must be less than 32 bits. Following 13 defines need to be changed when\r
+| changing the location of PIBS in SDRAM (the link file also need to be\r
+| changed in order to fully relocate PIBS.\r
++----------------------------------------------------------------------------*/\r
+#define PIBS_BASE_ADDR 0x00C00000\r
+#define BOOT_STACK_ADDR 0x00C50000\r
+#define BOOT_STACK_SIZE 0x00004000\r
+#define MEM_CHK_START_ADDR 0x00C40000\r
+#define MEM_CHK_SIZE 0x00010000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Address of a CPU0, CPU1 shared memory structure.\r
++----------------------------------------------------------------------------*/\r
+#define CPU1_DATA_STRUCT_ADDR 0x00C00040\r
+#define CPU1_DATA_STRUCT_SRR0_OFF 0x00000000\r
+#define CPU1_DATA_STRUCT_SRR1_OFF 0x00000008\r
+#define CPU1_DATA_STRUCT_R3_OFF 0x00000010\r
+#define CPU1_DATA_STRUCT_VALID_OFF 0x00000018\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Address of the memory location used for the test and set instruction\r
+| sequence.\r
++----------------------------------------------------------------------------*/\r
+#define VM_TEST_AND_SET_ADDR 0x0000000000C000F0UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Initial page table address.\r
++----------------------------------------------------------------------------*/\r
+#define INITIAL_PAGE_TABLE_ADDR_CPU0 0x0000000000D00000\r
+#define INITIAL_PAGE_TABLE_ADDR_CPU1 0x0000000000D40000\r
+#define INITIAL_PAGE_TABLE_SIZE 0x0000000000040000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Initial stack size. Must be less than 32 bits in length.\r
++----------------------------------------------------------------------------*/\r
+#define MY_MAIN_STACK_SIZE (8* 1024)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Serial port address. The base address must be programmed into super I/O. The\r
+| external time base is available only on JS20.\r
++----------------------------------------------------------------------------*/\r
+#define UART1_MMIO_BASE 0xF40002F8UL\r
+#define UART0_MMIO_BASE 0xF40003F8UL\r
+#define UART1_MMIO_OFFSET 0x2F8;\r
+#define UART0_MMIO_OFFSET 0x3F8;\r
+#define UART_INPUT_CLOCK 1843200\r
+#define EXT_TIME_BASE_FREQ 0\r
+#define DIV_HIGH_9600 0x00\r
+#define DIV_LOW_9600 0x0C\r
+\r
+#define EXT_IRQ_COM1 EXT_SB_HT4\r
+#define EXT_IRQ_COM2 EXT_SB_HT3\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Locations in Super I/O NVRAM where service processor stores information for\r
+| the PPC970FX CPU.\r
++----------------------------------------------------------------------------*/\r
+#define SUPER_IO_NVRAM_DATA_VALID 64\r
+#define SUPER_IO_NVRAM_SYS_CLK (SUPER_IO_NVRAM_DATA_VALID+ 0x04)\r
+#define SUPER_IO_NVRAM_CLK_MULT (SUPER_IO_NVRAM_SYS_CLK+ 0x04)\r
+#define SUPER_IO_NVRAM_EI_RATIO (SUPER_IO_NVRAM_CLK_MULT+ 0x01)\r
+\r
+#define SUPER_IO_VALID_VALUE 0x426F4F6D\r
+\r
+#define PPC970_EI_RATIO_000 2\r
+#define PPC970_EI_RATIO_001 3\r
+#define PPC970_EI_RATIO_010 4\r
+#define PPC970_EI_RATIO_011 6\r
+#define PPC970_EI_RATIO_100 8\r
+#define PPC970_EI_RATIO_101 12\r
+#define PPC970_EI_RATIO_110 16\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Locations in Super I/O NVRAM where PPC970 store commands for service\r
+| processor. 0x01 is written by PPC970 to initiate action by the service\r
+| processor. This value is cleared by the service processor upon receiving\r
+| the command.\r
++----------------------------------------------------------------------------*/\r
+#define SUPER_IO_NVRAM_POWER_OFF 96\r
+#define SUPER_IO_NVRAM_RESTART (SUPER_IO_NVRAM_POWER_OFF+ 0x2)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Default HID register settings.\r
++----------------------------------------------------------------------------*/\r
+#define HID0_PREFEAR 0x0011008180000000\r
+#define HID1_PREFEAR 0xFD3C200000000000\r
+#define HID4_PREFEAR 0x0000001000000000\r
+#define HID5_PREFEAR 0x0000000000000080\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Power control SCOM register definitions.\r
++----------------------------------------------------------------------------*/\r
+#define SCOM_ADDR_PCR_WRITE 0x000000000AA00000UL\r
+#define SCOM_ADDR_PCR_WRITE_ASM 0x000000000AA00000\r
+#define SCOM_ADDR_PSR_READ 0x0000000040808000UL\r
+#define SCOM_ADDR_PSR_READ_ASM 0x0000000040808000\r
+\r
+#define SCOM_ADDR_PCR_DATA_MASK 0x0000000080000000UL\r
+#define SCOM_ADDR_PCR_DATA_MASK_ASM 0x0000000080000000\r
+\r
+#define SCOM_ADDR_PCR_FREQ_VALID 0x0000000000010000UL\r
+#define SCOM_ADDR_PCR_FREQ_FULL 0x0000000000000000UL\r
+#define SCOM_ADDR_PCR_FREQ_HALF 0x0000000000020000UL\r
+#define SCOM_ADDR_PCR_FREQ_QUARTER 0x0000000000040000UL\r
+\r
+#define SCOM_PSR_FREQ_MASK 0x0300000000000000UL\r
+#define SCOM_PSR_FREQ_FULL 0x0000000000000000UL\r
+#define SCOM_PSR_FREQ_HALF 0x0100000000000000UL\r
+#define SCOM_PSR_FREQ_QUARTER 0x0200000000000000UL\r
+#define SCOM_PSR_COMM_COMPLETED 0x1000000000000000UL\r
+#define SCOM_PSR_COMM_COMPLETED_ASM 0x1000000000000000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Serial port for CPU2\r
++----------------------------------------------------------------------------*/\r
+#define CPU2_SERIAL_PORT 2\r
+#define CPU2_BAUD_RATE 115200\r
+\r
+/*----------------------------------------------------------------------------+\r
+| External interrupt assignments.\r
++----------------------------------------------------------------------------*/\r
+#define EXT_I2C_MASTER 0\r
+#define EXT_VSP 1\r
+#define EXT_HT1_BRIDGE 2\r
+#define EXT_PCI0_AGP_BRIDGE 3\r
+#define EXT_SLEEP0 4\r
+#define EXT_SLEEP1 5\r
+#define EXT_SB_HT0 6\r
+#define EXT_SB_HT1 7\r
+#define EXT_SB_HT2 8\r
+#define EXT_SB_HT3 9\r
+#define EXT_SB_HT4 10\r
+#define EXT_SB_HT5 11\r
+#define EXT_SB_HT6 12\r
+#define EXT_SB_HT7 13\r
+#define EXT_SB_HT8 14\r
+#define EXT_SB_HT9 15\r
+#define EXT_SB_HT10 16\r
+#define EXT_SB_HT11 17\r
+#define EXT_SB_HT12 18\r
+#define EXT_SB_HT13 19\r
+#define EXT_SB_HT14 20\r
+#define EXT_SB_HT15 21\r
+#define EXT_SB_HT16 22\r
+#define EXT_SB_HT17 23\r
+#define EXT_SB_HT18 24\r
+#define EXT_SB_HT19 25\r
+#define EXT_SB_HT20 26\r
+#define EXT_SB_HT21 27\r
+#define EXT_SB_HT22 28\r
+#define EXT_SB_HT23 29\r
+#define EXT_SB_HT24 30\r
+#define EXT_SB_HT25 31\r
+#define EXT_SB_HT26 32\r
+#define EXT_SB_HT27 33\r
+#define EXT_SB_HT28 34\r
+#define EXT_SB_HT29 35\r
+#define EXT_SB_HT30 36\r
+#define EXT_SB_HT31 37\r
+#define EXT_SB_HT32 38\r
+#define EXT_SB_HT33 39\r
+#define EXT_SB_HT34 40\r
+#define EXT_SB_HT35 41\r
+#define EXT_SB_HT36 42\r
+#define EXT_SB_HT37 43\r
+#define EXT_SB_HT38 44\r
+#define EXT_SB_HT39 45\r
+#define EXT_SB_HT40 46\r
+#define EXT_SB_HT41 47\r
+#define EXT_SB_HT42 48\r
+#define EXT_SB_HT43 49\r
+#define EXT_SB_HT44 50\r
+#define EXT_SB_HT45 51\r
+#define EXT_SB_HT46 52\r
+#define EXT_SB_HT47 53\r
+#define EXT_SB_HT48 54\r
+#define EXT_SB_HT49 55\r
+#define EXT_SB_HT50 56\r
+#define EXT_SB_HT51 57\r
+#define EXT_SB_HT52 58\r
+#define EXT_SB_HT53 59\r
+#define EXT_SB_HT54 60\r
+#define EXT_SB_HT55 61\r
+#define EXT_SB_HT56 62\r
+#define EXT_SB_HT57 63\r
+#define EXT_SB_HT58 64\r
+#define EXT_SB_HT59 65\r
+#define EXT_SB_HT60 66\r
+#define EXT_SB_HT61 67\r
+#define EXT_SB_HT62 68\r
+#define EXT_SB_HT63 69\r
+#define EXT_SB_HT64 70\r
+#define EXT_SB_HT65 71\r
+#define EXT_SB_HT66 72\r
+#define EXT_SB_HT67 73\r
+#define EXT_SB_HT68 74\r
+#define EXT_SB_HT69 75\r
+#define EXT_SB_HT70 76\r
+#define EXT_SB_HT71 77\r
+#define EXT_SB_HT72 78\r
+#define EXT_SB_HT73 79\r
+#define EXT_SB_HT74 80\r
+#define EXT_SB_HT75 81\r
+#define EXT_SB_HT76 82\r
+#define EXT_SB_HT77 83\r
+#define EXT_SB_HT78 84\r
+#define EXT_SB_HT79 85\r
+#define EXT_SB_HT80 86\r
+#define EXT_SB_HT81 87\r
+#define EXT_SB_HT82 88\r
+#define EXT_SB_HT83 89\r
+#define EXT_SB_HT84 90\r
+#define EXT_SB_HT85 91\r
+#define EXT_SB_HT86 92\r
+#define EXT_SB_HT87 93\r
+#define EXT_SB_HT88 94\r
+#define EXT_SB_HT90 95\r
+#define EXT_SB_HT91 96\r
+#define EXT_SB_HT92 97\r
+#define EXT_SB_HT93 98\r
+#define EXT_SB_HT94 99\r
+#define EXT_SB_HT95 100\r
+#define EXT_SB_HT96 101\r
+#define EXT_SB_HT97 102\r
+#define EXT_SB_HT98 103\r
+#define EXT_SB_HT99 104\r
+#define EXT_SB_HT100 105\r
+#define EXT_SB_HT101 106\r
+#define EXT_SB_HT102 107\r
+#define EXT_SB_HT103 108\r
+#define EXT_SB_HT104 109\r
+#define EXT_SB_HT105 110\r
+#define EXT_SB_HT106 111\r
+#define EXT_SB_HT107 112\r
+#define EXT_SB_HT108 113\r
+#define EXT_SB_HT109 114\r
+#define EXT_SB_HT110 115\r
+#define EXT_SB_HT111 116\r
+#define EXT_SB_HT112 117\r
+#define EXT_SB_HT113 118\r
+#define EXT_SB_HT114 119\r
+#define EXT_SB_HT115 120\r
+#define EXT_SB_HT116 121\r
+#define EXT_SB_HT117 122\r
+#define EXT_SB_HT118 123\r
+#define EXT_IPI_0 124\r
+#define EXT_IPI_1 125\r
+#define EXT_MAX_IRQ_NUM 125\r
+\r
+/*----------------------------------------------------------------------------+\r
+| # # # ###### #######\r
+| # # # # # # #\r
+| # # # # # # #\r
+| # # # # ###### #\r
+| # # ####### # # #\r
+| # # # # # # #\r
+| ##### # # # # #\r
++----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Interrupt Enable Register. DLAB must be set to 0 access this register.\r
++----------------------------------------------------------------------------*/\r
+#define asyncIER 1\r
+#define asyncIERModem 0x08\r
+#define asyncIERLine 0x04\r
+#define asyncIERTransmit 0x02\r
+#define asyncIERReceive 0x01\r
+#define asyncIERdisableAll 0x00\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Interrupt Identification Register. Read only register.\r
++----------------------------------------------------------------------------*/\r
+#define asyncIIR 2\r
+#define asyncIIRMask 0x0F\r
+#define asyncIIRFifoTimeout 0x0C\r
+#define asyncIIRLine 0x06\r
+#define asyncIIRReceive 0x04\r
+#define asyncIIRTransmit 0x02\r
+#define asyncIIRNoInterrupt 0x01\r
+#define asyncIIRModem 0x00\r
+\r
+/*----------------------------------------------------------------------------+\r
+| FIFO Control Register. Write only register.\r
++----------------------------------------------------------------------------*/\r
+#define asyncFCR 2\r
+#define asyncFCRFifoTrigger14 0xC0\r
+#define asyncFCRFifoTrigger8 0x80\r
+#define asyncFCRFifoTrigger4 0x40\r
+#define asyncFCRFifoTrigger1 0x00\r
+#define asyncFCRDmaSet 0x08\r
+#define asyncFCRClearXmitFifo 0x04\r
+#define asyncFCRClearRcvFifo 0x02\r
+#define asyncFCRFifoEnable 0x01\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Line Control Register.\r
++----------------------------------------------------------------------------*/\r
+#define asyncLCR 3\r
+#define asyncLCRDLAB 0x80\r
+#define asyncLCRSetBreak 0x40\r
+#define asyncLCRStickParity 0x20\r
+#define asyncLCREvenParity 0x10\r
+#define asyncLCROddParity 0x00\r
+#define asyncLCRParityEnable 0x08\r
+#define asyncLCRParityDisable 0x00\r
+#define asyncLCRStopBitsTwo 0x04\r
+#define asyncLCRStopBitsOne 0x00\r
+#define asyncLCRWordLengthSel 0x03\r
+#define asyncLCRWordLength5 0x00\r
+#define asyncLCRWordLength6 0x01\r
+#define asyncLCRWordLength7 0x02\r
+#define asyncLCRWordLength8 0x03\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Modem Control Register.\r
++----------------------------------------------------------------------------*/\r
+#define asyncMCR 4\r
+#define asyncMCRLoop 0x10\r
+#define asyncMCROut2 0x08\r
+#define asyncMCROut1 0x04\r
+#define asyncMCRRTS 0x02\r
+#define asyncMCRDTR 0x01\r
+#define asyncMCRdisableAll 0x00\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Line Status Register.\r
++----------------------------------------------------------------------------*/\r
+#define asyncLSR 5\r
+#define asyncLSRRxFifoError 0x80\r
+#define asyncLSRTxEmpty 0x60\r
+#define asyncLSRTxShiftEmpty 0x40\r
+#define asyncLSRTxHoldEmpty 0x20\r
+#define asyncLSRBreakInterrupt 0x10\r
+#define asyncLSRFramingError 0x08\r
+#define asyncLSRParityError 0x04\r
+#define asyncLSROverrunError 0x02\r
+#define asyncLSRDataReady 0x01\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Modem Status Register. Read only register.\r
++----------------------------------------------------------------------------*/\r
+#define asyncMSR 6\r
+#define asyncMSRCD 0x80\r
+#define asyncMSRRI 0x40\r
+#define asyncMSRDSR 0x20\r
+#define asyncMSRCTS 0x10\r
+#define asyncMSRDeltaDCD 0x08\r
+#define asyncMSRDeltaRI 0x04\r
+#define asyncMSRDeltaDSR 0x02\r
+#define asyncMSRDeltaCTS 0x01\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Miscellanies defines.\r
++----------------------------------------------------------------------------*/\r
+#define asyncScratchReg 7\r
+#define asyncTxBuffer 0\r
+#define asyncRxBuffer 0\r
+#define asyncDLABLsb 0\r
+#define asyncDLABMsb 1\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ##### ###### ##### ##### ##### #######\r
+| # # # # # # # # # # #\r
+| # # # # # # # #\r
+| # ###### # ###### ##### ######\r
+| # # # # # #\r
+| # # # # # # # # # #\r
+| ##### # ##### ##### ####### #####\r
++----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------+\r
+| When performing PCI configuration read/write the configuration address\r
+| register must be written and then read before configuration data register is\r
+| accessed.\r
+| PCI type 0 Configuration address format is:\r
+| 0-20 id. sel., 21-23 function number, 24-29 register number|00\r
++----------------------------------------------------------------------------*/\r
+#define NB_PCI_CONFIGURATION_ADDR 0x0F0800000UL\r
+#define NB_PCI_CONFIGURATION_DATA 0x0F0C00000UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| When performing HT configuration read/write the configuration address\r
+| register must be written and then read before configuration data register is\r
+| accessed.\r
+| HT type 0 Configuration address format is:\r
+| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|00\r
+| HT type 1 configuration address format is\r
+| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|01\r
++----------------------------------------------------------------------------*/\r
+#define NB_HT_CONFIGURATION_ADDR 0x0F2800000UL\r
+#define NB_HT_CONFIGURATION_DATA 0x0F2C00000UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HT Configuration Address Spaces.\r
++----------------------------------------------------------------------------*/\r
+#define NB_HT_CONFIG_TYPE_0_BASE 0x0F2000000UL\r
+#define NB_HT_CONFIG_TYPE_1_BASE 0x0F3000000UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HT I/O Space. NB_HT_IO_RESERVED is reserved for Super I/O peripherals. The\r
+| SuperI/O utilizes subtractive decode. All PCI I/0 addresses are translated\r
+| from 0xF4xxxxxx (CPU) to 0x00xxxxxx (PCI).\r
++----------------------------------------------------------------------------*/\r
+#define NB_HT_IO_BASE_CPU 0x0F4000000UL\r
+#define NB_HT_IO_BASE_BYTE 0xF4\r
+#define NB_HT_IO_BASE_BYTE_SH 24\r
+#define NB_HT_IO_BASE_PCI 0x000000000UL\r
+#define NB_HT_IO_BASE_ASM 0xF4000000\r
+#define NB_HT_IO_SIZE 0x000400000UL\r
+#define NB_HT_IO_RESERVED 0x000010000UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HT EOI Space.\r
++----------------------------------------------------------------------------*/\r
+#define NB_HT_EOI_BASE 0x0F4400000UL\r
+#define NB_HT_EOI_SIZE 0x000400000UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HT Device Header Regs. Big Endian.\r
++----------------------------------------------------------------------------*/\r
+#define NB_HT_REG_BASE 0x0F8070000UL\r
+#define NB_HT_DID_VID 0x0F8070000UL\r
+#define NB_HT_STAT_CMD 0x0F8070010UL\r
+#define NB_HT_CLASS_REV 0x0F8070020UL\r
+#define NB_HT_BIST_HT 0x0F8070030UL\r
+#define NB_HT_CAP_PTR 0x0F80700D0UL\r
+#define NB_HT_INT_LINE 0x0F80700F0UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HT Capabilities Block. Big Endian.\r
++----------------------------------------------------------------------------*/\r
+#define NB_HT_CMD_PTR_ID 0x0F8070100UL\r
+#define HT_WARM_RESET 0x00010000\r
+#define NB_HT_LINK_CFG_CONTROL 0x0F8070110UL\r
+#define HT_CRC_ERR 0x00000F00\r
+#define HT_END_OF_CHAIN 0x00000040\r
+#define HT_INIT 0x00000020\r
+#define HT_LINK_FAIL 0x00000010\r
+#define HT_LINK_OUT_MASK 0x70000000\r
+#define HT_LINK_IN_MASK 0x07000000\r
+#define HT_LINK_MAX_OUT_MASK 0x00700000\r
+#define HT_LINK_MAX_IN_MASK 0x00070000\r
+#define HT_LINK_WIDTH_8_BIT 0x0\r
+#define HT_LINK_WIDTH_16_BIT 0x1\r
+#define HT_LINK_WIDTH_32_BIT 0x3\r
+#define HT_LINK_WIDTH_2_BIT 0x4\r
+#define HT_LINK_WIDTH_4_BIT 0x5\r
+#define NB_HT_LINK_FREQ_ERROR 0x0F8070120UL\r
+#define HT_LINK_FREQ_CAP_MASK 0xFFFF0000\r
+#define HT_LINK_FREQ_MASK 0x00000F00\r
+#define HT_LINK_FREQ_200 0x0\r
+#define HT_LINK_FREQ_300 0x1\r
+#define HT_LINK_FREQ_400 0x2\r
+#define HT_LINK_FREQ_500 0x3\r
+#define HT_LINK_FREQ_600 0x4\r
+#define HT_LINK_FREQ_800 0x5\r
+#define HT_LINK_FREQ_1000 0x6\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HT Other registers. Big Endian.\r
++----------------------------------------------------------------------------*/\r
+#define NB_HT_ADDRESS_MASK 0x0F8070200UL\r
+#define NB_HT_PROCESSOR_INT_CONTROL 0x0F8070210UL\r
+#define NB_HT_BRIDGE_CONTROL 0x0F8070300UL\r
+#define HT_SECBUSRESET 0x00400000\r
+#define NB_HT_TXCTL_DATABUFALLOC 0x0F8070310UL\r
+#define NB_HT_TXBUFCOUNTMAX 0x0F8070340UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Accessed through AGP/PCI configuration space on PCI0 bus.\r
++----------------------------------------------------------------------------*/\r
+#define NB_PCI_ADDRESS_MASK 0x48\r
+#define NB_PCI_ADDRESS_MASK_RVALUE 0x00000003\r
+\r
+/*----------------------------------------------------------------------------+\r
+| MPIC\r
++----------------------------------------------------------------------------*/\r
+#define NB_MPIC_TOGGLE 0x0F80000E0UL\r
+#define NB_MPIC_ENABLE_OUT 0x00000004\r
+#define NB_MPIC_RESET 0x00000002\r
+\r
+#define NB_MPIC_BASE 0x0F8040000UL\r
+#define NB_MPIC_SIZE 0x000040000UL\r
+\r
+#define NB_MPIC_FEATURE 0x0F8041000UL\r
+#define NB_MPIC_GLOBAL0 0x0F8041020UL\r
+#define NB_MPIC_GLOBAL0_MPIC_RESET 0x80000000U\r
+#define NB_MPIC_IPI0_VECT_PRIO 0x0F80410A0UL\r
+#define NB_MPIC_IPI1_VECT_PRIO 0x0F80410B0UL\r
+#define NB_MPIC_SPURIOUS_VECTOR 0x0F80410E0UL\r
+\r
+#define NB_MPIC_S0_VECT_PRIO 0x0F8050000UL\r
+#define NB_MPIC_VECT_PRIO_ADDER 0x00000020\r
+#define NB_MPIC_S0_DESINATION 0x0F8050010UL\r
+#define NB_MPIC_DESINATION_ADDER 0x00000020\r
+\r
+#define NB_MPIC_P0_IPI0_DISPATCH 0x0F8060040UL\r
+#define NB_MPIC_P0_IPI1_DISPATCH 0x0F8060050UL\r
+#define NB_MPIC_P0_TASK_PRIO 0x0F8060080UL\r
+#define NB_MPIC_P0_INT_ACK 0x0F80600A0UL\r
+#define NB_MPIC_P0_INT_ACK_AS 0x0F80600A0\r
+#define NB_MPIC_P0_EIO 0x0F80600B0UL\r
+#define NB_MPIC_P0_EIO_AS 0x0F80600B0\r
+#define NB_MPIC_P1_IPI0_DISPATCH 0x0F8061040UL\r
+#define NB_MPIC_P1_IPI1_DISPATCH 0x0F8061050UL\r
+#define NB_MPIC_P1_TASK_PRIO 0x0F8061080UL\r
+#define NB_MPIC_P1_INT_ACK 0x0F80610A0UL\r
+#define NB_MPIC_P1_INT_ACK_AS 0x0F80610A0\r
+#define NB_MPIC_P1_EIO 0x0F80610B0UL\r
+#define NB_MPIC_P1_EIO_AS 0x0F80610B0\r
+\r
+#define NB_MPIC_IPI_PRIO_MASK 0x000F0000\r
+#define NB_MPIC_IPI_PRIO_SH 16\r
+#define NB_MPIC_IPI_VECTOR_MASK 0x000000FF\r
+#define NB_MPIC_IPI_MASK 0x80000000U\r
+#define NB_MPIC_IPI_ACTIVE 0x40000000\r
+\r
+#define NB_MPIC_EXT_PRIO_MASK 0x000F0000\r
+#define NB_MPIC_EXT_PRIO_SH 16\r
+#define NB_MPIC_EXT_VECTOR_MASK 0x000000FF\r
+#define NB_MPIC_EXT_MASK 0x80000000U\r
+#define NB_MPIC_EXT_ACTIVE 0x40000000\r
+#define NB_MPIC_EXT_SENSE 0x00400000\r
+\r
+#define NB_MPIC_DEST_CPU0 0x00000001\r
+#define NB_MPIC_DEST_CPU1 0x00000002\r
+\r
+#define NB_MPIC_IPI_CPU0 0x00000001\r
+#define NB_MPIC_IPI_CPU1 0x00000002\r
+\r
+#define NB_MPIC_TASK_PRIO_MASK 0x0000000F\r
+\r
+#define NB_MPIC_C0_CASCADE 0x20000000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| I2C\r
++----------------------------------------------------------------------------*/\r
+#define NB_IIC_MMIO_BASE 0xF8001000UL\r
+#define NB_IIC_MMIO_BASE_BYTE4 0xF8\r
+#define NB_IIC_MMIO_BASE_BYTE5 0x00\r
+#define NB_IIC_MMIO_BASE_BYTE6 0x10\r
+#define NB_IIC_MMIO_BASE_BYTE7 0x00\r
+#define NB_IIC_MMIO_BASE_MASK 0xFFFFFFFF\r
+#define NB_IIC_MMIO_SIZE 0x00001000UL\r
+#define NB_IIC_MODE 0x00\r
+#define NB_IIC_CNTRL 0x10\r
+#define NB_IIC_STATUS 0x20\r
+#define NB_IIC_ISR 0x30\r
+#define NB_IIC_IER 0x40\r
+#define NB_IIC_ADDR 0x50\r
+#define NB_IIC_SUBADDR 0x60\r
+#define NB_IIC_DATA 0x70\r
+#define NB_IIC_REV 0x80\r
+#define NB_IIC_RISETTIMECNT 0x90\r
+#define NB_IIC_BITTIMECNT 0xA0\r
+\r
+#define IIC_MODE_PORTSEL0 0x00000000\r
+#define IIC_MODE_PORTSEL1 0x00000010\r
+#define IIC_MODE_APMODE_MANUAL 0x00000000\r
+#define IIC_MODE_APMODE_STANDARD 0x00000004\r
+#define IIC_MODE_APMODE_SUBADDR 0x00000008\r
+#define IIC_MODE_APMODE_COMBINED 0x0000000C\r
+#define IIC_MODE_SPEED_25 0x00000002\r
+#define IIC_MODE_SPEED_50 0x00000001\r
+#define IIC_MODE_SPEED_100 0x00000000\r
+\r
+#define IIC_CNTRL_STOP 0x00000004\r
+#define IIC_CNTRL_XADDR 0x00000002\r
+#define IIC_CNTRL_AAK 0x00000001\r
+\r
+#define IIC_STATUS_LASTAAK 0x00000002\r
+\r
+#define IIC_ISR_ISTOP 0x00000004\r
+#define IIC_ISR_IADDR 0x00000002\r
+#define IIC_ISR_IDATA 0x00000001\r
+\r
+/*----------------------------------------------------------------------------+\r
+| DDR_SDRAM Controller\r
++----------------------------------------------------------------------------*/\r
+#define NB_SDRAM_BASE 0xF8002000UL\r
+#define NB_SDRAM_BASE_BYTE4 0xF8\r
+#define NB_SDRAM_BASE_BYTE5 0x00\r
+#define NB_SDRAM_BASE_BYTE6 0x20\r
+#define NB_SDRAM_BASE_BYTE7 0x00\r
+#define NB_SDRAM_BASE_MASK 0xFFFFFFFF\r
+#define NB_SDRAM_SIZE 0x00001000UL\r
+#define NB_SDRAM_MEMTIMINGPARAM 0x050\r
+#define NB_SDRAM_MEMPROGCNTL 0x0E0\r
+#define NB_SDRAM_MRS 0x0F0\r
+#define NB_SDRAM_MRSREGCNTL 0x0F0\r
+#define NB_SDRAM_EMRS 0x100\r
+#define NB_SDRAM_EMRSREGCNTL 0x100\r
+#define NB_SDRAM_MEMBUSCFG 0x190\r
+#define NB_SDRAM_MEMMODE0 0x1C0\r
+#define NB_SDRAM_MEMBOUNDAD0 0x1D0\r
+#define NB_SDRAM_MEMMODE1 0x1E0\r
+#define NB_SDRAM_MEMBOUNDAD1 0x1F0\r
+#define NB_SDRAM_MEMMODE2 0x200\r
+#define NB_SDRAM_MEMBOUNDAD2 0x210\r
+#define NB_SDRAM_MEMMODE3 0x220\r
+#define NB_SDRAM_MEMBOUNDAD3 0x230\r
+#define NB_SDRAM_MEMMODE4 0x240\r
+#define NB_SDRAM_MEMBOUNDAD4 0x250\r
+#define NB_SDRAM_MEMMODE5 0x260\r
+#define NB_SDRAM_MEMBOUNDAD5 0x270\r
+#define NB_SDRAM_MEMMODE6 0x280\r
+#define NB_SDRAM_MEMBOUNDAD6 0x290\r
+#define NB_SDRAM_MEMMODE7 0x2A0\r
+#define NB_SDRAM_MEMBOUNDAD7 0x2B0\r
+#define NB_SDRAM_MSCR 0x400\r
+#define NB_SDRAM_MSRSR 0x410\r
+#define NB_SDRAM_MSRER 0x420\r
+#define NB_SDRAM_MSPR 0x430\r
+#define NB_SDRAM_MCCR 0x440\r
+#define NB_SDRAM_MEMMODECNTL 0x500\r
+#define NB_SDRAM_DELMEASSTATE 0x510\r
+#define NB_SDRAM_CKDELADJ 0x520\r
+#define NB_SDRAM_IOMODECNTL 0x530\r
+#define NB_SDRAM_DQSDELADJ0 0x600\r
+#define NB_SDRAM_DQSDATADELADJ0 0x610\r
+\r
+#define SDRAM_MEMORY_MODE_256M_16Mx16 0x0A000000\r
+#define SDRAM_MEMORY_MODE_256M_32Mx8 0x0C000000\r
+#define SDRAM_MEMORY_MODE_512M_64Mx8 0x0E000000\r
+#define SDRAM_MEMORY_MODE_1G_64Mx16 0x10000000\r
+#define SDRAM_MEMORY_MODE_1G_128Mx8 0x12000000\r
+\r
+#define SDRAM_MEMMODE_BANKEN 0x40000000\r
+#define SDRAM_MEMMODE_BASEBANKADDR 0x01000000\r
+#define SDRAM_MEMMODE_LSSIDE 0x00800000\r
+#define SDRAM_MEMMODE_HSSIDE 0x00400000\r
+\r
+#define SDRAM_MEMBOUNDAD_BASEBANKADDR 0xFF000000\r
+\r
+#define SDRAM_MEMPROGCNTL_SL 0x80000000\r
+#define SDRAM_MEMPROGCNTL_WDR 0x40000000\r
+\r
+#define SDRAM_MTP_RCD_MASK 0xE0000000\r
+#define SDRAM_MTP_RP_MASK 0x1C000000\r
+#define SDRAM_MTP_RAS_MASK 0x03800000\r
+#define SDRAM_MTP_WRT 0x00400000\r
+#define SDRAM_MTP_RFC_MASK 0x003C0000\r
+#define SDRAM_MTP_WRCD 0x00020000\r
+#define SDRAM_MTP_CAS_RR_MASK 0x0001C000\r
+#define SDRAM_MTP_CAS_RW_MASK 0x00003800\r
+#define SDRAM_MTP_TRFCX2 0x00000400\r
+\r
+#define SDRAM_MTP_RCD_2 0x20000000\r
+#define SDRAM_MTP_RCD_3 0x40000000\r
+#define SDRAM_MTP_RCD_4 0x60000000\r
+#define SDRAM_MTP_RCD_5 0x80000000\r
+#define SDRAM_MTP_RCD_6 0xA0000000\r
+#define SDRAM_MTP_RP_2 0x04000000\r
+#define SDRAM_MTP_RP_3 0x08000000\r
+#define SDRAM_MTP_RP_4 0x0C000000\r
+#define SDRAM_MTP_RP_5 0x10000000\r
+#define SDRAM_MTP_RP_6 0x14000000\r
+#define SDRAM_MTP_RAS_4 0x00000000\r
+#define SDRAM_MTP_RAS_5 0x00800000\r
+#define SDRAM_MTP_RAS_6 0x01000000\r
+#define SDRAM_MTP_RAS_7 0x01800000\r
+#define SDRAM_MTP_RAS_8 0x02000000\r
+#define SDRAM_MTP_CAS_RR_2 0x00008000\r
+#define SDRAM_MTP_CAS_RR_3 0x0000C000\r
+#define SDRAM_MTP_CAS_RR_4 0x00010000\r
+#define SDRAM_MTP_CAS_RR_5 0x00014000\r
+#define SDRAM_MTP_CAS_RR_25 0x00018000\r
+#define SDRAM_MTP_CAS_RW_2 0x00001000\r
+#define SDRAM_MTP_CAS_RW_3 0x00001800\r
+#define SDRAM_MTP_CAS_RW_4 0x00002000\r
+#define SDRAM_MTP_CAS_RW_5 0x00002800\r
+#define SDRAM_MTP_CAS_RW_25 0x00003000\r
+\r
+#define SDRAM_MRS_LTMODE_MASK 0x00000070\r
+#define SDRAM_MRS_LTMODE_20 0x00000020\r
+#define SDRAM_MRS_LTMODE_25 0x00000060\r
+#define SDRAM_MRS_BT 0x00000008\r
+#define SDRAM_MRS_BL4 0x00000002\r
+\r
+#define SDRAM_MMCR_REGISTERED_MASK 0x14400000\r
+\r
+#define SDRAM_MSCR_SCRUBMODOFF 0x00000000\r
+#define SDRAM_MSCR_SCRUBMODBACKG 0x40000000\r
+#define SDRAM_MSCR_SCRUBMODIMMED 0x80000000\r
+#define SDRAM_MSCR_SCRUBMODIMMEDFILL 0xC0000000\r
+#define SDRAM_MSCR_SI_MASK 0x00FF0000\r
+\r
+#define SDRAM_MCCR_ECC_EN 0x80000000\r
+#define SDRAM_MCCR_ECC_APP_DIS 0x40000000\r
+#define SDRAM_MCCR_EI_EN_H 0x20000000\r
+#define SDRAM_MCCR_EI_EN_L 0x10000000\r
+#define SDRAM_MCCR_ECC_UE_MASK_H 0x08000000\r
+#define SDRAM_MCCR_ECC_CE_MASK_H 0x04000000\r
+#define SDRAM_MCCR_ECC_UE_MASK_L 0x02000000\r
+#define SDRAM_MCCR_ECC_CE_MASK_L 0x01000000\r
+#define SDRAM_MCCR_EI_PAT_H 0x0000FF00\r
+#define SDRAM_MCCR_EI_PAT_L 0x000000FF\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Power Management\r
++----------------------------------------------------------------------------*/\r
+#define NB_CLOCK_CTL 0xF8000F00UL\r
+#define HT_LOGIC_STOP_EN 0x00000010\r
+#define HT_CLK_EN 0x00000008\r
+#define NB_PLL2 0xF8000F60UL\r
+#define NB_PLL2_BYTE4 0xF8\r
+#define NB_PLL2_BYTE5 0x00\r
+#define NB_PLL2_BYTE6 0x0F\r
+#define NB_PLL2_BYTE7 0x60\r
+#define NB_PLL2_MASK 0xFFFFFFFF\r
+#define PLL2_FORCEPLLLOAD 0x40000000\r
+#define PLL2_VALUES_MASK 0x0F01F3FF\r
+#define PLL2_266 0x021082B8\r
+#define PLL2_300 0x021092B8\r
+#define PLL2_333 0x0210A2B8\r
+#define PLL2_FEEDBACK_MASK 0x0001F000\r
+#define PLL2_FEEDBACK_SPEED_266 0x00008000\r
+#define PLL2_FEEDBACK_SPEED_300 0x00009000\r
+#define PLL2_FEEDBACK_SPEED_333 0x0000A000\r
+#define PLL2_FEEDBACK_SPEED_366 0x0000B000\r
+#define PLL2_FEEDBACK_SPEED_400 0x0000C000\r
+#define PLL2_FEEDBACK_SPEED_433 0x0000D000\r
+#define PLL2_FEEDBACK_SPEED_466 0x0000E000\r
+#define PLL2_FEEDBACK_SPEED_500 0x0000F000\r
+#define NB_PLL4 0xF8000F80UL\r
+#define PLL4_FORCEPLLLOAD 0x40000000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| CPC925 Control\r
++----------------------------------------------------------------------------*/\r
+#define NB_REVISION 0xF8000000UL\r
+#define CPC925_DD1_1 0x00000035\r
+#define NB_WHOAMI 0xF8000050UL\r
+#define NB_SEMAPHORE 0xF8000060UL\r
+#define NB_HW_INIT_STATE 0xF8000070UL\r
+#define NB_HW_INIT_STATE_ASM 0xF8000070\r
+\r
+/*----------------------------------------------------------------------------+\r
+| DART\r
++----------------------------------------------------------------------------*/\r
+#define NB_DART_BASE 0xF8033000UL\r
+#define NB_DART_SIZE 0x00007000UL\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ##### # # ###### ####### ###### ### #######\r
+| # # # # # # # # # # # #\r
+| # # # # # # # # # # #\r
+| ##### # # ###### ##### ###### # # #\r
+| # # # # # # # # # #\r
+| # # # # # # # # # # #\r
+| ##### ##### # ####### # # ####### ### #######\r
++----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Configuration registers.\r
++----------------------------------------------------------------------------*/\r
+#define SUPER_IO_INDEX_OFF 0x2E\r
+#define SUPER_IO_DATA_OFF 0x2F\r
+\r
+#define SUPER_SST_IO_INDEX_OFF 0x2E\r
+#define SUPER_SST_IO_DATA_OFF 0x2F\r
+\r
+#define SUPER_IO_DEVICE_SEL 0x07\r
+\r
+#define SUPER_IO_DEVICE_S1 3\r
+#define SUPER_IO_DEVICE_S2 2\r
+#define SUPER_IO_DEVICE_XBUS 15\r
+#define SUPER_IO_DEVICE_RTC 16\r
+\r
+#define SUPER_IO_ADDR_XBUS 0x800\r
+#define SUPER_IO_ADDR_RTC 0x900\r
+#define SUPER_IO_ADDR_NVRAM 0x902\r
+\r
+#define SUPER_IO_DEVICE_CTRL 0x30\r
+#define SUPER_IO_BASE_DEV_MSB 0x60\r
+#define SUPER_IO_BASE_DEV_LSB 0x61\r
+#define SUPER_IO_EXT_DEV_MSB 0x62\r
+#define SUPER_IO_EXT_DEV_LSB 0x63\r
+#define SUPER_IO_INT_NUM 0x70\r
+#define SUPER_IO_INT_TYPE 0x71\r
+\r
+#define SUPER_IO_SERIAL_CONFIG 0xF0\r
+\r
+#define SUPER_IO_XBUS_CONFIG 0xF8\r
+#define SUPER_IO_BIOS_SIZE_16M 0x06\r
+#define SUPER_IO_BIOS_SIZE_1M 0x02\r
+\r
+#define SUPER_IO_XBUS_HOST_ACCESS (SUPER_IO_ADDR_XBUS+ 0x13)\r
+\r
+#define SUPER_IO_RTC_DATE_ALARM_OFF 0xF1\r
+#define SUPER_IO_RTC_MONTH_ALARM_OFF 0xF2\r
+#define SUPER_IO_RTC_CENTURY_ALARM_OFF 0xF3\r
+\r
+#define SUPER_IO_RTC_DATE_ALARM_LOC 0x0D\r
+#define SUPER_IO_RTC_MONTH_ALARM_LOC 0x0E\r
+#define SUPER_IO_RTC_CENTURY_ALARM_LOC 0x0F\r
+\r
+#define SUPER_IO_DEVICE_ENABLE 0x01\r
+\r
+#define SUPER_IO_SST_START_CONFIG 0x55\r
+#define SUPER_IO_SST_STOP_CONFIG 0xAA\r
+\r
+#define SUPER_IO_SST_ID_INDEX 0x20\r
+#define SUPER_IO_SST_ID_VALUE 0x51\r
+\r
+#define SUPER_IO_SST_DEVICE_INDEX 0x07\r
+#define SUPER_IO_SST_DEVICE_S1 0x04\r
+#define SUPER_IO_SST_DEVICE_S2 0x05\r
+#define SUPER_IO_SST_DEVICE_RUNTIME 0x0A\r
+\r
+#define SUPER_IO_INT_SELECT 0x70\r
+#define SUPER_IO_INT_SERIAL_1 0x04\r
+#define SUPER_IO_INT_SERIAL_2 0x03\r
+\r
+#define SUPER_IO_SST_RUNTIME_REGS 0x100\r
+\r
+#define SUPER_IO_BASE_CLOCKL32 0xF0\r
+\r
+#define SUPER_IO_BASE_CLOCKL32_ALL_OFF 0x03\r
+\r
+#define SUPER_IO_SST_GPIO_52 0x41\r
+#define SUPER_IO_SST_GPIO_53 0x42\r
+\r
+#define SUPER_IO_SST_GPIO_60 0x47\r
+#define SUPER_IO_SST_GPIO_61 0x48\r
+\r
+#define SUPER_IO_SST_GPIO_LED1 0x5D\r
+#define SUPER_IO_SST_GPIO_LED2 0x5E\r
+\r
+#define SEPER_IO_SST_RX 0x05\r
+#define SEPER_IO_SST_TX 0x04\r
+\r
+#define SEPER_IO_SST_LED1 0x06\r
+#define SEPER_IO_SST_LED2 0x06\r
+\r
+#define SEPER_IO_SST_LED_ONE_HZ 0x01\r
+#define SEPER_IO_SST_LED_HALF_HZ 0x02\r
+\r
+/*----------------------------------------------------------------------------+\r
+| # # # ###### ##### # ##### #\r
+| # # ## ## # # # # ## # # ##\r
+| # # # # # # # # # # # # # # #\r
+| # # # # # # # ##### # ##### #\r
+| ####### # # # # # # # # #\r
+| # # # # # # # # # # # #\r
+| # # # # ###### ##### ##### ##### #####\r
++----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PCI register information.\r
++----------------------------------------------------------------------------*/\r
+#define HTT_BRIDGE_ID ((unsigned int)0x7450)\r
+#define HTT_IOAPIC_ID ((unsigned int)0x7451)\r
+\r
+#define HTT_INDEX_OFF 0xB8\r
+#define HTT_DATA_OFF 0xBC\r
+#define HTT_IOAPIC_CTRL 0x44\r
+#define HTT_PREF_CONFIG_REG 0x4C\r
+#define HTT_LINK_CFG_A 0xC4\r
+#define HTT_LINK_CFG_B 0xC8\r
+#define HTT_LINK_FREQ_CAP_A 0xCC\r
+#define HTT_SEC_STATUS_REG 0xA0\r
+#define HTT_LINK_FREQ_CAP_B 0xD0\r
+\r
+/*----------------------------------------------------------------------------+\r
+| # # # ###### ##### # # #\r
+| # # ## ## # # # # ## ## ##\r
+| # # # # # # # # # # # # # # # #\r
+| # # # # # # # ##### # # #\r
+| ####### # # # # # # # # #\r
+| # # # # # # # # # # #\r
+| # # # # ###### ##### ##### ##### #####\r
++----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PCI register information.\r
++----------------------------------------------------------------------------*/\r
+#define AMD_VENDOR_ID ((unsigned int)0x1022)\r
+#define SB_LPCB_DEV_ID ((unsigned int)0x7468)\r
+#define SB_SYSM_DEV_ID ((unsigned int)0x746B)\r
+#define SB_PCIB_DEV_ID ((unsigned int)0x7460)\r
+#define SB_USB_DEV_ID ((unsigned int)0x7464)\r
+#define SB_EHC_DEV_ID ((unsigned int)0x7463)\r
+#define SB_ENET_DEV_ID ((unsigned int)0x7462)\r
+#define SB_IDE_DEV_ID ((unsigned int)0x7469)\r
+#define SB_SMB_DEV_ID ((unsigned int)0x746A)\r
+#define SB_AC97AUDIO_DEV_ID ((unsigned int)0x746D)\r
+#define SB_AC97MODEM_DEV_ID ((unsigned int)0x746E)\r
+\r
+#define SB_R_IO_CTRL1 0x40\r
+#define SB_R_LEG_CTRL 0x42\r
+#define SB_R_ROM_DECODE 0x43\r
+#define SB_R_MISC_CTRL 0x47\r
+#define SB_R_FUNC_ENABLE 0x48\r
+#define SB_R_IOAPIC_C0 0x4A\r
+#define SB_R_IOAPIC_C1 0x4B\r
+#define SB_R_SCICONFIG 0x42\r
+#define SB_R_PNP_IRQ_SEL 0x44\r
+#define SB_R_SERIRQ_CONNF 0x4A\r
+#define SB_R_PCI_PREF_C0 0x50\r
+#define SB_R_PCI_PREF_C1 0x54\r
+#define SB_R_PCI_IRQ_ROUTE 0x56\r
+#define SB_R_NVCTRL 0x74\r
+\r
+#define SB_LPC_ROM_W 0x01\r
+#define SB_LPC_ROM_SIZE 0xC0\r
+#define SB_PCI_PR_C0 0x00000000\r
+#define SB_PCI_PR_C1 0x0000718D\r
+#define SB_NVRAM_EN 0xDE01\r
+\r
+#define SB_SYSM_CC_WRITE 0x60\r
+\r
+#define SB_NVRAM_ADDR (NB_HT_IO_BASE_CPU+ 0xDE00)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| IDE controller\r
++----------------------------------------------------------------------------*/\r
+#define SB_IDE_PRI_BASE (NB_HT_IO_BASE_CPU+ 0x1F0)\r
+#define SB_IDE_SEC_BASE (NB_HT_IO_BASE_CPU+ 0x170)\r
+#define SB_IDE_DATA (NB_HT_IO_BASE_CPU+ 0x1F0)\r
+#define SB_IDE_CNT (NB_HT_IO_BASE_CPU+ 0x1F2)\r
+#define SB_IDE_LBAL (NB_HT_IO_BASE_CPU+ 0x1F3)\r
+#define SB_IDE_LBAM (NB_HT_IO_BASE_CPU+ 0x1F4)\r
+#define SB_IDE_LBAH (NB_HT_IO_BASE_CPU+ 0x1F5)\r
+#define SB_IDE_DEV (NB_HT_IO_BASE_CPU+ 0x1F6)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Write.\r
++----------------------------------------------------------------------------*/\r
+#define SB_IDE_CMD (NB_HT_IO_BASE_CPU+ 0x1F7)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Read.\r
++----------------------------------------------------------------------------*/\r
+#define SB_IDE_STAT (NB_HT_IO_BASE_CPU+ 0x1F7)\r
+#define SB_IDE_CTRL (NB_HT_IO_BASE_CPU+ 0x3F6)\r
+\r
+#define IDE_STAT_BSY 0x80\r
+#define IDE_DEV_LBA 0x40\r
+#define IDE_DEV_HEAD_MASK 0x0F\r
+#define IDE_CMD_READ_RETRIES 0x20\r
+#define IDE_CTRL_NIEN 0x02\r
+\r
+#define IDE_RANGE_LEGACY 0xCC00\r
+\r
+#define SB_EIDEC_CMD 0x04\r
+#define SB_EIDEC_PROG 0x08\r
+#define SB_EIDEC_INT 0x3C\r
+#define SB_EIDEC_CONFIG 0x40\r
+\r
+#define EIDEC_CMD_BMEN 0x00000004\r
+#define EIDEC_CMD_IOEN 0x00000001\r
+#define EIDEC_PROG_PROGIF2 0x00000400\r
+#define EIDEC_PROG_PROGIF0 0x00000100\r
+#define EIDEC_CONFIG_PRIEN 0x00000002\r
+#define EIDEC_CONFIG_SECEN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------+\r
+| LPC bus.\r
++----------------------------------------------------------------------------*/\r
+#define SB_LPC_FUNCENAB 0x48\r
+#define LPC_FUNCENAB_IDE 0x0002\r
+\r
+#define SB_RTC_LEG_ADDR 0x70\r
+#define SB_RTC_LEG_DATA 0x71\r
+\r
+/*----------------------------------------------------------------------------+\r
+| RTC.\r
++----------------------------------------------------------------------------*/\r
+#define SB_RTC_ADDR_PORT70 (NB_HT_IO_BASE_CPU+ 0x70)\r
+#define SB_RTC_DATA_PORT71 (NB_HT_IO_BASE_CPU+ 0x71)\r
+#define SB_RTC_ADDR_PORT72 (NB_HT_IO_BASE_CPU+ 0x72)\r
+#define SB_RTC_DATA_PORT73 (NB_HT_IO_BASE_CPU+ 0x73)\r
+\r
+\r
+/************ as_archppc.h ****************/\r
+/*----------------------------------------------------------------------------+\r
+| Schould be included only in assemble files.\r
++----------------------------------------------------------------------------*/\r
+//#ifdef __ASM__\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Register definitions and assembler specific definitions.\r
++----------------------------------------------------------------------------*/\r
+#ifdef __GNUC__\r
+#define new_section(name,attr) .section "name", "attr"\r
+#define r0 0\r
+#define r1 1\r
+#define r2 2\r
+#define r3 3\r
+#define r4 4\r
+#define r5 5\r
+#define r6 6\r
+#define r7 7\r
+#define r8 8\r
+#define r9 9\r
+#define r10 10\r
+#define r11 11\r
+#define r12 12\r
+#define r13 13\r
+#define r14 14\r
+#define r15 15\r
+#define r16 16\r
+#define r17 17\r
+#define r18 18\r
+#define r19 19\r
+#define r20 20\r
+#define r21 21\r
+#define r22 22\r
+#define r23 23\r
+#define r24 24\r
+#define r25 25\r
+#define r26 26\r
+#define r27 27\r
+#define r28 28\r
+#define r29 29\r
+#define r30 30\r
+#define r31 31\r
+#define fr0 0\r
+#define fr1 1\r
+#define fr2 2\r
+#define fr3 3\r
+#define fr4 4\r
+#define fr5 5\r
+#define fr6 6\r
+#define fr7 7\r
+#define fr8 8\r
+#define fr9 9\r
+#define fr10 10\r
+#define fr11 11\r
+#define fr12 12\r
+#define fr13 13\r
+#define fr14 14\r
+#define fr15 15\r
+#define fr16 16\r
+#define fr17 17\r
+#define fr18 18\r
+#define fr19 19\r
+#define fr20 20\r
+#define fr21 21\r
+#define fr22 22\r
+#define fr23 23\r
+#define fr24 24\r
+#define fr25 25\r
+#define fr26 26\r
+#define fr27 27\r
+#define fr28 28\r
+#define fr29 29\r
+#define fr30 30\r
+#define fr31 31\r
+#endif\r
+#ifdef __MW__\r
+#define new_section(name,attr) .section name, attr\r
+#define r0 %r0\r
+#define r1 %r1\r
+#define r2 %r2\r
+#define r3 %r3\r
+#define r4 %r4\r
+#define r5 %r5\r
+#define r6 %r6\r
+#define r7 %r7\r
+#define r8 %r8\r
+#define r9 %r9\r
+#define r10 %r10\r
+#define r11 %r11\r
+#define r12 %r12\r
+#define r13 %r13\r
+#define r14 %r14\r
+#define r15 %r15\r
+#define r16 %r16\r
+#define r17 %r17\r
+#define r18 %r18\r
+#define r19 %r19\r
+#define r20 %r20\r
+#define r21 %r21\r
+#define r22 %r22\r
+#define r23 %r23\r
+#define r24 %r24\r
+#define r25 %r25\r
+#define r26 %r26\r
+#define r27 %r27\r
+#define r28 %r28\r
+#define r29 %r29\r
+#define r30 %r30\r
+#define r31 %r31\r
+#define fr0 %f0\r
+#define fr1 %f1\r
+#define fr2 %f2\r
+#define fr3 %f3\r
+#define fr4 %f4\r
+#define fr5 %f5\r
+#define fr6 %f6\r
+#define fr7 %f7\r
+#define fr8 %f8\r
+#define fr9 %f9\r
+#define fr10 %f10\r
+#define fr11 %f11\r
+#define fr12 %f12\r
+#define fr13 %f13\r
+#define fr14 %f14\r
+#define fr15 %f15\r
+#define fr16 %f16\r
+#define fr17 %f17\r
+#define fr18 %f18\r
+#define fr19 %f19\r
+#define fr20 %f20\r
+#define fr21 %f21\r
+#define fr22 %f22\r
+#define fr23 %f23\r
+#define fr24 %f24\r
+#define fr25 %f25\r
+#define fr26 %f26\r
+#define fr27 %f27\r
+#define fr28 %f28\r
+#define fr29 %f29\r
+#define fr30 %f30\r
+#define fr31 %f31\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Condition register defines.\r
++----------------------------------------------------------------------------*/\r
+#define cr0 0\r
+#define cr1 1\r
+#define cr2 2\r
+#define cr3 3\r
+#define cr4 4\r
+#define cr5 5\r
+#define cr6 6\r
+#define cr7 7\r
+#define cr0_0 0\r
+#define cr0_1 1\r
+#define cr0_2 2\r
+#define cr0_3 3\r
+#define cr1_0 4\r
+#define cr1_1 5\r
+#define cr1_2 6\r
+#define cr1_3 7\r
+#define cr2_0 8\r
+#define cr2_1 9\r
+#define cr2_2 10\r
+#define cr2_3 11\r
+#define cr3_0 12\r
+#define cr3_1 13\r
+#define cr3_2 14\r
+#define cr3_3 15\r
+#define cr4_0 16\r
+#define cr4_1 17\r
+#define cr4_2 18\r
+#define cr4_3 19\r
+#define cr5_0 20\r
+#define cr5_1 21\r
+#define cr5_2 22\r
+#define cr5_3 23\r
+#define cr6_0 24\r
+#define cr6_1 25\r
+#define cr6_2 26\r
+#define cr6_3 27\r
+#define cr6_sign 24\r
+#define cr6_inf 25\r
+#define cr6_zero 26\r
+#define cr6_NaN 27\r
+#define cr7_0 28\r
+#define cr7_1 29\r
+#define cr7_2 30\r
+#define cr7_3 31\r
+#define cr7_sign 28\r
+#define cr7_inf 29\r
+#define cr7_zero 30\r
+#define cr7_NaN 31\r
+\r
+#define cr4_lt 16 \r
+#define cr4_eq 18 \r
+#define cr6_lt 24 \r
+#define cr7_lt 28 \r
+\r
+/*----------------------------------------------------------------------------+\r
+| Basic PowerPC 32/64 bit instruction definitions and 32/64 bit defines.\r
++----------------------------------------------------------------------------*/\r
+#ifdef __PPC64__\r
+#define LOAD(rd,disp,ds) ld rd,disp(ds)\r
+#define STORE(rs,disp,ra) std rs,disp(ra)\r
+#define CMPI(cr,ra,si) cmpdi cr,ra,si\r
+#define CMPL(cr,ra,rb) cmpld cr,ra,rb\r
+#define GETTIMEBASEL(ra) mftb ra\r
+#define TRACE_ENTRY_SIZE 16\r
+#define MULL(rt,ra,rb) mulld rt,ra,rb\r
+#define RFI rfid\r
+#else\r
+#define LOAD(rd,disp,ds) lwz rd,disp(ds)\r
+#define STORE(rs,disp,ra) stw rs,disp(ra)\r
+#define CMPI(cr,ra,si) cmpwi cr,ra,si\r
+#define CMPL(cr,ra,rb) cmplw cr,ra,rb\r
+#define GETTIMEBASEL(ra) mfspr ra,tblr\r
+#define TRACE_ENTRY_SIZE 12\r
+#define MULL(rt,ra,rb) mullw rt,ra,rb\r
+#define RFI rfi\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Macro for loading a 64 bit value into a register without using TOC and a \r
+| TOC entry that has to be used when loading symbol address using TOC.\r
++----------------------------------------------------------------------------*/\r
+#ifdef __PPC64__\r
+#define LOAD_64BIT_VAL(ra,value) addis ra,r0,value@highest; \\r
+ ori ra,ra,value@higher; \\r
+ sldi ra,ra,32; \\r
+ oris ra,ra,value@h; \\r
+ ori ra,ra,value@l\r
+#define TOC_ENTRY(name,symbol) .section ".toc","aw"; \\r
+ name: .tc symbol[TC],symbol\r
+#define GETSYMADDR(ra,sym,name) ld ra,name@toc(r2)\r
+#else\r
+#define TOC_ENTRY(name,symbol) \r
+#define GETSYMADDR(ra,sym,name) addis ra,r0,sym@h;ori ra,ra,sym@l\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Stack frame offsets. FP register area starts after back chain and LR save. \r
+| Space to save non-volatile registers 16-31 starts after FP register area.\r
+| Stack frame needs to be a multiple of 8 bytes for EABI. This is only used\r
+| in 32-bit mode for floating point emulation functions.\r
++----------------------------------------------------------------------------*/\r
+#ifndef __PPC64__\r
+#define NUMB_SAVEREGS 16\r
+#define STACKSIZE ((NUMB_SAVEREGS* 4)+ 8)\r
+#define SAVER_BASE 8\r
+#define SAVEREG(rn) stw r##rn,(SAVER_BASE+ (rn- 16)* 4)(r1)\r
+#define RESTREG(rn) lwz r##rn,(SAVER_BASE+ (rn- 16)* 4)(r1)\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Macros for function prolog/epilog, function call.\r
++----------------------------------------------------------------------------*/\r
+#ifdef __PPC64__\r
+#define function_prolog(fn) .section ".text"; \\r
+ .align 2; \\r
+ .globl fn; \\r
+ .section ".opd","aw"; \\r
+ .align 3; \\r
+ fn:; \\r
+ .quad .fn,.TOC.@tocbase,0; \\r
+ .previous; \\r
+ .size fn,24; \\r
+ .globl .fn; \\r
+ .fn:\r
+\r
+#define function_epilog(fn) .long 0; \\r
+ .byte 0,12,0,0,0,0,0,0; \\r
+ .type .fn,@function; \\r
+ .size .fn,.-.fn\r
+\r
+#define data_global_prolog(dn) .section ".toc","aw"; \\r
+ .tc dn[TC],dn; \\r
+ .section ".data"; \\r
+ .align 3; \\r
+ .globl dn; \\r
+ dn:\r
+\r
+#define data_global_epilog(dn) .type dn,@object; \\r
+ .size dn,.-dn\r
+\r
+#define data_prolog(dn) .section ".toc","aw"; \\r
+ .tc dn[TC],dn; \\r
+ .section ".data"; \\r
+ .align 3; \\r
+ dn:\r
+\r
+#define data_epilog(data_name) .type dn,@object; \\r
+ .size dn,.-dn\r
+\r
+#define function_call(func_name) bl .func_name \r
+\r
+#else\r
+#define function_nos_prolog(func_name) .align 2; \\r
+ .globl func_name; \\r
+ func_name:\r
+\r
+#define function_prolog(func_name) .text; \\r
+ .align 2; \\r
+ .globl func_name; \\r
+ func_name:\r
+\r
+#define function_epilog(func_name) .type func_name,@function; \\r
+ .size func_name,.-func_name\r
+\r
+#define data_global_prolog(data_name) .data; \\r
+ .align 2; \\r
+ .globl data_name; \\r
+ data_name:\r
+\r
+#define data_global_epilog(data_name) .type data_name,@object; \\r
+ .size data_name,.-data_name\r
+\r
+#define data_prolog(data_name) .data; \\r
+ .align 2; \\r
+ data_name:\r
+\r
+#define data_epilog(data_name) .type data_name,@object; \\r
+ .size data_name,.-data_name\r
+\r
+#define function_call(func_name) bl func_name \r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| EABI and 64-bit API stack frame definition.\r
++----------------------------------------------------------------------------*/\r
+#ifdef __PPC64__\r
+#define stack_frame_min 112\r
+#define stack_frame_bc 0\r
+#define stack_frame_lr 16\r
+#define stack_neg_off 288\r
+#else\r
+#define stack_frame_min 8\r
+#define stack_frame_bc 0\r
+#define stack_frame_lr 4\r
+#define stack_neg_off 0\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Size of the context register.\r
++----------------------------------------------------------------------------*/\r
+#ifdef __PPC64__\r
+#define stack_reg_image_size 328\r
+#define stack_reg_img_s_new 328\r
+#define stack_reg_s_spr 72\r
+#else\r
+#define stack_reg_image_size 160\r
+#define stack_reg_img_s_new 168\r
+#define stack_reg_s_spr 40\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| "dlmzb" instruction is not supported by the GNU assembler. On 7XX \r
+| processorsdlmzb instruction does not exist. In that case the instruction\r
+| is emulated. The emulated unstruction does not set CR[CR0] SO (overflow).\r
++----------------------------------------------------------------------------*/\r
+#if ! defined __PPC7XX__ && ! defined __PPC64__\r
+#define DLMZBDOT(ra,rs,rb,lab,rt) .long 0x7c00009d|\\r
+ (rs<<21)|(ra<<16)|(rb<<11)\r
+\r
+#define DLMZBNDOT(ra,rs,rb,lab,rt) .long 0x7c00009c|\\r
+ (rs<<21)|(ra<<16)|(rb<<11)\r
+#else\r
+#define DLMZBDOT(ra,rs,rb,lab,rt) addi ra,r0,0x0001;\\r
+ rlwinm. rt,rs,0,0,7;\\r
+ beq lab##end1;\\r
+ addi ra,r0,0x0002;\\r
+ rlwinm. rt,rs,0,8,15;\\r
+ beq lab##end1;\\r
+ addi ra,r0,0x0003;\\r
+ rlwinm. rt,rs,0,16,23;\\r
+ beq lab##end1;\\r
+ addi ra,r0,0x0004;\\r
+ rlwinm. rt,rs,0,24,31;\\r
+ beq lab##end1;\\r
+ addi ra,r0,0x0005;\\r
+ rlwinm. rt,rb,0,0,7;\\r
+ beq lab##end2;\\r
+ addi ra,r0,0x0006;\\r
+ rlwinm. rt,rb,0,8,15;\\r
+ beq lab##end2;\\r
+ addi ra,r0,0x0007;\\r
+ rlwinm. rt,rb,0,16,23;\\r
+ beq lab##end2;\\r
+ addi ra,r0,0x0008;\\r
+ rlwinm. rt,rb,0,24,31;\\r
+ beq lab##end2;\\r
+ addis rt,r0,0x2000;\\r
+ mtcrf 0x80,rt;\\r
+ b lab##fin;\\r
+ lab##end1:;\\r
+ addis rt,r0,0x4000;\\r
+ mtcrf 0x80,rt;\\r
+ b lab##fin;\\r
+ lab##end2:;\\r
+ addis rt,r0,0x8000;\\r
+ mtcrf 0x80,rt;\\r
+ lab##fin:;\\r
+ mfspr rt,xer_reg;\\r
+ rlwinm rt,rt,0,0,24;\\r
+ or rt,rt,ra;\\r
+ mtspr xer_reg,rt\r
+\r
+#define DLMZBNDOT(ra,rs,rb,lab,rt) addi ra,r0,0x0001;\\r
+ rlwinm. rt,rs,0,0,7;\\r
+ beq lab##end;\\r
+ addi ra,r0,0x0002;\\r
+ rlwinm. rt,rs,0,8,15;\\r
+ beq lab##end;\\r
+ addi ra,r0,0x0003;\\r
+ rlwinm. rt,rs,0,16,23;\\r
+ beq lab##end;\\r
+ addi ra,r0,0x0004;\\r
+ rlwinm. rt,rs,0,24,31;\\r
+ beq lab##end;\\r
+ addi ra,r0,0x0005;\\r
+ rlwinm. rt,rb,0,0,7;\\r
+ beq lab##end;\\r
+ addi ra,r0,0x0006;\\r
+ rlwinm. rt,rb,0,8,15;\\r
+ beq lab##end;\\r
+ addi ra,r0,0x0007;\\r
+ rlwinm. rt,rb,0,16,23;\\r
+ beq lab##end;\\r
+ addi ra,r0,0x0008;\\r
+ rlwinm. rt,rb,0,24,31;\\r
+ lab##end:;\\r
+ mfspr rt,xer_reg;\\r
+ rlwinm rt,rt,0,0,24;\\r
+ or rt,rt,ra;\\r
+ mtspr xer_reg,rt\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Following instructions are not available in Book E mode of the GNU assembler.\r
++----------------------------------------------------------------------------*/\r
+#ifdef __PPC64__\r
+#define TLBIEL(rb) .long 0x7C000000|\\r
+ (rb<<11)|(274<<1)\r
+#define HRFID() .long 0x4C000000|\\r
+ (274<<1)\r
+#else\r
+#define DCCCI(ra,rb) .long 0x7c000000|\\r
+ (ra<<16)|(rb<<11)|(454<<1)\r
+\r
+#define ICCCI(ra,rb) .long 0x7c000000|\\r
+ (ra<<16)|(rb<<11)|(966<<1)\r
+\r
+#define DCREAD(rt,ra,rb) .long 0x7c000000|\\r
+ (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)\r
+\r
+#define ICREAD(ra,rb) .long 0x7c000000|\\r
+ (ra<<16)|(rb<<11)|(998<<1)\r
+\r
+#define TLBSX(rt,ra,rb) .long 0x7c000000|\\r
+ (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)\r
+\r
+#define TLBWE(rs,ra,ws) .long 0x7c000000|\\r
+ (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)\r
+\r
+#define TLBRE(rt,ra,ws) .long 0x7c000000|\\r
+ (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)\r
+\r
+#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\\r
+ (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)\r
+\r
+#define MSYNC .long 0x7c000000|\\r
+ (598<<1)\r
+\r
+#define MBAR .long 0x7c000000|\\r
+ (854<<1)\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Special Purpose Registers. Xer, lr, ctr, srr0, srr1, sprg0, sprg1, sprg2,\r
+| sprg3, pvr, tbl (read), tlu (read) registers.\r
++----------------------------------------------------------------------------*/\r
+#define xer_reg 0x001\r
+#define lr_reg 0x008\r
+#define ctr 0x009\r
+#define srr0 0x01a\r
+#define srr1 0x01b\r
+#define sprg0 0x110\r
+#define sprg1 0x111\r
+#define sprg2 0x112\r
+#define sprg3 0x113\r
+#define pvr 0x11f\r
+#define tblr 0x10c\r
+#define tbur 0x10d\r
+\r
+//#endif //__ASM__\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Same as above for the C code.\r
++----------------------------------------------------------------------------*/\r
+#define SPR_SRR0 0x01a\r
+#define SPR_SRR1 0x01b\r
+#define SPR_SPRG0 0x110\r
+#define SPR_SPRG1 0x111\r
+#define SPR_SPRG2 0x112\r
+#define SPR_SPRG3 0x113\r
+#define SPR_PVR 0x11f\r
+#define SPR_TBLR 0x10c\r
+#define SPR_TBUR 0x10d\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1.\r
++----------------------------------------------------------------------------*/\r
+#define MSR_EE 0x00008000\r
+#define MSR_PR 0x00004000\r
+#define MSR_FP 0x00002000\r
+#define MSR_ME 0x00001000\r
+#define MSR_FE0 0x00000800\r
+#define MSR_FE1 0x00000100\r
+\r
+\r
+/************ as_archppc970.h ****************/\r
+/*----------------------------------------------------------------------------+\r
+| PVR value.\r
++----------------------------------------------------------------------------*/\r
+#define PVR_970_DD1 0x00391100\r
+#define PVR_970FX_DD2 0x003C0200\r
+#define PVR_970FX_DD2_1 0x003C0201\r
+#define PVR_970FX_DD3 0x003C0300\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64)\r
+| sprg0 (64), sprg1 (64), sprg2 (64), sprg3 (64), pvr (32) tblr (64), tbur (32)\r
+| registers are defined in as_archppc.h.\r
++----------------------------------------------------------------------------*/\r
+#define SPR_ACCR 0x001D /* 64-bit read/write $*/\r
+#define SPR_ASR 0x0118 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_DABR 0x03F5 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_DABRX 0x03F7 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_DAR 0x0013 /* 64-bit read/write */\r
+#define SPR_DEC 0x0016 /* 32-bit read/write */\r
+#define SPR_DSISR 0x0012 /* 32-bit read/write */\r
+#define SPR_HDEC 0x0136 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HID0 0x03F0 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HID1 0x03F1 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HID4 0x03F4 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HID5 0x03F6 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HIOR 0x0137 /* 64-bit read/write */\r
+#define SPR_HSPRG0 0x0130 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HSPRG1 0x0131 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HSRR0 0x013A /* 64-bit read/write, write hypervisor only */\r
+#define SPR_HSRR1 0x013B /* 64-bit read/write, write hypervisor only */\r
+#define SPR_IMC 0x030F /* 64-bit read/write */\r
+#define SPR_MMCR0 0x031B /* 64-bit read/write */\r
+#define SPR_MMCR1 0x031E /* 64-bit read/write */\r
+#define SPR_MMCRA 0x0312 /* 64-bit read/write */\r
+#define SPR_PIR 0x03FF /* 32-bit read */\r
+#define SPR_PMC1 0x0313 /* 32-bit read/write */\r
+#define SPR_PMC2 0x0314 /* 32-bit read/write */\r
+#define SPR_PMC3 0x0315 /* 32-bit read/write */\r
+#define SPR_PMC4 0x0316 /* 32-bit read/write */\r
+#define SPR_PMC5 0x0317 /* 32-bit read/write */\r
+#define SPR_PMC6 0x0318 /* 32-bit read/write */\r
+#define SPR_PMC7 0x0319 /* 32-bit read/write */\r
+#define SPR_PMC8 0x031A /* 32-bit read/write */\r
+#define SPR_SCOMC 0x0114 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_SCOMD 0x0115 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_SDAR 0x031D /* 64-bit read/write */\r
+#define SPR_SDR1 0x0019 /* 64-bit read/write, write hypervisor only */\r
+#define SPR_SIAR 0x031C /* 64-bit read/write */\r
+#define SPR_TBL_WRITE 0x011C /* 32-bit write */\r
+#define SPR_TBU_WRITE 0x011D /* 32-bit write */\r
+#define SPR_TRACE 0x03FE /* 64-bit read $*/\r
+#define SPR_TRIG0 0x03D0 /* 64-bit write */\r
+#define SPR_TRIG1 0x03D1 /* 64-bit write */\r
+#define SPR_TRIG2 0x03D2 /* 64-bit write */\r
+#define SPR_VRSAVE 0x0100 /* 64-bit read/write $*/\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Vector status and control register is accessed using the mfvscr and mtvscr\r
+| instructions.\r
++----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,\r
+| register bits are defined in as_archppc.h. This is a 64-bit register.\r
++----------------------------------------------------------------------------*/\r
+#define MSR_SF 0x8000000000000000 /* 64/32 bit mode indicator */\r
+#define MSR_HV 0x1000000000000000 /* hypervisor mode */\r
+#define MSR_VMX 0x0000000002000000 /* vmx unit available */\r
+#define MSR_POW 0x0000000000040000 /* power management enable */\r
+#define MSR_SE 0x0000000000000400 /* single step */\r
+#define MSR_BE 0x0000000000000200 /* branch trace */\r
+#define MSR_IS 0x0000000000000020 /* instruction address space */\r
+#define MSR_DS 0x0000000000000010 /* data address space */\r
+#define MSR_PM 0x0000000000000004 /* performance monitor */\r
+#define MSR_RI 0x0000000000000002 /* recoverable interrupt */\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HID0 bits.\r
++----------------------------------------------------------------------------*/\r
+#define HID0_ONEPPC 0x8000000000000000\r
+#define HID0_SINGLE 0x4000000000000000\r
+#define HID0_ISYNC_SC 0x2000000000000000\r
+#define HID0_SERIAL_G 0x1000000000000000\r
+#define HID0_DEEP_NAP 0x0100000000000000\r
+#define HID0_NAP 0x0040000000000000\r
+#define HID0_DPM 0x0010000000000000\r
+#define HID0_TR_GR 0x0004000000000000\r
+#define HID0_TR_DIS 0x0002000000000000\r
+#define HID0_NHR 0x0001000000000000\r
+#define HID0_INORDER 0x0000800000000000\r
+#define HID0_ENH_TR 0x0000400000000000\r
+#define HID0_TB_CTRL 0x0000200000000000\r
+#define HID0_EXT_TB_EN 0x0000100000000000\r
+#define HID0_CIABR_EN 0x0000020000000000\r
+#define HID0_HDEC_EN 0x0000010000000000\r
+#define HID0_EB_THERM 0x0000008000000000\r
+#define HID0_EN_ATTN 0x0000000100000000\r
+#define HID0_EN_MAC 0x0000000080000000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HID1 bits.\r
++----------------------------------------------------------------------------*/\r
+#define HID1_BHT_PM 0xE000000000000000\r
+#define HID1_BHT_STATIC 0x0000000000000000\r
+#define HID1_BHT_GLOBAL 0x4000000000000000\r
+#define HID1_BHT_LOCAL 0x8000000000000000\r
+#define HID1_BHT_GL_LO 0xC000000000000000\r
+#define HID1_BHT_GL_CO 0x6000000000000000\r
+#define HID1_BHT_FULL 0xE000000000000000\r
+#define HID1_EN_LS 0x1000000000000000\r
+#define HID1_EN_CC 0x0800000000000000\r
+#define HID1_EN_IC 0x0400000000000000\r
+#define HID1_PF_MASK 0x0180000000000000\r
+#define HID1_PF_NSA 0x0080000000000000\r
+#define HID1_PF_NSA_P 0x0100000000000000\r
+#define HID1_PF_DIS 0x0180000000000000\r
+#define HID1_EN_ICBI 0x0040000000000000\r
+#define HID1_EN_IF_CACH 0x0020000000000000\r
+#define HID1_EN_IC_REC 0x0010000000000000\r
+#define HID1_EN_ID_REC 0x0008000000000000\r
+#define HID1_EN_ER_REC 0x0004000000000000\r
+#define HID1_IC_PE 0x0002000000000000\r
+#define HID1_ICD0_PE 0x0001000000000000\r
+#define HID1_ICD1_PE 0x0000800000000000\r
+#define HID1_IER_PE 0x0000400000000000\r
+#define HID1_EN_SP_ITW 0x0000200000000000\r
+#define HID1_S_CHICKEN 0x0000100000000000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HID4 bits.\r
++----------------------------------------------------------------------------*/\r
+#define HID4_LPES0 0x8000000000000000\r
+#define HID4_RMLR12_MSK 0x6000000000000000\r
+#define HID4_LPID25_MSK 0x1E00000000000000\r
+#define HID4_RMOR_MASK 0x01FFFE0000000000\r
+#define HID4_RM_CI 0x0000010000000000\r
+#define HID4_FORCE_AI 0x0000008000000000\r
+#define HID4_DIS_PERF 0x0000004000000000\r
+#define HID4_RES_PERF 0x0000002000000000\r
+#define HID4_EN_SP_DTW 0x0000001000000000\r
+#define HID4_L1DC_FLSH 0x0000000800000000\r
+#define HID4_D_DERAT_P1 0x0000000400000000\r
+#define HID4_D_DERAT_P2 0x0000000200000000\r
+#define HID4_D_DERAT_G 0x0000000100000000\r
+#define HID4_D_DERAT_S1 0x0000000040000000\r
+#define HID4_D_DERAT_S2 0x0000000080000000\r
+#define HID4_DC_TP_S1 0x0000000020000000\r
+#define HID4_DC_TP_S2 0x0000000010000000\r
+#define HID4_DC_TP_GEN 0x0000000008000000\r
+#define HID4_DC_SET1 0x0000000004000000\r
+#define HID4_DC_SET2 0x0000000002000000\r
+#define HID4_DC_DP_S1 0x0000000001000000\r
+#define HID4_DC_DP_S2 0x0000000000800000\r
+#define HID4_DC_DP_GEN 0x0000000000400000\r
+#define HID4_R_TAG1P_CH 0x0000000000200000\r
+#define HID4_R_TAG2P_CH 0x0000000000100000\r
+#define HID4_TLB_PC1 0x0000000000080000\r
+#define HID4_TLB_PC2 0x0000000000040000\r
+#define HID4_TLB_PC3 0x0000000000020000\r
+#define HID4_TLB_PC4 0x0000000000010000\r
+#define HID4_TLB_P_GEN 0x0000000000008000\r
+#define HID4_TLB_SET1 0x0000000000003800\r
+#define HID4_TLB_SET2 0x0000000000005800\r
+#define HID4_TLB_SET3 0x0000000000006800\r
+#define HID4_TLB_SET4 0x0000000000007000\r
+#define HID4_DIS_SLBPC 0x0000000000000400\r
+#define HID4_DIS_SLBPG 0x0000000000000200\r
+#define HID4_MCK_INJ 0x0000000000000100\r
+#define HID4_DIS_STFWD 0x0000000000000080\r
+#define HID4_LPES1 0x0000000000000040\r
+#define HID4_RMLR0_MSK 0x0000000000000020\r
+#define HID4_DIS_SPLARX 0x0000000000000008\r
+#define HID4_LP_PG_EN 0x0000000000000004\r
+#define HID4_LPID01_MSK 0x0000000000000003\r
+\r
+/*----------------------------------------------------------------------------+\r
+| HID5 bits.\r
++----------------------------------------------------------------------------*/\r
+#define HID5_HRMOR_MASK 0x00000000FFFF0000\r
+#define HID5_DC_MCK 0x0000000000002000\r
+#define HID5_DIS_PWRSAV 0x0000000000001000\r
+#define HID5_FORCE_G 0x0000000000000800\r
+#define HID5_DC_REPL 0x0000000000000400\r
+#define HID5_HWR_STMS 0x0000000000000200\r
+#define HID5_DST_NOOP 0x0000000000000100\r
+#define HID5_DCBZ_SIZE 0x0000000000000080\r
+#define HID5_DCBZ32_ILL 0x0000000000000040\r
+#define HID5_TLB_MAP 0x0000000000000020\r
+#define HID5_IMQ_PORT 0x0000000000000010\r
+#define HID5_LMP_SIZE0 0x0000000000000008\r
+#define HID5_DPFLOOD 0x0000000000000004\r
+#define HID5_TCH_NOP 0x0000000000000002\r
+#define HID5_LMP_SIZE1 0x0000000000000001\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Specific SRR1 bit definitions for Machine Check.\r
++----------------------------------------------------------------------------*/\r
+#define SRR1_IFU_UNREC 0x0000000000200000\r
+#define SRR1_LOAD_STORE 0x0000000000100000\r
+#define SRR1_SLB_PARITY 0x0000000000040000\r
+#define SRR1_TLB_PARITY 0x0000000000080000\r
+#define SRR1_ITLB_RELOA 0x00000000000C0000\r
+#define SRR1_RI 0x0000000000000002\r
+\r
+#endif /* _ppc970_h_ */\r
--- /dev/null
+#ifndef _ppc970lib_h_\r
+#define _ppc970lib_h_\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Time base structure.\r
++----------------------------------------------------------------------------*/\r
+typedef struct tb {\r
+ unsigned long tb_all; \r
+} tb_t;\r
+\r
+/*----------------------------------------------------------------------------+\r
+| 970FX specific ppc prototypes.\r
++----------------------------------------------------------------------------*/\r
+void ppcMfvscr(\r
+ void );\r
+\r
+void ppcMtvscr(\r
+ void );\r
+\r
+int ppcMfvr(\r
+ unsigned int reg_num,\r
+ unsigned long *data_msb,\r
+ unsigned long *data_lsb );\r
+\r
+int ppcMtvr(\r
+ unsigned int reg_num,\r
+ unsigned long data_msb,\r
+ unsigned long data_lsb );\r
+\r
+void ppcLvxl(\r
+ unsigned int reg_num,\r
+ void *addr );\r
+\r
+void ppcStvx(\r
+ unsigned int reg_num,\r
+ void *addr );\r
+\r
+unsigned long ppcMflr(\r
+ void );\r
+\r
+unsigned char inbyte(\r
+ unsigned long addr );\r
+\r
+void outbyte(\r
+ unsigned long addr,\r
+ unsigned int data );\r
+\r
+unsigned short inhalf(\r
+ unsigned long addr );\r
+\r
+void outhalf(\r
+ unsigned long addr,\r
+ unsigned int data );\r
+\r
+unsigned short inhalf_brx(\r
+ unsigned long addr );\r
+\r
+void outhalf_brx(\r
+ unsigned long addr,\r
+ unsigned int data );\r
+\r
+unsigned long inword(\r
+ unsigned long addr );\r
+\r
+void outword(\r
+ unsigned long addr,\r
+ unsigned long data );\r
+\r
+unsigned int inint(\r
+ unsigned long addr );\r
+\r
+void outint(\r
+ unsigned long addr,\r
+ unsigned int data );\r
+\r
+unsigned int inint_brx(\r
+ unsigned long addr );\r
+\r
+void outint_brx(\r
+ unsigned long addr,\r
+ unsigned int data );\r
+\r
+void ppcDflush(\r
+ void );\r
+\r
+void ppcDcbz_area(\r
+ unsigned long addr,\r
+ unsigned long len );\r
+\r
+unsigned long ppcTlbsync(\r
+ void );\r
+\r
+unsigned long ppcTlbie(\r
+ unsigned long vaddr,\r
+ int large_page );\r
+\r
+void ppcTlbiel(\r
+ unsigned long vaddr );\r
+\r
+void ppcSlbie(\r
+ unsigned long rb );\r
+\r
+void ppcSlbia(\r
+ void );\r
+\r
+void ppcSlbmte(\r
+ unsigned long rs,\r
+ unsigned long rb );\r
+\r
+unsigned long ppcSlbmfev(\r
+ int index );\r
+\r
+unsigned long ppcSlbmfee(\r
+ int index );\r
+\r
+void ppcAbend(\r
+ void );\r
+\r
+unsigned long ppcAndMsr(\r
+ unsigned long value );\r
+\r
+unsigned int ppcCntlzw(\r
+ unsigned int value );\r
+\r
+unsigned int ppcCntlzd(\r
+ unsigned long value );\r
+\r
+void ppcDcbf(\r
+ void *addr );\r
+\r
+void ppcDcbst(\r
+ void *addr );\r
+\r
+void ppcDcbz(\r
+ void *addr );\r
+\r
+void ppcHalt(\r
+ void );\r
+\r
+void ppcIcbi(\r
+ void *addr );\r
+\r
+void ppcIsync(\r
+ void );\r
+\r
+unsigned long ppcMfgpr1(\r
+ void );\r
+\r
+unsigned long ppcMfgpr2(\r
+ void );\r
+\r
+void ppcMtmsr(\r
+ unsigned long msr_value );\r
+\r
+unsigned long ppcMfmsr(\r
+ void );\r
+\r
+unsigned long ppcOrMsr(\r
+ unsigned long value );\r
+\r
+void ppcSync(\r
+ void );\r
+\r
+void ppcLwsync(\r
+ void );\r
+\r
+void ppcPtesync(\r
+ void );\r
+\r
+void ppcEieio(\r
+ void );\r
+\r
+void ppcTestandset(\r
+ unsigned long addr,\r
+ unsigned long value );\r
+\r
+unsigned long ppcMfscom(\r
+ unsigned int scom_num );\r
+\r
+void ppcMtscom(\r
+ unsigned int scom_num,\r
+ unsigned long scom_data );\r
+\r
+/*----------------------------------------------------------------------------+\r
+| 970FX SPR's.\r
++----------------------------------------------------------------------------*/\r
+void ppcMthid0(\r
+ unsigned long data );\r
+\r
+void ppcMthid1(\r
+ unsigned long data );\r
+\r
+void ppcMthid4(\r
+ unsigned long data );\r
+\r
+void ppcMthid5(\r
+ unsigned long data );\r
+\r
+void ppcMftb(\r
+ tb_t *clock_data );\r
+\r
+void ppcMttb(\r
+ tb_t *clock_data );\r
+\r
+void ppcMtspr_any(\r
+ unsigned int spr_num,\r
+ unsigned long value );\r
+\r
+unsigned long ppcMfspr_any(\r
+ unsigned int spr_num );\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Additional functions required by debug connection.\r
++----------------------------------------------------------------------------*/\r
+int ppcCachelinesize(\r
+ void );\r
+\r
+unsigned long ppcProcid(\r
+ void );\r
+\r
+void ppcMtmmucr(\r
+ unsigned long data );\r
+\r
+void ppcMttlb1(\r
+ unsigned long index,\r
+ unsigned long value );\r
+\r
+void ppcMttlb2(\r
+ unsigned long index,\r
+ unsigned long value );\r
+\r
+void ppcMttlb3(\r
+ unsigned long index,\r
+ unsigned long value );\r
+\r
+unsigned long ppcMftlb1(\r
+ unsigned long index );\r
+\r
+unsigned long ppcMftlb2(\r
+ unsigned long index );\r
+\r
+unsigned long ppcMftlb3(\r
+ unsigned long index );\r
+\r
+unsigned long ppcMfmmucr(\r
+ void );\r
+\r
+unsigned long ppcMfdcr_any(\r
+ unsigned long dcr_num );\r
+\r
+unsigned long ppcMfspr_any_name(\r
+ char *name,\r
+ unsigned long *value_msb );\r
+\r
+void ppcMtdcr_any(\r
+ unsigned long dcr_num,\r
+ unsigned long value );\r
+\r
+void ppcMtspr_any_name(\r
+ char *name,\r
+ unsigned long value_lsb,\r
+ unsigned long value_msb );\r
+\r
+int ppcIstrap(\r
+ void );\r
+\r
+unsigned long p_ptegg(\r
+ int lp,\r
+ unsigned long ea,\r
+ unsigned long sdr1,\r
+ unsigned long vsid );\r
+\r
+unsigned long s_ptegg(\r
+ int lp,\r
+ unsigned long ea,\r
+ unsigned long sdr1,\r
+ unsigned long vsid );\r
+\r
+#endif /* _ppc970lib_h_ */\r
-/*
- * Memory map:
- *
- * _ROMBASE : start of ROM
- * _RESET : reset vector (may be at top of ROM)
- * _EXCEPTIONS_VECTORS : exception table
- *
- * _ROMSTART : linuxbios text
- * : payload text
- *
- * _RAMBASE : address to copy payload
- */
-
-/*
- * Written by Johan Rydberg, based on work by Daniel Kahlin.
- * Rewritten by Eric Biederman
- * Re-rewritten by Greg Watson for PPC
- */
-
-/*
- * We use ELF as output format. So that we can
- * debug the code in some form.
- */
-
-OUTPUT_FORMAT("elf32-powerpc")
-ENTRY(_start)
-
-TARGET(binary)
-INPUT(linuxbios_ram.rom)
+/*----------------------------------------------------------------------------+
+| Memory layout. RAM length is referenced again in __heap_size variable
+| definition.
++----------------------------------------------------------------------------*/
+MEMORY
+{
+ RAM_VECT (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 0x003F0000
+ ROM_INIT (r x) : ORIGIN = 0xFFF00000, LENGTH = 0x00002000
+ ROM (r x) : ORIGIN = 0xFFF02000, LENGTH = 0x000FE000
+}
+
+/*----------------------------------------------------------------------------+
+| Sections originally taken from default GNU LD script.
++----------------------------------------------------------------------------*/
SECTIONS
{
- /*
- * Absolute location of base of ROM
- */
- . = _ROMBASE;
-
- /*
- * Absolute location of reset vector. This may actually be at the
- * the top of ROM.
- */
- . = _RESET;
- .reset . : {
- *(.rom.reset);
- . = ALIGN(16);
- }
-
- /*
- * Absolute location of exception vector table.
- */
- . = _EXCEPTION_VECTORS;
- .exception_vectors . : {
- *(.rom.exception_vectors);
- . = ALIGN(16);
- }
-
- /*
- * Absolute location of LinuxBIOS initialization code in ROM.
- */
- . = _ROMSTART;
- .rom . : {
- _rom = .;
- *(.rom.text);
- *(.text);
- *(.rom.data);
- *(.rodata);
- *(EXCLUDE_FILE(linuxbios_ram.rom) .data);
- . = ALIGN(16);
- _erom = .;
- }
- _lrom = LOADADDR(.rom);
- _elrom = LOADADDR(.rom) + SIZEOF(.rom);
-
- /*
- * Ram is the LinuxBIOS code that runs from RAM.
- */
- .ram . : {
- _ram = . ;
- linuxbios_ram.rom(*)
- _eram = . ;
- }
-
- /*
- * Absolute location of where LinuxBIOS will be relocated in RAM.
- */
- _iseg = _RAMBASE;
- _eiseg = _iseg + SIZEOF(.ram);
- _liseg = _ram;
- _eliseg = _eram;
-
- /DISCARD/ : {
- *(.comment)
- *(.note)
- }
+
+ /*-------------------------------------------------------------------------+
+ | Create dummy section. We need to do this so that the __stext symbol is
+ | set correctly.
+ +-------------------------------------------------------------------------*/
+ .dummyt :
+ {
+ LONG(0x00000000)
+ } > RAM
+
+ /*-------------------------------------------------------------------------+
+ | Create variable holding the value of the start of the text.
+ +-------------------------------------------------------------------------*/
+ __stext = . - SIZEOF(.dummyt);
+
+ .hash :
+ {
+ *(.hash)
+ } > RAM
+
+ .dynsym :
+ {
+ *(.dynsym)
+ } > RAM
+
+ .dynstr :
+ {
+ *(.dynstr)
+ } > RAM
+
+ .rel.init :
+ {
+ *(.rel.init)
+ } > RAM
+
+ .rela.init :
+ {
+ *(.rela.init)
+ } > RAM
+
+ .rel.text :
+ {
+ *(.rel.text)
+ *(.rel.text.*)
+ *(.rel.gnu.linkonce.t.*)
+ } > RAM
+
+ .rela.text :
+ {
+ *(.rela.text)
+ *(.rela.text.*)
+ *(.rela.gnu.linkonce.t.*)
+ } > RAM
+
+ .rel.rodata :
+ {
+ *(.rel.rodata)
+ *(.rel.rodata.*)
+ *(.rel.gnu.linkonce.r.*)
+ } > RAM
+
+ .rela.rodata :
+ {
+ *(.rela.rodata)
+ *(.rela.rodata.*)
+ *(.rela.gnu.linkonce.r.*)
+ } > RAM
+
+ .rel.data :
+ {
+ *(.rel.data)
+ *(.rel.data.*)
+ *(.rel.gnu.linkonce.d.*)
+ } > RAM
+
+ .rela.data :
+ {
+ *(.rela.data)
+ *(.rela.data.*)
+ *(.rela.gnu.linkonce.d.*)
+ } > RAM
+
+ .rel.sdata :
+ {
+ *(.rel.sdata)
+ *(.rel.sdata.*)
+ *(.rel.gnu.linkonce.s.*)
+ } > RAM
+
+ .rela.sdata :
+ {
+ *(.rela.sdata)
+ *(.rela.sdata.*)
+ *(.rela.gnu.linkonce.s.*)
+ } > RAM
+
+ .rel.sbss :
+ {
+ *(.rel.sbss)
+ *(.rel.sbss.*)
+ *(.rel.gnu.linkonce.sb.*)
+ } > RAM
+
+ .rela.sbss :
+ {
+ *(.rela.sbss)
+ *(.rela.sbss.*)
+ *(.rel.gnu.linkonce.sb.*)
+ } > RAM
+
+ .rel.sdata2 :
+ {
+ *(.rel.sdata2)
+ *(.rel.sdata2.*)
+ *(.rel.gnu.linkonce.s2.*)
+ } > RAM
+
+ .rela.sdata2 :
+ {
+ *(.rela.sdata2)
+ *(.rela.sdata2.*)
+ *(.rela.gnu.linkonce.s2.*)
+ } > RAM
+
+ .rel.sbss2 :
+ {
+ *(.rel.sbss2)
+ *(.rel.sbss2.*)
+ *(.rel.gnu.linkonce.sb2.*)
+ } > RAM
+
+ .rela.sbss2 :
+ {
+ *(.rela.sbss2)
+ *(.rela.sbss2.*)
+ *(.rela.gnu.linkonce.sb2.*)
+ } > RAM
+
+ .rel.bss :
+ {
+ *(.rel.bss)
+ *(.rel.bss.*)
+ *(.rel.gnu.linkonce.b.*)
+ } > RAM
+
+ .rela.bss :
+ {
+ *(.rela.bss)
+ *(.rela.bss.*)
+ *(.rela.gnu.linkonce.b.*)
+ } > RAM
+
+ .rel.plt :
+ {
+ *(.rel.plt)
+ } > RAM
+
+ .rela.plt :
+ {
+ *(.rela.plt)
+ } > RAM
+
+ /*-------------------------------------------------------------------------+
+ | Keep the .init sections even if they are not referenced. Fill in the
+ | space (if any) in the .init serctions with 0.
+ +-------------------------------------------------------------------------*/
+ .text :
+ {
+ *(.text)
+ *(.text.*)
+ *(.stub)
+ *(.gnu.warning)
+ *(.gnu.linkonce.t.*)
+ } > RAM = 0
+
+ /*-------------------------------------------------------------------------+
+ | Create variable holding the value of the end of the text.
+ +-------------------------------------------------------------------------*/
+ __etext = .;
+
+ /*-------------------------------------------------------------------------+
+ | Create variable holding the value of the start of the data.
+ +-------------------------------------------------------------------------*/
+ __sdata = .;
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ } > RAM
+
+ .rodata1 :
+ {
+ *(.rodata1)
+ } > RAM
+
+ .sdata2 :
+ {
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ } > RAM
+
+ .sbss2 :
+ {
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ } > RAM
+
+ /*-------------------------------------------------------------------------+
+ | Align data to word boundary.
+ +-------------------------------------------------------------------------*/
+ . = ALIGN(4);
+
+ .data :
+ {
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ } > RAM
+
+ .toc :
+ {
+ *(.toc)
+ *(.toc.*)
+ } > RAM
+
+ .opd :
+ {
+ *(.opd)
+ *(.opd.*)
+ } > RAM
+
+ .data1 :
+ {
+ *(.data1)
+ } > RAM
+
+ .eh_frame :
+ {
+ KEEP(*(.eh_frame))
+ } > RAM
+
+ .fixup :
+ {
+ *(.fixup)
+ } > RAM
+
+ .dynamic :
+ {
+ *(.dynamic)
+ } > RAM
+
+ /*-------------------------------------------------------------------------+
+ | We want the small data sections together, so single-instruction offsets
+ | can access them all, and initialized data all before uninitialized, so
+ | we can shorten the on-disk segment size.
+ +-------------------------------------------------------------------------*/
+ .sdata :
+ {
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ } > RAM
+
+ /*-------------------------------------------------------------------------+
+ | Create variable holding the value of the end of the data.
+ +-------------------------------------------------------------------------*/
+ __edata = .;
+
+ /*-------------------------------------------------------------------------+
+ | Create variable holding the value of the start of the bss.
+ +-------------------------------------------------------------------------*/
+ __sbss = .;
+
+ .sbss :
+ {
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ } > RAM
+
+ .plt :
+ {
+ *(.plt)
+ } > RAM
+
+ /*-------------------------------------------------------------------------+
+ | Common symbols are placed in the BSS section.
+ +-------------------------------------------------------------------------*/
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ } > RAM
+
+ /*-------------------------------------------------------------------------+
+ | Align so that the bss size and __ebss are word aligned.
+ +-------------------------------------------------------------------------*/
+ . = ALIGN(4);
+
+ /*-------------------------------------------------------------------------+
+ | Create variable holding the value of the end of the bss.
+ +-------------------------------------------------------------------------*/
+ __ebss = .;
+
+ /*-------------------------------------------------------------------------+
+ | Create variables describing the heap. The value "0x3F0000" must be
+ | equal to RAM length.
+ +-------------------------------------------------------------------------*/
+ __heap_start = .;
+ __heap_size = 0x3F0000 + ADDR(.dummyt) - .;
+
+ /*-------------------------------------------------------------------------+
+ | Stabs. Symbols in the following sections are relative to the beginning
+ | of the section so we begin them at 0.
+ +-------------------------------------------------------------------------*/
+ .stab 0 :
+ {
+ *(.stab)
+ }
+
+ .stabstr 0 :
+ {
+ *(.stabstr)
+ }
+
+ .stab.excl 0 :
+ {
+ *(.stab.excl)
+ }
+
+ .stab.exclstr 0 :
+ {
+ *(.stab.exclstr)
+ }
+
+ .stab.index 0 :
+ {
+ *(.stab.index)
+ }
+
+ .stab.indexstr 0 :
+ {
+ *(.stab.indexstr)
+ }
+
}
#include <board.h>
#include <sdram.h>
+#ifndef __PPC64__
extern unsigned _iseg[];
extern unsigned _liseg[];
extern unsigned _eliseg[];
void (*payload)(void) = (void (*)(void))_iseg;
+#endif
/*
* At this point we're running out of flash with our
* - start hardwaremain() which does remainder of setup
*/
+#ifndef __PPC64__
extern void flush_dcache(void);
+#endif
void ppc_main(void)
{
*/
board_init2();
+#ifndef __PPC64__
/*
* Flush cache now that memory is enabled.
*/
}
payload();
+#endif
/* NOT REACHED */
}
* configuring the machine.
*/
+#ifndef __PPC64__
#define ASM
#include "ppcreg.h"
#include <ppc_asm.tmpl>
.globl __DTOR_END__
__DTOR_END__:
blr
+
+#endif
*/
#include <ppc_asm.tmpl>
+#ifndef __PPC64__
.globl __div64_32
__div64_32:
+#else
+ .globl .__div64_32
+.__div64_32:
+#endif
lwz r5,0(r3) # get the dividend into r5/r6
lwz r6,4(r3)
cmplw r5,r4
/*
* unsigned long long _get_ticks(void);
*/
+#ifndef __PPC64__
.globl _get_ticks
_get_ticks:
+#else
+ .globl ._get_ticks
+._get_ticks:
+#endif
1: mftbu r3
mftb r4
mftbu r5
/*
* Delay for a number of ticks
*/
+#ifndef __PPC64__
.globl _wait_ticks
_wait_ticks:
+#else
+ .globl ._wait_ticks
+._wait_ticks:
+#endif
mflr r8 /* save link register */
mr r7, r3 /* save tick count */
+#ifndef __PPC64__
bl _get_ticks /* Get start time */
+#else
+ bl ._get_ticks /* Get start time */
+#endif
/* Calculate end time */
addc r7, r4, r7 /* Compute end time lower */
addze r6, r3 /* and end time upper */
+#ifndef __PPC64__
1: bl _get_ticks /* Get current time */
+#else
+1: bl ._get_ticks /* Get current time */
+#endif
subfc r4, r4, r7 /* Subtract current time from end time */
subfe. r3, r3, r6
bge 1b /* Loop until time expired */
##
default USE_DCACHE_RAM=0
-initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc
+initinclude "EXCEPTION_VECTOR_TABLE" cpu/ppc/ppc970/ppc970excp.S
+initinclude "PROCESSOR_INIT" cpu/ppc/ppc970/ppc970.inc
+
+object clock.o
+initobject clock.o
+initobject ppc970lib.S
+
+dir /cpu/simple_init
--- /dev/null
+#include <ppc.h>
+
+static int PLL_multiplier[] = {
+ 25, /* 0000 - 2.5x */
+ 75, /* 0001 - 7.5x */
+ 70, /* 0010 - 7x */
+ 10, /* 0011 - bypass */
+ 20, /* 0100 - 2x */
+ 65, /* 0101 - 6.5x */
+ 100, /* 0110 - 10x */
+ 45, /* 0111 - 4.5x */
+ 30, /* 1000 - 3x */
+ 55, /* 1001 - 5.5x */
+ 40, /* 1010 - 4x */
+ 50, /* 1011 - 5x */
+ 80, /* 1100 - 8x */
+ 60, /* 1101 - 6x */
+ 35, /* 1110 - 3.5x */
+ 0, /* 1111 - off */
+};
+
+unsigned long
+get_timer_freq(void)
+{
+ unsigned long clock = CONFIG_SYS_CLK_FREQ * 1000000;
+ return clock * PLL_multiplier[ppc_gethid1() >> 28] / 10;
+}
-/*bsp_970fx/bootlib/init_core.s, pibs_970, pibs_970_1.0 1/14/05 14:58:41*/
-/*----------------------------------------------------------------------------+
-| COPYRIGHT I B M CORPORATION 2002, 2004
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-| US Government Users Restricted Rights - Use, duplication or
-| disclosure restricted by GSA ADP Schedule Contract with
-| IBM Corp.
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| PPC970FX BSP for EPOS
-| Author: Maciej P. Tyrlik
-| Component: Boot library.
-| File: init_core.s
-| Purpose: Basic PPC405 core initialization.
-| Changes:
-| Date: Comment:
-| ----- --------
-| 29-Jan-02 Created MPT
-| 30-Jan-02 Completed MPT
-| 19-Apr-02 Changed some instructions to macros so that new GCC AS worksMPT
-| 23-Apr-02 Removed critical interrupt enabling after rfi MPT
-| 31-Jul-02 Fixed data cache invalidate code MPT
-| 01-Feb-03 Ported to Argan 7XXFX CRB
-| 07-Aug-03 Ported to PPC7XXGX CRB
-| 12-Sep-03 Removed PVR definitions, now in board include file MCG
-| 16-Sep-03 Do not enable HID0[MUM] or L2CR[L2CE] if 7XXGX DD1.0 MCG
-| 31-Oct-03 Enable cache for MV64460 integrated SRAM MCG
-| 07-Jan-04 Initialize FPRs to avoid errata. MCG
-| 10-Feb-04 Port to PPC970FX MPT
-+----------------------------------------------------------------------------*/
-
-#include <ppc970.h>
-
-/*----------------------------------------------------------------------------+
-| Local defines.
-+----------------------------------------------------------------------------*/
-#define INITIAL_SLB_VSID_VAL 0x0000000000000C00
-#define INITIAL_SLB_ESID_VAL 0x0000000008000000
-#define INITIAL_SLB_INVA_VAL 0x0000000000000000
-
-/*----------------------------------------------------------------------------+
-| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0.
-| Data cahability must be turned on. Instruction cahability must be off.
-+----------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------+
- | Set time base to 0.
- +--------------------------------------------------------------------*/
- addi r4,r0,0x0000
- mtspr SPR_TBU_WRITE,r4
- mtspr SPR_TBL_WRITE,r4
- /*--------------------------------------------------------------------+
- | Set HID1[10] to 0 (instruction cache off) and set HID4[23] to 0 (data
- | cache on), set HID4[DC_SET1] and HID4[DC_SET2] to 0.
- +--------------------------------------------------------------------*/
- LOAD_64BIT_VAL(r4,HID1_EN_IC)
- nor r4,r4,r4
- mfspr r5,SPR_HID1
- isync
- and r5,r5,r4
- mtspr SPR_HID1,r5
- mtspr SPR_HID1,r5
- isync
- LOAD_64BIT_VAL(r4,HID4_RM_CI|HID4_DC_SET1|HID4_DC_SET2)
- nor r4,r4,r4
- mfspr r5,SPR_HID4
- LOAD_64BIT_VAL(r6,HID4_L1DC_FLSH)
- isync
- and r5,r5,r4
- or r5,r5,r6
- sync
- mtspr SPR_HID4,r5
- isync
- /*--------------------------------------------------------------------+
- | Clear the flash invalidate L1 data cache bit in HID4.
- +--------------------------------------------------------------------*/
- nor r6,r6,r6
- and r5,r5,r6
- sync
- mtspr SPR_HID4,r5
- isync
- /*--------------------------------------------------------------------+
- | Clear and set up some registers.
- +--------------------------------------------------------------------*/
- addi r4,r0,0x0000
- mtxer r4
- /*--------------------------------------------------------------------+
- | Invalidate SLB. First load SLB with known values then perform
- | invalidate. Invalidate will clear the D-ERAT and I-ERAT. The SLB
- | is 64 entry fully associative. On power on D-ERAT and I-ERAT are all
- | set to invalid values.
- +--------------------------------------------------------------------*/
- addi r5,r0,SLB_SIZE
- mtctr r5
- LOAD_64BIT_VAL(r6,INITIAL_SLB_VSID_VAL)
- LOAD_64BIT_VAL(r7,INITIAL_SLB_ESID_VAL)
- addis r8,r0,0x1000
-0: slbmte r6,r7
- addi r6,r6,0x1000
- add r7,r7,r8
- addi r7,r7,0x0001
- bdnz 0b
- mtctr r5
- LOAD_64BIT_VAL(r6,INITIAL_SLB_INVA_VAL)
-1: slbie r6
- add r6,r6,r8
- bdnz 1b
- /*--------------------------------------------------------------------+
- | Load SLB. Following is the initial memory map.
- | Entry(6) ESID(36) VSID
- | 0x0 0x000000000 0x0000000000000 (large page cachable)
- | 0x1 0x00000000F 0x000000000000F (small non-cachable, G)
- | at 0x00000000 there will be 48MB mapped (SDRAM)
- | at 0xF8000000 there will be 16MB mapped (NB)
- | at 0xF4000000 there will be 64KB mapped (I/O space)
- | at 0xFF000000 there will be 16MB or 1MB mapped (FLASH)
- +--------------------------------------------------------------------*/
- addi r6,r0,0x0100
- addis r7,r0,0x0800
- slbmte r6,r7
- addi r6,r0,0x0000
- ori r6,r6,0xF000
- addi r7,r0,0x0001
- oris r7,r7,0xF800
- slbmte r6,r7
- /*--------------------------------------------------------------------+
- | Invalidate all 1024 instruction and data TLBs (4 way)
- +--------------------------------------------------------------------*/
- addi r8,r0,0x0100
- mtspr CTR,r8
- addi r8,r0,0x0000
-2: TLBIEL(r8)
- addi r8,r8,0x1000
- bdnz 2b
- ptesync
- /*--------------------------------------------------------------------+
- | Dcbz the page table space. Calculate SDR1 address. Store SDR1
- | address in r30.
- +--------------------------------------------------------------------*/
- mfspr r3,SPR_PIR
- cmpi cr0,1,r3,0x0000
- bne 3f
- addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU0@h
- ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU0@l
- b 4f
-3: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h
- ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU1@l
-4: addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h
- ori r4,r4,INITIAL_PAGE_TABLE_SIZE@l
- rlwinm r5,r4,14,14,31
- cntlzw r5,r5
- subfic r5,r5,31
- or r30,r3,r5
- bl .ppcDcbz_area
- /*--------------------------------------------------------------------+
- | Setup 0x00000000FFFFFFFF mask in r29.
- +--------------------------------------------------------------------*/
- addi r29,r0,0x0001
- rldicl r29,r29,32,31
- addi r29,r29,-1
- /*--------------------------------------------------------------------+
- | Setup 48MB of addresses in DRAM in page table (3 large PTE). The
- | parameters to p_ptegg are: r3 = lp, r4 = ea, r5 = sdr1, r6 = vsid.
- +--------------------------------------------------------------------*/
- addi r3,r0,0x0001
- addi r4,r0,0x0000
- ori r5,r30,0x0000
- addi r6,r0,0x0000
- bl .p_ptegg
- addi r4,r0,0x0001
- stw r4,0x0004(r3)
- addi r4,r0,0x0180
- stw r4,0x000C(r3)
- /*--------------------------------------------------------------------+
- | Second 16MB is mapped here.
- +--------------------------------------------------------------------*/
- addi r3,r0,0x0001
- addis r4,r0,0x0100
- ori r5,r30,0x0000
- addi r6,r0,0x0000
- bl .p_ptegg
- addi r4,r0,0x0101
- stw r4,0x0004(r3)
- addis r4,r0,0x0100
- ori r4,r4,0x0180
- stw r4,0x000C(r3)
- /*--------------------------------------------------------------------+
- | Third 16MB is mapped here.
- +--------------------------------------------------------------------*/
- addi r3,r0,0x0001
- addis r4,r0,0x0200
- ori r5,r30,0x0000
- addi r6,r0,0x0000
- bl .p_ptegg
- addi r4,r0,0x0201
- stw r4,0x0004(r3)
- addis r4,r0,0x0200
- ori r4,r4,0x0180
- stw r4,0x000C(r3)
- /*--------------------------------------------------------------------+
- | Setup 64KB of addresses in I/O space (0xF4000000).
- +--------------------------------------------------------------------*/
- addi r3,r0,0x0010
- mtctr r3
- addis r31,r0,0xF400
- and r31,r31,r29
-5: addi r3,r0,0x0000
- ori r4,r31,0x0000
- ori r5,r30,0x0000
- addi r6,r0,0x000F
- bl .p_ptegg
- addi r6,r3,0x0080
-6: lwz r4,0x0004(r3)
- cmpli cr0,1,r4,0x0000
- beq 8f
- addi r3,r3,0x0010
- cmp cr0,1,r3,r6
- blt 6b
-7: b 7b
-8: rlwinm r4,r31,16,4,24
- ori r4,r4,0x0001
- stw r4,0x0004(r3)
- ori r4,r31,0x01AC
- stw r4,0x000C(r3)
- addi r31,r31,0x1000
- bdnz 5b
- /*--------------------------------------------------------------------+
- | Setup 16MB of addresses in NB register space (0xF8000000).
- +--------------------------------------------------------------------*/
- addi r3,r0,0x1000
- mtctr r3
- addis r31,r0,0xF800
- and r31,r31,r29
-9: addi r3,r0,0x0000
- ori r4,r31,0x0000
- ori r5,r30,0x0000
- addi r6,r0,0x000F
- bl .p_ptegg
- addi r6,r3,0x0080
-10: lwz r4,0x0004(r3)
- cmpli cr0,1,r4,0x0000
- beq 12f
- addi r3,r3,0x0010
- cmp cr0,1,r3,r6
- blt 10b
-11: b 11b
-12: rlwinm r4,r31,16,4,24
- ori r4,r4,0x0001
- stw r4,0x0004(r3)
- ori r4,r31,0x01AC
- stw r4,0x000C(r3)
- addi r31,r31,0x1000
- bdnz 9b
- /*--------------------------------------------------------------------+
- | Setup 16MB or 1MB of addresses in ROM (at 0xFF000000 or 0xFFF00000).
- +--------------------------------------------------------------------*/
- mfspr r3,SPR_HIOR
- LOAD_64BIT_VAL(r4,BOOT_BASE_AS)
- cmpd cr0,r3,r4
- beq 13f
- addi r3,r0,0x0100
- mtctr r3
- addis r31,r0,0xFFF0
- b 14f
-13: addi r3,r0,0x1000
- mtctr r3
- addis r31,r0,0xFF00
-14: and r31,r31,r29
-15: addi r3,r0,0x0000
- ori r4,r31,0x0000
- ori r5,r30,0x0000
- addi r6,r0,0x000F
- bl .p_ptegg
- addi r6,r3,0x0080
-16: lwz r4,0x0004(r3)
- cmpli cr0,1,r4,0x0000
- beq 18f
- addi r3,r3,0x0010
- cmp cr0,1,r3,r6
- blt 16b
-17: b 17b
-18: rlwinm r4,r31,16,4,24
- ori r4,r4,0x0001
- stw r4,0x0004(r3)
- ori r4,r31,0x01A3
- stw r4,0x000C(r3)
- addi r31,r31,0x1000
- bdnz 15b
- /*--------------------------------------------------------------------+
- | Synchronize after setting up page table.
- +--------------------------------------------------------------------*/
- ptesync
- /*--------------------------------------------------------------------+
- | Set the SDR1 register.
- +--------------------------------------------------------------------*/
- mtspr SPR_SDR1,r30
- /*--------------------------------------------------------------------+
- | Clear SRR0, SRR1.
- +--------------------------------------------------------------------*/
- addi r0,r0,0x0000
- mtspr SPR_SRR0,r0
- mtspr SPR_SRR1,r0
- /*--------------------------------------------------------------------+
- | Setup for subsequent MSR[ME] initialization to enable machine checks
- | and translation.
- +--------------------------------------------------------------------*/
- mfmsr r3
- ori r3,r3,(MSR_ME|MSR_IS|MSR_DS|MSR_FP)
- mtsrr1 r3
- mtmsrd r3,0
- isync
- /*--------------------------------------------------------------------+
- | Setup HID registers (HID0, HID1, HID4, HID5). When HIOR is set to
- | 0 HID0 external time base bit is inherited from current HID0. When
- | HIOR is set to FLASH_BASE_INTEL_AS then HID0 external time base bit
- | is set to 1 in order to indicate that the tiembase is driven by
- | external source. When HIOR is greater than FLASH_BASE_INTEL_AS then
- | HID0 external time base bit is set to 0 in order to indicate that the
- | tiembase is driven from internal clock.
- +--------------------------------------------------------------------*/
- LOAD_64BIT_VAL(r6,HID0_EXT_TB_EN)
- LOAD_64BIT_VAL(r7,FLASH_BASE_INTEL_AS)
- mfspr r5,SPR_HIOR
- cmpdi cr0,r5,0x0000
- beq 19f
- cmpd cr0,r5,r7
- beq 20f
- addi r8,r0,0x0000
- b 21f
-20: ori r8,r6,0x0000
- b 21f
-19: mfspr r5,SPR_HID0
- and r8,r5,r6
-21: LOAD_64BIT_VAL(r4,HID0_PREFEAR)
- andc r4,r4,r6
- or r4,r4,r8
- sync
- mtspr SPR_HID0,r4
- mfspr r4,SPR_HID0
- mfspr r4,SPR_HID0
- mfspr r4,SPR_HID0
- mfspr r4,SPR_HID0
- mfspr r4,SPR_HID0
- mfspr r4,SPR_HID0
- LOAD_64BIT_VAL(r4,HID1_PREFEAR)
- mtspr SPR_HID1,r4
- mtspr SPR_HID1,r4
- isync
- LOAD_64BIT_VAL(r4,HID4_PREFEAR)
- sync
- mtspr SPR_HID4,r4
- isync
- sync
- LOAD_64BIT_VAL(r4,HID5_PREFEAR)
- mtspr SPR_HID5,r4
- isync
- /*--------------------------------------------------------------------+
- | Synchronize memory accesses (sync).
- +--------------------------------------------------------------------*/
- sync
- LOAD_64BIT_VAL(r0,.init_chip)
- mfspr r1,SPR_HIOR
- or r0,r0,r1
- eieio
- mtspr SPR_SRR0,r0
- rfid
+\r
+#include <ppc970.h>\r
+\r
+/******** init_core.s ***************/\r
+/*----------------------------------------------------------------------------+\r
+| Local defines.\r
++----------------------------------------------------------------------------*/\r
+#define INITIAL_SLB_VSID_VAL 0x0000000000000C00\r
+#define INITIAL_SLB_ESID_VAL 0x0000000008000000\r
+#define INITIAL_SLB_INVA_VAL 0x0000000000000000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0.\r
+| Data cahability must be turned on. Instruction cahability must be off.\r
++----------------------------------------------------------------------------*/\r
+function_prolog(init_core)\r
+ /*--------------------------------------------------------------------+\r
+ | Set time base to 0.\r
+ +--------------------------------------------------------------------*/\r
+ addi r4,r0,0x0000\r
+ mtspr SPR_TBU_WRITE,r4\r
+ mtspr SPR_TBL_WRITE,r4\r
+ /*--------------------------------------------------------------------+\r
+ | Set HID1[10] to 0 (instruction cache off) and set HID4[23] to 0 (data\r
+ | cache on), set HID4[DC_SET1] and HID4[DC_SET2] to 0.\r
+ +--------------------------------------------------------------------*/\r
+ LOAD_64BIT_VAL(r4,HID1_EN_IC)\r
+ nor r4,r4,r4\r
+ mfspr r5,SPR_HID1\r
+ isync\r
+ and r5,r5,r4\r
+ mtspr SPR_HID1,r5 \r
+ mtspr SPR_HID1,r5 \r
+ isync\r
+ LOAD_64BIT_VAL(r4,HID4_RM_CI|HID4_DC_SET1|HID4_DC_SET2)\r
+ nor r4,r4,r4\r
+ mfspr r5,SPR_HID4\r
+ LOAD_64BIT_VAL(r6,HID4_L1DC_FLSH)\r
+ isync\r
+ and r5,r5,r4\r
+ or r5,r5,r6\r
+ sync\r
+ mtspr SPR_HID4,r5 \r
+ isync\r
+ /*--------------------------------------------------------------------+\r
+ | Clear the flash invalidate L1 data cache bit in HID4.\r
+ +--------------------------------------------------------------------*/\r
+ nor r6,r6,r6\r
+ and r5,r5,r6\r
+ sync\r
+ mtspr SPR_HID4,r5 \r
+ isync\r
+ /*--------------------------------------------------------------------+\r
+ | Clear and set up some registers.\r
+ +--------------------------------------------------------------------*/\r
+ addi r4,r0,0x0000\r
+ mtxer r4\r
+ /*--------------------------------------------------------------------+\r
+ | Invalidate SLB. First load SLB with known values then perform \r
+ | invalidate. Invalidate will clear the D-ERAT and I-ERAT. The SLB\r
+ | is 64 entry fully associative. On power on D-ERAT and I-ERAT are all\r
+ | set to invalid values.\r
+ +--------------------------------------------------------------------*/\r
+ addi r5,r0,SLB_SIZE\r
+ mtctr r5\r
+ LOAD_64BIT_VAL(r6,INITIAL_SLB_VSID_VAL)\r
+ LOAD_64BIT_VAL(r7,INITIAL_SLB_ESID_VAL)\r
+ addis r8,r0,0x1000\r
+..slbl: slbmte r6,r7\r
+ addi r6,r6,0x1000\r
+ add r7,r7,r8\r
+ addi r7,r7,0x0001\r
+ bdnz ..slbl\r
+ mtctr r5\r
+ LOAD_64BIT_VAL(r6,INITIAL_SLB_INVA_VAL)\r
+..slbi: slbie r6\r
+ add r6,r6,r8\r
+ bdnz ..slbi\r
+ /*--------------------------------------------------------------------+\r
+ | Load SLB. Following is the initial memory map.\r
+ | Entry(6) ESID(36) VSID\r
+ | 0x0 0x000000000 0x0000000000000 (large page cachable)\r
+ | 0x1 0x00000000F 0x000000000000F (small non-cachable, G)\r
+ | at 0x00000000 there will be 32MB mapped (SDRAM)\r
+ | at 0xF8000000 there will be 16MB mapped (NB)\r
+ | at 0xF4000000 there will be 64KB mapped (I/O space)\r
+ | at 0xFF000000 there will be 16MB or 1MB mapped (FLASH)\r
+ +--------------------------------------------------------------------*/\r
+ addi r6,r0,0x0100\r
+ addis r7,r0,0x0800\r
+ slbmte r6,r7\r
+ addi r6,r0,0x0000\r
+ ori r6,r6,0xF000\r
+ addi r7,r0,0x0001\r
+ oris r7,r7,0xF800\r
+ slbmte r6,r7\r
+ /*--------------------------------------------------------------------+\r
+ | Invalidate all 1024 instruction and data TLBs (4 way)\r
+ +--------------------------------------------------------------------*/\r
+ addi r8,r0,0x0100\r
+ mtspr ctr,r8\r
+ addi r8,r0,0x0000\r
+..ivt: TLBIEL(r8)\r
+ addi r8,r8,0x1000\r
+ bdnz ..ivt\r
+ ptesync\r
+ /*--------------------------------------------------------------------+\r
+ | Dcbz the page table space. Calculate SDR1 address. Store SDR1\r
+ | address in r30.\r
+ +--------------------------------------------------------------------*/\r
+ mfspr r3,SPR_PIR\r
+ cmpi cr0,1,r3,0x0000\r
+ bne ..cpu1_init_core\r
+ addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU0@h\r
+ ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU0@l\r
+ b ..skcpu\r
+..cpu1_init_core: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h\r
+ ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU1@l\r
+..skcpu:addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h\r
+ ori r4,r4,INITIAL_PAGE_TABLE_SIZE@l\r
+ rlwinm r5,r4,14,14,31 \r
+ cntlzw r5,r5\r
+ subfic r5,r5,31\r
+ or r30,r3,r5\r
+ bl .ppcDcbz_area\r
+ /*--------------------------------------------------------------------+\r
+ | Setup 0x00000000FFFFFFFF mask in r29. \r
+ +--------------------------------------------------------------------*/\r
+ addi r29,r0,0x0001\r
+ rldicl r29,r29,32,31\r
+ addi r29,r29,-1\r
+ /*--------------------------------------------------------------------+\r
+ | Setup 32MB of addresses in DRAM in page table (2 large PTE). The \r
+ | parameters to p_ptegg are: r3 = lp, r4 = ea, r5 = sdr1, r6 = vsid.\r
+ +--------------------------------------------------------------------*/\r
+ addi r3,r0,0x0001\r
+ addi r4,r0,0x0000\r
+ ori r5,r30,0x0000\r
+ addi r6,r0,0x0000\r
+ bl .p_ptegg\r
+ addi r4,r0,0x0001\r
+ stw r4,0x0004(r3)\r
+ addi r4,r0,0x0180\r
+ stw r4,0x000C(r3)\r
+ /*--------------------------------------------------------------------+\r
+ | Second 32MB is mapped here.\r
+ +--------------------------------------------------------------------*/\r
+ addi r3,r0,0x0001\r
+ addis r4,r0,0x0100\r
+ ori r5,r30,0x0000\r
+ addi r6,r0,0x0000\r
+ bl .p_ptegg\r
+ addi r4,r0,0x0101\r
+ stw r4,0x0004(r3)\r
+ addis r4,r0,0x0100\r
+ ori r4,r4,0x0180\r
+ stw r4,0x000C(r3)\r
+ /*--------------------------------------------------------------------+\r
+ | Setup 64KB of addresses in I/O space (0xF4000000).\r
+ +--------------------------------------------------------------------*/\r
+ addi r3,r0,0x0010\r
+ mtctr r3\r
+ addis r31,r0,0xF400\r
+ and r31,r31,r29\r
+..aF4: addi r3,r0,0x0000\r
+ ori r4,r31,0x0000\r
+ ori r5,r30,0x0000\r
+ addi r6,r0,0x000F\r
+ bl .p_ptegg\r
+ addi r6,r3,0x0080\r
+..aF4a: lwz r4,0x0004(r3)\r
+ cmpli cr0,1,r4,0x0000\r
+ beq ..aF4s\r
+ addi r3,r3,0x0010\r
+ cmp cr0,1,r3,r6\r
+ blt ..aF4a\r
+..aF4h: b ..aF4h\r
+..aF4s: rlwinm r4,r31,16,4,24\r
+ ori r4,r4,0x0001\r
+ stw r4,0x0004(r3)\r
+ ori r4,r31,0x01AC\r
+ stw r4,0x000C(r3)\r
+ addi r31,r31,0x1000\r
+ bdnz ..aF4\r
+ /*--------------------------------------------------------------------+\r
+ | Setup 16MB of addresses in NB register space (0xF8000000).\r
+ +--------------------------------------------------------------------*/\r
+ addi r3,r0,0x1000\r
+ mtctr r3\r
+ addis r31,r0,0xF800\r
+ and r31,r31,r29\r
+..aF8: addi r3,r0,0x0000\r
+ ori r4,r31,0x0000\r
+ ori r5,r30,0x0000\r
+ addi r6,r0,0x000F\r
+ bl .p_ptegg\r
+ addi r6,r3,0x0080\r
+..aF8a: lwz r4,0x0004(r3)\r
+ cmpli cr0,1,r4,0x0000\r
+ beq ..aF8s\r
+ addi r3,r3,0x0010\r
+ cmp cr0,1,r3,r6\r
+ blt ..aF8a\r
+..aF8h: b ..aF8h\r
+..aF8s: rlwinm r4,r31,16,4,24\r
+ ori r4,r4,0x0001\r
+ stw r4,0x0004(r3)\r
+ ori r4,r31,0x01AC\r
+ stw r4,0x000C(r3)\r
+ addi r31,r31,0x1000\r
+ bdnz ..aF8\r
+ /*--------------------------------------------------------------------+\r
+ | Setup 16MB or 1MB of addresses in ROM (at 0xFF000000 or 0xFFF00000).\r
+ +--------------------------------------------------------------------*/\r
+ mfspr r3,SPR_HIOR\r
+ LOAD_64BIT_VAL(r4,BOOT_BASE_AS)\r
+ cmpd cr0,r3,r4\r
+ beq ..big\r
+ addi r3,r0,0x0100\r
+ mtctr r3\r
+ addis r31,r0,0xFFF0\r
+ b ..done\r
+..big: addi r3,r0,0x1000\r
+ mtctr r3\r
+ addis r31,r0,0xFF00\r
+..done: and r31,r31,r29\r
+..aFF: addi r3,r0,0x0000\r
+ ori r4,r31,0x0000\r
+ ori r5,r30,0x0000\r
+ addi r6,r0,0x000F\r
+ bl .p_ptegg\r
+ addi r6,r3,0x0080\r
+..aFFa: lwz r4,0x0004(r3)\r
+ cmpli cr0,1,r4,0x0000\r
+ beq ..aFFs\r
+ addi r3,r3,0x0010\r
+ cmp cr0,1,r3,r6\r
+ blt ..aFFa\r
+..aFFh: b ..aFFh\r
+..aFFs: rlwinm r4,r31,16,4,24\r
+ ori r4,r4,0x0001\r
+ stw r4,0x0004(r3)\r
+ ori r4,r31,0x01A3\r
+ stw r4,0x000C(r3)\r
+ addi r31,r31,0x1000\r
+ bdnz ..aFF\r
+ /*--------------------------------------------------------------------+\r
+ | Synchronize after setting up page table.\r
+ +--------------------------------------------------------------------*/\r
+ ptesync\r
+ /*--------------------------------------------------------------------+\r
+ | Set the SDR1 register.\r
+ +--------------------------------------------------------------------*/\r
+ mtspr SPR_SDR1,r30\r
+ /*--------------------------------------------------------------------+\r
+ | Clear SRR0, SRR1.\r
+ +--------------------------------------------------------------------*/\r
+ addi r0,r0,0x0000\r
+ mtspr SPR_SRR0,r0\r
+ mtspr SPR_SRR1,r0\r
+ /*--------------------------------------------------------------------+\r
+ | Setup for subsequent MSR[ME] initialization to enable machine checks\r
+ | and translation.\r
+ +--------------------------------------------------------------------*/\r
+ mfmsr r3\r
+ ori r3,r3,(MSR_ME|MSR_IS|MSR_DS|MSR_FP)\r
+ mtsrr1 r3\r
+ mtmsrd r3,0\r
+ isync\r
+ /*--------------------------------------------------------------------+\r
+ | Setup HID registers (HID0, HID1, HID4, HID5). When HIOR is set to\r
+ | 0 HID0 external time base bit is inherited from current HID0. When\r
+ | HIOR is set to FLASH_BASE_INTEL_AS then HID0 external time base bit\r
+ | is set to 1 in order to indicate that the tiembase is driven by\r
+ | external source. When HIOR is greater than FLASH_BASE_INTEL_AS then\r
+ | HID0 external time base bit is set to 0 in order to indicate that the\r
+ | tiembase is driven from internal clock.\r
+ +--------------------------------------------------------------------*/\r
+ LOAD_64BIT_VAL(r6,HID0_EXT_TB_EN)\r
+ LOAD_64BIT_VAL(r7,FLASH_BASE_INTEL_AS)\r
+ mfspr r5,SPR_HIOR\r
+ cmpdi cr0,r5,0x0000\r
+ beq ..hior0\r
+ cmpd cr0,r5,r7\r
+ beq ..hiorl\r
+ addi r8,r0,0x0000 \r
+ b ..hiors\r
+..hiorl:ori r8,r6,0x0000\r
+ b ..hiors\r
+..hior0:mfspr r5,SPR_HID0\r
+ and r8,r5,r6\r
+..hiors:LOAD_64BIT_VAL(r4,HID0_PREFEAR)\r
+ andc r4,r4,r6\r
+ or r4,r4,r8 \r
+ sync\r
+ mtspr SPR_HID0,r4\r
+ mfspr r4,SPR_HID0\r
+ mfspr r4,SPR_HID0\r
+ mfspr r4,SPR_HID0\r
+ mfspr r4,SPR_HID0\r
+ mfspr r4,SPR_HID0\r
+ mfspr r4,SPR_HID0\r
+ LOAD_64BIT_VAL(r4,HID1_PREFEAR)\r
+ mtspr SPR_HID1,r4\r
+ mtspr SPR_HID1,r4\r
+ isync\r
+ LOAD_64BIT_VAL(r4,HID4_PREFEAR)\r
+ sync \r
+ mtspr SPR_HID4,r4\r
+ isync\r
+ sync\r
+ LOAD_64BIT_VAL(r4,HID5_PREFEAR)\r
+ mtspr SPR_HID5,r4\r
+ isync\r
+ /*--------------------------------------------------------------------+\r
+ | Synchronize memory accesses (sync).\r
+ +--------------------------------------------------------------------*/\r
+ sync\r
+ LOAD_64BIT_VAL(r0,.init_chip)\r
+ mfspr r1,SPR_HIOR\r
+ or r0,r0,r1\r
+ eieio\r
+ mtspr SPR_SRR0,r0\r
+ rfid\r
+ function_epilog(init_core)\r
+\r
+\r
+/******** init_chip.s ***************/\r
+/*----------------------------------------------------------------------------+\r
+| Local defines.\r
++----------------------------------------------------------------------------*/\r
+#define CPU1_DELAY 0x00010000\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Init_chip.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(init_chip)\r
+ /*--------------------------------------------------------------------+\r
+ | Skip if CPU1.\r
+ +--------------------------------------------------------------------*/\r
+ mfspr r3,SPR_PIR\r
+ cmpi cr0,1,r3,0x0000\r
+ bne ..cpu1\r
+ /*--------------------------------------------------------------------+\r
+ | Initialize the stack in the data cache for the "C" code that gets\r
+ | called.\r
+ +--------------------------------------------------------------------*/\r
+ addis r3,r0,BOOT_STACK_ADDR@h\r
+ ori r3,r3,BOOT_STACK_ADDR@l\r
+ addis r4,r0,BOOT_STACK_SIZE@h\r
+ ori r4,r4,BOOT_STACK_SIZE@l\r
+ add r1,r3,r4\r
+ bl .ppcDcbz_area\r
+ addi r1,r1,-stack_frame_min\r
+ addi r5,r0,0x0000\r
+ std r5,stack_frame_bc(r1)\r
+ /*--------------------------------------------------------------------+\r
+ | Load TOC. Can't use ld since the TOC value might not be aligned on\r
+ | double word boundary.\r
+ +--------------------------------------------------------------------*/\r
+ bl ..ot_init_chip\r
+ .quad .TOC.@tocbase\r
+..ot_init_chip: mflr r3\r
+ lwz r2,0x0000(r3)\r
+ lwz r3,0x0004(r3)\r
+ rldicr r2,r2,32,31\r
+ or r2,r2,r3\r
+ mfspr r3,SPR_HIOR\r
+ or r2,r2,r3\r
+ /*--------------------------------------------------------------------+\r
+ | Code for chip initialization code goes here. Subtractive decoding\r
+ | allows access to specified registers.\r
+ +--------------------------------------------------------------------*/\r
+ bl .super_io_setup\r
+ /*--------------------------------------------------------------------+\r
+ | Setup default serial port using default baud rate.\r
+ +--------------------------------------------------------------------*/\r
+// bl .sinit_default_no_global\r
+ /*--------------------------------------------------------------------+\r
+ | Enable SDRAM only if running from FLASH.\r
+ +--------------------------------------------------------------------*/\r
+ mflr r3\r
+ LOAD_64BIT_VAL(r4,BOOT_BASE_AS)\r
+ cmpld cr0,r3,r4\r
+ blt ..skip\r
+ bl memory_init\r
+ /*--------------------------------------------------------------------+\r
+ | Check the memory where PIBS data section will be placed.\r
+ +--------------------------------------------------------------------*/\r
+..skip: bl ..skip_data\r
+ .string "\nMemory check failed at 0x%x, expected 0x%x, actual 0x%x"\r
+ .align 2\r
+..skip_data:\r
+ addis r3,r0,MEM_CHK_START_ADDR@h\r
+ ori r3,r3,MEM_CHK_START_ADDR@l\r
+ addis r4,r0,MEM_CHK_SIZE@h\r
+ ori r4,r4,MEM_CHK_SIZE@l\r
+ mflr r5\r
+// bl mem_check\r
+ /*--------------------------------------------------------------------+\r
+ | Initialize RAM area that holds boot information for CPU1.\r
+ +--------------------------------------------------------------------*/\r
+ LOAD_64BIT_VAL(r31,CPU1_DATA_STRUCT_ADDR)\r
+ addi r3,r0,0x0000\r
+ std r3,CPU1_DATA_STRUCT_VALID_OFF(r31)\r
+ /*--------------------------------------------------------------------+\r
+ | DCBZ area stack is left in the cache since there is no way to \r
+ | invalidate data cache. This area will be written to memory at some\r
+ | point. Main memory should be functional at this point.\r
+ +--------------------------------------------------------------------*/\r
+ b .init_data\r
+ /*--------------------------------------------------------------------+\r
+ | CPU1 will spin waiting for the CPU0 to initialize the system. CPU1\r
+ | then will check if the image for CPU1 has been loaded. If the image\r
+ | for CPU1 has been loaded CPU1 will jump to that image. If the image\r
+ | for CPU1 has not been loaded CPU1 will spin waiting for the image to\r
+ | be loaded.\r
+ +--------------------------------------------------------------------*/\r
+..cpu1: LOAD_64BIT_VAL(r31,NB_HW_INIT_STATE_ASM)\r
+ lwz r30,0x0000(r31) \r
+ cmpi cr0,1,r30,0x0000\r
+ beq ..cpu1\r
+ /*--------------------------------------------------------------------+\r
+ | Jump to SDRAM (cachable storage) and wait there.\r
+ +--------------------------------------------------------------------*/\r
+ sync\r
+ ba ..loada\r
+ /*--------------------------------------------------------------------+\r
+ | Wait for image valid indicator.\r
+ +--------------------------------------------------------------------*/\r
+..loada:LOAD_64BIT_VAL(r31,CPU1_DATA_STRUCT_ADDR)\r
+ ld r3,CPU1_DATA_STRUCT_VALID_OFF(r31)\r
+ cmpi cr0,1,r3,0x0000\r
+ beq ..spin2\r
+ ld r3,CPU1_DATA_STRUCT_SRR0_OFF(r31)\r
+ mtspr SPR_SRR0,r3\r
+ ld r4,CPU1_DATA_STRUCT_SRR1_OFF(r31)\r
+ mtspr SPR_SRR1,r4\r
+ ld r3,CPU1_DATA_STRUCT_R3_OFF(r31)\r
+ isync\r
+ rfid\r
+..spin2:mfspr r29,tblr\r
+ LOAD_64BIT_VAL(r31,CPU1_DELAY)\r
+..spin3:mfspr r30,tblr\r
+ subf r30,r29,r30\r
+ cmp cr0,1,r30,r31\r
+ blt ..spin3\r
+ b ..loada\r
+ function_epilog(init_chip)\r
+\r
+\r
+/******** init_data.s ***************/\r
+/*----------------------------------------------------------------------------+\r
+| Init_data.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(init_data)\r
+ /*--------------------------------------------------------------------+\r
+ | Check if we are running from FLASH. If running from FLASH copy 1M\r
+ | of FLASH to SDRAM.\r
+ +--------------------------------------------------------------------*/\r
+ bl ..next\r
+..next: mflr r3\r
+ LOAD_64BIT_VAL(r4,BOOT_BASE_AS)\r
+ cmpld cr0,r3,r4\r
+ blt ..sk_c\r
+ /*--------------------------------------------------------------------+\r
+ | Perform the copy operation. This copies data starting from SPR_HIOR\r
+ | for number of bytes queal to __edata - __stext.\r
+ +--------------------------------------------------------------------*/\r
+ LOAD_64BIT_VAL(r6,__stext)\r
+ addi r3,r6,-8\r
+ mfspr r4,SPR_HIOR\r
+ addi r4,r4,-8\r
+ LOAD_64BIT_VAL(r5,__edata);\r
+ sub r5,r5,r6\r
+ rlwinm r5,r5,29,3,31\r
+ addi r5,r5,0x0001\r
+ mtctr r5\r
+..again1:ldu r6,0x0008(r4)\r
+ stdu r6,0x0008(r3)\r
+ bdnz ..again1\r
+ /*--------------------------------------------------------------------+\r
+ | Get the size of BSS into r6.\r
+ +--------------------------------------------------------------------*/ \r
+..sk_c: LOAD_64BIT_VAL(r4,__sbss)\r
+ LOAD_64BIT_VAL(r5,__ebss)\r
+ sub r6,r5,r4\r
+ /*--------------------------------------------------------------------+\r
+ | Clear BSS.\r
+ +--------------------------------------------------------------------*/\r
+ addi r8,r4,-1\r
+ mtspr ctr,r6\r
+ addi r9,r0,0x0000\r
+..bag: stbu r9,0x0001(r8)\r
+ bdnz ..bag\r
+ /*--------------------------------------------------------------------+\r
+ | Synchronize.\r
+ +--------------------------------------------------------------------*/\r
+ sync\r
+ ba .init_cenv\r
+ function_epilog(init_data)\r
+\r
+\r
+/******** init_cenv.s ***************/\r
+/*----------------------------------------------------------------------------+\r
+| TOC entry for __initial_stack.\r
++----------------------------------------------------------------------------*/\r
+TOC_ENTRY(.LC0,__initial_stack)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Initial stack.\r
++----------------------------------------------------------------------------*/\r
+ data_prolog(__initial_stack)\r
+ .space MY_MAIN_STACK_SIZE\r
+ data_epilog(__initial_stack)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Init_cenv.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(init_cenv)\r
+ /*--------------------------------------------------------------------+\r
+ | Load TOC. Can't use ld since the TOC value might not be aligned on\r
+ | double word boundary. R2 is loaded for the first time here when \r
+ | loaded by PIBS (second time when originally running from FLASH). \r
+ +--------------------------------------------------------------------*/\r
+ bl ..ot\r
+ .quad .TOC.@tocbase\r
+..ot: mflr r3\r
+ lwz r2,0x0000(r3)\r
+ lwz r3,0x0004(r3)\r
+ rldicr r2,r2,32,31\r
+ or r2,r2,r3\r
+ /*--------------------------------------------------------------------+\r
+ | Get the address and size of the stack.\r
+ +--------------------------------------------------------------------*/\r
+ GETSYMADDR(r3,__initial_stack,.LC0)\r
+ addis r4,r0,MY_MAIN_STACK_SIZE@h\r
+ ori r4,r4,MY_MAIN_STACK_SIZE@l\r
+ /*--------------------------------------------------------------------+\r
+ | Setup the stack, stack bust be quadword (128-bit) aligned.\r
+ +--------------------------------------------------------------------*/\r
+ add r1,r3,r4\r
+ addi r1,r1,-stack_frame_min\r
+ rldicr r1,r1,0,59\r
+ addi r5,r0,0x0000\r
+ std r5,stack_frame_bc(r1)\r
+ std r5,stack_frame_lr(r1)\r
+ /*--------------------------------------------------------------------+\r
+ | Call the "C" function.\r
+ +--------------------------------------------------------------------*/\r
+// b .my_main\r
+ b .ppc_main\r
+..spin: b ..spin\r
+ function_epilog(init_cenv)\r
+\r
--- /dev/null
+\r
+#include <ppc970.h>\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Init_excp. The external interrupt vector should never be called before\r
+| io_init() is called so it can be removed from this file.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(init_excp)\r
+ .space 0x100\r
+ b .init_core /* 0100 */\r
+ function_epilog(init_excp)\r
--- /dev/null
+\r
+#include "ppc970.h"\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMflr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMflr)\r
+ mflr r3\r
+ blr\r
+ function_epilog(ppcMflr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Inbyte\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(inbyte)\r
+ lbz r3,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(inbyte)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Outbyte\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(outbyte)\r
+ stb r4,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(outbyte)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Inhalf\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(inhalf)\r
+ lhz r3,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(inhalf)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Outhalf\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(outhalf)\r
+ sth r4,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(outhalf)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Inhalf_brx (Load halfword byte-reverse indexed)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(inhalf_brx)\r
+ lhbrx r3,r0,r3\r
+ sync\r
+ blr\r
+ function_epilog(inhalf_brx)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Outhalf_brx (Store halfword byte-reverse indexed)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(outhalf_brx)\r
+ sthbrx r4,r0,r3\r
+ sync\r
+ blr\r
+ function_epilog(outhalf_brx)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Inword\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(inword)\r
+ ld r3,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(inword)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Outword\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(outword)\r
+ std r4,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(outword)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Inint\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(inint)\r
+ lwz r3,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(inint)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Outint\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(outint)\r
+ stw r4,0x0000(r3)\r
+ sync\r
+ blr\r
+ function_epilog(outint)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Inint_brx (Load word byte-reverse indexed)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(inint_brx)\r
+ lwbrx r3,r0,r3\r
+ sync\r
+ blr\r
+ function_epilog(inint_brx)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Outint_brx (Store word byte-reverse indexed)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(outint_brx)\r
+ stwbrx r4,r0,r3\r
+ sync\r
+ blr\r
+ function_epilog(outint_brx)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcDflush. Assume addresses 0-2MB are cachable. Do a series of loads to \r
+| fill the L2 using a memory range twice as large as the L2 in case a line\r
+| between 0-2MB is dirty in the L2 to start.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcDflush)\r
+ mfmsr r9\r
+ rlwinm r8,r9,0,17,15\r
+ mtmsrd r8,1\r
+ isync\r
+ /*--------------------------------------------------------------------+\r
+ | Back to the initial start address.\r
+ +--------------------------------------------------------------------*/\r
+ addi r3,r0,0x0000\r
+ addis r4,r0,0x0000\r
+ /*--------------------------------------------------------------------+\r
+ | 2x number of blocks in 512KB L2 cache.\r
+ +--------------------------------------------------------------------*/\r
+ ori r4,r4,0x2000\r
+ mtctr r4\r
+..fl: lwz r6,0x0(r3)\r
+ addi r3,r3,128\r
+ bdnz ..fl\r
+ sync\r
+ /*--------------------------------------------------------------------+\r
+ | Now flush the last lines.\r
+ +--------------------------------------------------------------------*/\r
+ addis r3,r0,0x0008\r
+ ori r4,r4,0x1000\r
+ mtctr r4\r
+..fl1: dcbf r0,r3\r
+ addi r3,r3,123\r
+ bdnz ..fl1\r
+ /*--------------------------------------------------------------------+\r
+ | No dirty lines should exist in the L2 at this point.\r
+ +--------------------------------------------------------------------*/\r
+ mtmsrd r9,1\r
+ isync\r
+ blr\r
+ function_epilog(ppcDflush)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcDcbz_area (dcbz: data cache block set to zero). Although the cache line\r
+| in L2 is 128 bytes the dcbz instruction will only zero 32 bytes when HID5\r
+| bit 56 is set to 0. This function will work with HID5 bit 56 set to 0 or 1.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcDcbz_area)\r
+ rlwinm. r5,r4,0,27,31\r
+ rlwinm r5,r4,27,5,31\r
+ beq ..d_ran\r
+ addi r5,r5,0x0001\r
+..d_ran:mtctr r5\r
+..d_ag: dcbz r0,r3\r
+ addi r3,r3,32\r
+ bdnz ..d_ag\r
+ blr\r
+ function_epilog(ppcDcbz_area)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcTlbsync (tlbsync: TLB Synchronize)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcTlbsync)\r
+ tlbsync\r
+ blr\r
+ function_epilog(ppcTlbsync)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcTlbie (tlbie: TLB Invalidate Entry)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcTlbie)\r
+ cmpi cr0,1,r4,0x0000\r
+ bne ..tlp\r
+ tlbie r3,0\r
+ blr\r
+..tlp: tlbie r3,1\r
+ blr\r
+ function_epilog(ppcTlbie)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcAbend\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcAbend)\r
+ .long 0x00000000\r
+ function_epilog(ppcAbend)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcAndMsr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcAndMsr)\r
+ mfmsr r6\r
+ and r7,r6,r3\r
+ mtmsrd r7,0\r
+ isync\r
+ ori r3,r6,0x000\r
+ blr\r
+ function_epilog(ppcAndMsr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcCntlzw (cntlzw: count leading zeros word)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcCntlzw)\r
+ cntlzw r3,r3\r
+ blr\r
+ function_epilog(ppcCntlzw)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcCntlzd (cntlzd: count leading zeros double word)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcCntlzd)\r
+ cntlzd r3,r3\r
+ blr\r
+ function_epilog(ppcCntlzd)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcDcbf (dcbf: data cache block flush)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcDcbf)\r
+ dcbf r0,r3\r
+ blr\r
+ function_epilog(ppcDcbf)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcDcbst (dcbst: data cache block touch for store)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcDcbst)\r
+ dcbst r0,r3\r
+ blr\r
+ function_epilog(ppcDcbst)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcDcbz (dcbz: data cache block set to zero)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcDcbz)\r
+ dcbz r0,r3\r
+ blr\r
+ function_epilog(ppcDcbz)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcHalt (3 nop instructions + branch)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcHalt)\r
+ ori r0,r0,0x0000 \r
+ b .ppcHalt\r
+ function_epilog(ppcHalt)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcIcbi (icbi: instruction cache block invalidate)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcIcbi)\r
+ icbi r0,r3\r
+ blr\r
+ function_epilog(ppcIcbi)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcIsync (isync: instruction synchronize)\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcIsync)\r
+ isync\r
+ blr\r
+ function_epilog(ppcIsync)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMfgpr1\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMfgpr1)\r
+ addi r3,r1,0x0000\r
+ blr\r
+ function_epilog(ppcMfgpr1)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMfgpr2\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMfgpr2)\r
+ addi r3,r2,0x0000\r
+ blr\r
+ function_epilog(ppcMfgpr2)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMtmsr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMtmsr)\r
+ mtmsrd r3,0\r
+ isync\r
+ blr\r
+ function_epilog(ppcMtmsr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMfmsr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMfmsr)\r
+ mfmsr r3\r
+ blr\r
+ function_epilog(ppcMfmsr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcOrMsr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcOrMsr)\r
+ mfmsr r6\r
+ or r7,r6,r3\r
+ mtmsrd r7,0\r
+ isync\r
+ ori r3,r6,0x000\r
+ blr\r
+ function_epilog(ppcOrMsr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcSync\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcSync)\r
+ sync\r
+ blr\r
+ function_epilog(ppcSync)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcEieio\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcEieio)\r
+ eieio\r
+ blr\r
+ function_epilog(ppcEieio)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMthid0\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMthid0)\r
+ sync\r
+ mtspr SPR_HID0,r3\r
+ mfspr r3,SPR_HID0\r
+ mfspr r3,SPR_HID0\r
+ mfspr r3,SPR_HID0\r
+ mfspr r3,SPR_HID0\r
+ mfspr r3,SPR_HID0\r
+ mfspr r3,SPR_HID0\r
+ blr\r
+ function_epilog(ppcMthid0)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMthid1\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMthid1)\r
+ mtspr SPR_HID1,r3\r
+ mtspr SPR_HID1,r3\r
+ isync\r
+ blr\r
+ function_epilog(ppcMthid1)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMthid4\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMthid4)\r
+ sync\r
+ mtspr SPR_HID4,r3\r
+ isync\r
+ blr\r
+ function_epilog(ppcMthid4)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMthid5\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMthid5)\r
+ mtspr SPR_HID5,r3\r
+ blr\r
+ function_epilog(ppcMthid5)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMftb\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMftb)\r
+ mfspr r6,tblr\r
+ std r6,0x0000(r3)\r
+ blr\r
+ function_epilog(ppcMftb)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMttb\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMttb)\r
+ mfmsr r7\r
+ lwz r6,0x0000(r3)\r
+ rlwinm r8,r7,0,17,15\r
+ mtmsrd r8,1\r
+ ori r5,r6,0x0000\r
+ sradi r6,r6,32\r
+ addi r4,r0,0x0000\r
+ rldicl r6,r6,0,32\r
+ mtspr SPR_TBL_WRITE,r4\r
+ mtspr SPR_TBU_WRITE,r6\r
+ mtspr SPR_TBL_WRITE,r5\r
+ mtmsrd r7,1\r
+ blr\r
+ function_epilog(ppcMttb)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMtspr_any\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMtspr_any)\r
+ rlwinm r3,r3,3,19,29\r
+ addi r3,r3,0x0010\r
+ mflr r6\r
+ bl ..sp_get_lr\r
+..sp_get_lr:\r
+ mflr r5\r
+ add r5,r5,r3\r
+ mtlr r5\r
+ blr\r
+ mtspr 0x000,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x001,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x002,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x003,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x004,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x005,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x006,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x007,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x008,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x009,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x00a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x00b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x00c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x00d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x00e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x00f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x010,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x011,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x012,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x013,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x014,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x015,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x016,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x017,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x018,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x019,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x01a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x01b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x01c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x01d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x01e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x01f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x020,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x021,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x022,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x023,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x024,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x025,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x026,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x027,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x028,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x029,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x02a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x02b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x02c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x02d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x02e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x02f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x030,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x031,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x032,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x033,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x034,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x035,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x036,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x037,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x038,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x039,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x03a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x03b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x03c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x03d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x03e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x03f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x040,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x041,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x042,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x043,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x044,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x045,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x046,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x047,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x048,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x049,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x04a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x04b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x04c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x04d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x04e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x04f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x050,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x051,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x052,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x053,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x054,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x055,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x056,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x057,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x058,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x059,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x05a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x05b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x05c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x05d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x05e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x05f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x060,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x061,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x062,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x063,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x064,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x065,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x066,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x067,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x068,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x069,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x06a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x06b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x06c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x06d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x06e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x06f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x070,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x071,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x072,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x073,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x074,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x075,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x076,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x077,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x078,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x079,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x07a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x07b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x07c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x07d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x07e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x07f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x080,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x081,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x082,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x083,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x084,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x085,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x086,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x087,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x088,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x089,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x08a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x08b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x08c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x08d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x08e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x08f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x090,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x091,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x092,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x093,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x094,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x095,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x096,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x097,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x098,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x099,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x09a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x09b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x09c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x09d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x09e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x09f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0a9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0aa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ab,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ac,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ad,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ae,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0af,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0b9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ba,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0bb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0bc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0bd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0be,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0bf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0c9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ca,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0cb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0cc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0cd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ce,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0cf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0d9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0da,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0db,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0dc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0dd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0de,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0df,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0e9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ea,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0eb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ec,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ed,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ee,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ef,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0f9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0fa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0fb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0fc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0fd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0fe,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x0ff,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x100,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x101,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x102,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x103,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x104,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x105,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x106,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x107,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x108,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x109,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x10a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x10b,r4\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x10e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x10f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x110,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x111,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x112,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x113,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x114,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x115,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x116,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x117,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x118,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x119,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x11a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x11b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x11c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x11d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x11e,r4\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x120,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x121,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x122,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x123,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x124,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x125,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x126,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x127,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x128,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x129,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x12a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x12b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x12c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x12d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x12e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x12f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x130,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x131,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x132,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x133,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x134,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x135,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x136,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x137,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x138,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x139,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x13a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x13b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x13c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x13d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x13e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x13f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x140,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x141,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x142,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x143,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x144,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x145,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x146,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x147,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x148,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x149,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x14a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x14b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x14c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x14d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x14e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x14f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x150,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x151,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x152,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x153,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x154,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x155,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x156,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x157,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x158,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x159,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x15a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x15b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x15c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x15d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x15e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x15f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x160,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x161,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x162,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x163,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x164,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x165,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x166,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x167,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x168,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x169,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x16a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x16b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x16c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x16d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x16e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x16f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x170,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x171,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x172,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x173,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x174,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x175,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x176,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x177,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x178,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x179,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x17a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x17b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x17c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x17d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x17e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x17f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x180,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x181,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x182,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x183,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x184,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x185,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x186,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x187,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x188,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x189,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x18a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x18b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x18c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x18d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x18e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x18f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x190,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x191,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x192,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x193,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x194,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x195,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x196,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x197,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x198,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x199,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x19a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x19b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x19c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x19d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x19e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x19f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1a9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1aa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ab,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ac,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ad,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ae,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1af,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1b9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ba,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1bb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1bc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1bd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1be,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1bf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1c9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ca,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1cb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1cc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1cd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ce,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1cf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1d9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1da,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1db,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1dc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1dd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1de,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1df,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1e9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ea,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1eb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ec,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ed,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ee,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ef,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1f9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1fa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1fb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1fc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1fd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1fe,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x1ff,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x200,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x201,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x202,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x203,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x204,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x205,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x206,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x207,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x208,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x209,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x20a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x20b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x20c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x20d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x20e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x20f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x210,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x211,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x212,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x213,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x214,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x215,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x216,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x217,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x218,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x219,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x21a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x21b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x21c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x21d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x21e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x21f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x220,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x221,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x222,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x223,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x224,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x225,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x226,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x227,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x228,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x229,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x22a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x22b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x22c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x22d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x22e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x22f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x230,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x231,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x232,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x233,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x234,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x235,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x236,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x237,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x238,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x239,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x23a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x23b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x23c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x23d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x23e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x23f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x240,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x241,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x242,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x243,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x244,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x245,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x246,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x247,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x248,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x249,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x24a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x24b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x24c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x24d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x24e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x24f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x250,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x251,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x252,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x253,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x254,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x255,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x256,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x257,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x258,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x259,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x25a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x25b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x25c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x25d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x25e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x25f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x260,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x261,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x262,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x263,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x264,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x265,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x266,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x267,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x268,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x269,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x26a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x26b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x26c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x26d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x26e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x26f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x270,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x271,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x272,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x273,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x274,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x275,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x276,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x277,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x278,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x279,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x27a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x27b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x27c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x27d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x27e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x27f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x280,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x281,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x282,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x283,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x284,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x285,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x286,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x287,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x288,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x289,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x28a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x28b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x28c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x28d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x28e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x28f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x290,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x291,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x292,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x293,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x294,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x295,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x296,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x297,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x298,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x299,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x29a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x29b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x29c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x29d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x29e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x29f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2a9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2aa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ab,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ac,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ad,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ae,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2af,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2b9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ba,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2bb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2bc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2bd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2be,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2bf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2c9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ca,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2cb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2cc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2cd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ce,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2cf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2d9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2da,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2db,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2dc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2dd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2de,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2df,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2e9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ea,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2eb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ec,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ed,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ee,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ef,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2f9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2fa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2fb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2fc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2fd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2fe,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x2ff,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x300,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x301,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x302,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x303,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x304,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x305,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x306,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x307,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x308,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x309,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x30a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x30b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x30c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x30d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x30e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x30f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x310,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x311,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x312,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x313,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x314,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x315,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x316,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x317,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x318,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x319,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x31a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x31b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x31c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x31d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x31e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x31f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x320,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x321,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x322,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x323,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x324,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x325,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x326,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x327,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x328,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x329,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x32a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x32b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x32c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x32d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x32e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x32f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x330,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x331,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x332,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x333,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x334,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x335,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x336,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x337,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x338,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x339,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x33a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x33b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x33c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x33d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x33e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x33f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x340,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x341,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x342,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x343,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x344,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x345,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x346,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x347,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x348,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x349,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x34a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x34b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x34c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x34d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x34e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x34f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x350,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x351,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x352,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x353,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x354,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x355,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x356,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x357,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x358,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x359,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x35a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x35b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x35c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x35d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x35e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x35f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x360,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x361,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x362,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x363,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x364,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x365,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x366,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x367,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x368,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x369,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x36a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x36b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x36c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x36d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x36e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x36f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x370,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x371,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x372,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x373,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x374,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x375,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x376,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x377,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x378,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x379,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x37a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x37b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x37c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x37d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x37e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x37f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x380,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x381,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x382,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x383,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x384,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x385,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x386,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x387,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x388,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x389,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x38a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x38b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x38c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x38d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x38e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x38f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x390,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x391,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x392,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x393,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x394,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x395,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x396,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x397,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x398,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x399,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x39a,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x39b,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x39c,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x39d,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x39e,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x39f,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3a9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3aa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ab,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ac,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ad,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ae,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3af,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3b9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ba,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3bb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3bc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3bd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3be,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3bf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3c9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ca,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3cb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3cc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3cd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ce,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3cf,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3d9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3da,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3db,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3dc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3dd,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3de,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3df,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e0,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e1,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e3,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e4,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e5,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e6,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3e9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ea,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3eb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ec,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ed,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ee,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3ef,r4\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3f2,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3f3,r4\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3f5,r4\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3f7,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3f8,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3f9,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3fa,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3fb,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3fc,r4\r
+ b ..ppcMtspr_any_end\r
+ mtspr 0x3fd,r4\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMtspr_any_end\r
+..ppcMtspr_any_end:\r
+ mtlr r6\r
+ blr\r
+ function_epilog(ppcMtspr_any)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMfspr_any\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMfspr_any)\r
+ rlwinm r3,r3,3,19,29\r
+ addi r3,r3,0x0010\r
+ mflr r6\r
+ bl ..sp_gett_lr\r
+..sp_gett_lr:\r
+ mflr r5\r
+ add r5,r5,r3\r
+ mtlr r5\r
+ blr\r
+ mfspr r3,0x000\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x001\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x002\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x003\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x004\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x005\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x006\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x007\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x008\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x009\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x00a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x00b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x00c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x00d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x00e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x00f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x010\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x011\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x012\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x013\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x014\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x015\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x016\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x017\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x018\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x019\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x01a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x01b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x01c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x01d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x01e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x01f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x020\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x021\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x022\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x023\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x024\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x025\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x026\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x027\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x028\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x029\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x02a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x02b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x02c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x02d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x02e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x02f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x030\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x031\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x032\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x033\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x034\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x035\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x036\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x037\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x038\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x039\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x03a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x03b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x03c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x03d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x03e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x03f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x040\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x041\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x042\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x043\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x044\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x045\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x046\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x047\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x048\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x049\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x04a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x04b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x04c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x04d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x04e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x04f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x050\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x051\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x052\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x053\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x054\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x055\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x056\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x057\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x058\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x059\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x05a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x05b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x05c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x05d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x05e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x05f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x060\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x061\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x062\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x063\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x064\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x065\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x066\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x067\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x068\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x069\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x06a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x06b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x06c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x06d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x06e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x06f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x070\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x071\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x072\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x073\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x074\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x075\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x076\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x077\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x078\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x079\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x07a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x07b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x07c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x07d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x07e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x07f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x080\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x081\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x082\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x083\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x084\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x085\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x086\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x087\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x088\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x089\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x08a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x08b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x08c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x08d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x08e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x08f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x090\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x091\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x092\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x093\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x094\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x095\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x096\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x097\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x098\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x099\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x09a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x09b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x09c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x09d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x09e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x09f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0a9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0aa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ab\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ac\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ad\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ae\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0af\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0b9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ba\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0bb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0bc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0bd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0be\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0bf\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0c9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ca\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0cb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0cc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0cd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ce\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0cf\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0d9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0da\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0db\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0dc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0dd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0de\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0df\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0e9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ea\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0eb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ec\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ed\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ee\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ef\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0f9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0fa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0fb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0fc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0fd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0fe\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x0ff\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x100\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x101\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x102\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x103\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x104\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x105\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x106\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x107\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x108\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x109\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x10a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x10b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x10c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x10d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x10e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x10f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x110\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x111\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x112\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x113\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x114\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x115\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x116\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x117\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x118\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x119\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x11a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x11b\r
+ b ..ppcMfspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMfspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x11e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x11f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x120\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x121\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x122\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x123\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x124\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x125\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x126\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x127\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x128\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x129\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x12a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x12b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x12c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x12d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x12e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x12f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x130\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x131\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x132\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x133\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x134\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x135\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x136\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x137\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x138\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x139\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x13a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x13b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x13c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x13d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x13e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x13f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x140\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x141\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x142\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x143\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x144\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x145\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x146\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x147\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x148\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x149\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x14a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x14b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x14c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x14d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x14e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x14f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x150\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x151\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x152\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x153\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x154\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x155\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x156\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x157\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x158\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x159\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x15a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x15b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x15c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x15d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x15e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x15f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x160\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x161\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x162\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x163\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x164\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x165\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x166\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x167\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x168\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x169\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x16a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x16b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x16c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x16d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x16e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x16f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x170\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x171\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x172\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x173\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x174\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x175\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x176\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x177\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x178\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x179\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x17a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x17b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x17c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x17d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x17e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x17f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x180\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x181\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x182\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x183\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x184\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x185\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x186\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x187\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x188\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x189\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x18a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x18b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x18c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x18d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x18e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x18f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x190\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x191\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x192\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x193\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x194\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x195\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x196\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x197\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x198\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x199\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x19a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x19b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x19c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x19d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x19e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x19f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1a9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1aa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ab\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ac\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ad\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ae\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1af\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1b9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ba\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1bb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1bc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1bd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1be\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1bf\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1c9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ca\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1cb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1cc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1cd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ce\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1cf\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1d9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1da\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1db\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1dc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1dd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1de\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1df\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1e9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ea\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1eb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ec\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ed\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ee\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ef\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1f9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1fa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1fb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1fc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1fd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1fe\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x1ff\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x200\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x201\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x202\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x203\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x204\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x205\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x206\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x207\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x208\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x209\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x20a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x20b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x20c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x20d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x20e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x20f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x210\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x211\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x212\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x213\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x214\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x215\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x216\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x217\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x218\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x219\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x21a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x21b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x21c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x21d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x21e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x21f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x220\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x221\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x222\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x223\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x224\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x225\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x226\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x227\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x228\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x229\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x22a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x22b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x22c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x22d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x22e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x22f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x230\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x231\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x232\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x233\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x234\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x235\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x236\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x237\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x238\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x239\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x23a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x23b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x23c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x23d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x23e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x23f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x240\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x241\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x242\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x243\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x244\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x245\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x246\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x247\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x248\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x249\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x24a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x24b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x24c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x24d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x24e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x24f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x250\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x251\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x252\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x253\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x254\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x255\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x256\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x257\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x258\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x259\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x25a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x25b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x25c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x25d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x25e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x25f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x260\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x261\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x262\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x263\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x264\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x265\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x266\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x267\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x268\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x269\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x26a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x26b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x26c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x26d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x26e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x26f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x270\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x271\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x272\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x273\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x274\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x275\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x276\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x277\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x278\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x279\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x27a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x27b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x27c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x27d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x27e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x27f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x280\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x281\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x282\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x283\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x284\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x285\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x286\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x287\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x288\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x289\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x28a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x28b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x28c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x28d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x28e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x28f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x290\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x291\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x292\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x293\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x294\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x295\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x296\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x297\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x298\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x299\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x29a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x29b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x29c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x29d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x29e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x29f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2a9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2aa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ab\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ac\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ad\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ae\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2af\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2b9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ba\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2bb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2bc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2bd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2be\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2bf\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2c9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ca\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2cb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2cc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2cd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ce\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2cf\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2d9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2da\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2db\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2dc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2dd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2de\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2df\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2e9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ea\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2eb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ec\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ed\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ee\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ef\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2f9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2fa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2fb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2fc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2fd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2fe\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x2ff\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x300\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x301\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x302\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x303\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x304\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x305\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x306\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x307\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x308\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x309\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x30a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x30b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x30c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x30d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x30e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x30f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x310\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x311\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x312\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x313\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x314\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x315\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x316\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x317\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x318\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x319\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x31a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x31b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x31c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x31d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x31e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x31f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x320\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x321\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x322\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x323\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x324\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x325\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x326\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x327\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x328\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x329\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x32a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x32b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x32c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x32d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x32e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x32f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x330\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x331\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x332\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x333\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x334\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x335\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x336\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x337\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x338\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x339\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x33a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x33b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x33c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x33d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x33e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x33f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x340\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x341\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x342\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x343\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x344\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x345\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x346\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x347\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x348\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x349\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x34a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x34b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x34c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x34d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x34e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x34f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x350\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x351\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x352\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x353\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x354\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x355\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x356\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x357\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x358\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x359\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x35a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x35b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x35c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x35d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x35e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x35f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x360\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x361\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x362\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x363\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x364\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x365\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x366\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x367\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x368\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x369\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x36a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x36b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x36c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x36d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x36e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x36f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x370\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x371\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x372\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x373\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x374\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x375\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x376\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x377\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x378\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x379\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x37a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x37b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x37c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x37d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x37e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x37f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x380\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x381\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x382\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x383\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x384\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x385\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x386\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x387\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x388\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x389\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x38a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x38b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x38c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x38d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x38e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x38f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x390\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x391\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x392\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x393\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x394\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x395\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x396\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x397\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x398\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x399\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x39a\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x39b\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x39c\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x39d\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x39e\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x39f\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3a9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3aa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ab\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ac\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ad\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ae\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3af\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3b9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ba\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3bb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3bc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3bd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3be\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3bf\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3c9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ca\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3cb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3cc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3cd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ce\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3cf\r
+ b ..ppcMfspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMfspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMfspr_any_end\r
+ addi r3,r0,0x0000\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3d3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3d4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3d5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3d6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3d7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3d8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3d9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3da\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3db\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3dc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3dd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3de\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3df\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3e9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ea\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3eb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ec\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ed\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ee\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ef\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f0\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f1\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f2\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f3\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f4\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f5\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f6\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f7\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f8\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3f9\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3fa\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3fb\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3fc\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3fd\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3fe\r
+ b ..ppcMfspr_any_end\r
+ mfspr r3,0x3ff\r
+ b ..ppcMfspr_any_end\r
+..ppcMfspr_any_end:\r
+ mtlr r6\r
+ blr\r
+ function_epilog(ppcMfspr_any)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcCachelinesize\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcCachelinesize)\r
+ addi r3,r0,0x0080\r
+ blr\r
+ function_epilog(ppcCachelinesize)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcProcid\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcProcid)\r
+ addi r3,r0,0x03CA\r
+ blr\r
+ function_epilog(ppcProcid)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMtmmucr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMtmmucr)\r
+ blr\r
+ function_epilog(ppcMtmmucr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMttlb1\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMttlb1)\r
+ blr\r
+ function_epilog(ppcMttlb1)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMttlb2\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMttlb2)\r
+ blr\r
+ function_epilog(ppcMttlb2)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMttlb3\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMttlb3)\r
+ blr\r
+ function_epilog(ppcMttlb3)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMftlb1\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMftlb1)\r
+ addis r3,r0,0xdead\r
+ ori r3,r3,0xbeef\r
+ blr\r
+ function_epilog(ppcMftlb1)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMftlb2\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMftlb2)\r
+ addis r3,r0,0xdead\r
+ ori r3,r3,0xbeef\r
+ blr\r
+ function_epilog(ppcMftlb2)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMftlb3\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMftlb3)\r
+ addis r3,r0,0xdead\r
+ ori r3,r3,0xbeef\r
+ blr\r
+ function_epilog(ppcMftlb3)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMfmmucr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMfmmucr)\r
+ addis r3,r0,0xdead\r
+ ori r3,r3,0xbeef\r
+ blr\r
+ function_epilog(ppcMfmmucr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMfdcr_any\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMfdcr_any)\r
+ addis r3,r0,0xdead\r
+ ori r3,r3,0xbeef\r
+ blr\r
+ function_epilog(ppcMfdcr_any)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMtdcr_any\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMtdcr_any)\r
+ blr\r
+ function_epilog(ppcMtdcr_any)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcIstrap.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcIstrap)\r
+ mfspr r3,srr1\r
+ rlwinm. r3,r3,0,13,15\r
+ bne ..is_trap\r
+ addi r3,r0,0x0000\r
+ b ..is_return\r
+..is_trap:\r
+ addi r3,r0,0x0001\r
+..is_return:\r
+ blr\r
+ function_epilog(ppcIstrap)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| P_ptegg. r3=large page inidicator, r4=ea, r5 = sdr1, r6 = vsid.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(p_ptegg)\r
+ cmpi cr0,1,r3,0x0000\r
+ bne ..lp\r
+ addi r3,r0,12\r
+ addi r8,r0,0x0001\r
+ rlwinm r8,r8,16,0,31\r
+ addi r8,r8,-1\r
+ b ..ppast\r
+..lp: addi r3,r0,24\r
+ addi r8,r0,0x0001\r
+ rlwinm r8,r8,4,0,31\r
+ addi r8,r8,-1\r
+ /*--------------------------------------------------------------------+\r
+ | Only lower 39 bits of VSID are used in hash function.\r
+ +--------------------------------------------------------------------*/\r
+..ppast:rldicl r6,r6,0,25\r
+ /*--------------------------------------------------------------------+\r
+ | Discard page offset in effective address, only bits specified in \r
+ | the mask (r8) are used.\r
+ +--------------------------------------------------------------------*/\r
+ srd r4,r4,r3\r
+ and r4,r4,r8\r
+ /*--------------------------------------------------------------------+\r
+ | Perform hash function.\r
+ +--------------------------------------------------------------------*/\r
+ xor r6,r6,r4\r
+ /*--------------------------------------------------------------------+\r
+ | 11 lowest bits from hash function are used directly.\r
+ +--------------------------------------------------------------------*/\r
+ rlwinm r3,r6,7,14,24\r
+ /*--------------------------------------------------------------------+\r
+ | Shift output of the hash function by 11 bits.\r
+ +--------------------------------------------------------------------*/\r
+ sradi r4,r6,11\r
+ /*--------------------------------------------------------------------+\r
+ | Calculate mask from sdr1.htabsize and AND it with upper 28 bits \r
+ | of the hash function result.\r
+ +--------------------------------------------------------------------*/\r
+ rldicl r7,r5,0,59\r
+ addi r8,r0,0x0001\r
+ slw r8,r8,r7\r
+ addi r8,r8,-1\r
+ and r8,r8,r4\r
+ /*--------------------------------------------------------------------+\r
+ | Or in the 28+ 16 bits of the sdr1.htaborg.\r
+ +--------------------------------------------------------------------*/\r
+ rldicl r5,r5,0,2\r
+ addi r4,r0,0x0012\r
+ srd r5,r5,r4\r
+ or r4,r5,r8\r
+ rldicr r4,r4,18,46\r
+ or r3,r3,r4\r
+ blr\r
+ function_epilog(p_ptegg)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| S_ptegg. r3=large page inidicator, r4=ea, r5 = sdr1, r6 = vsid.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(s_ptegg)\r
+ cmpi cr0,1,r3,0x0000\r
+ bne ..lps\r
+ addi r3,r0,12\r
+ addi r8,r0,0x0001\r
+ rlwinm r8,r8,16,0,31\r
+ addi r8,r8,-1\r
+ b ..spast\r
+..lps: addi r3,r0,24\r
+ addi r8,r0,0x0001\r
+ rlwinm r8,r8,4,0,31\r
+ addi r8,r8,-1\r
+ /*--------------------------------------------------------------------+\r
+ | Only lower 39 bits of VSID are used in hash function.\r
+ +--------------------------------------------------------------------*/\r
+..spast:rldicl r6,r6,0,25\r
+ /*--------------------------------------------------------------------+\r
+ | Discard page offset in effective address, only bits specified in \r
+ | the mask (r8) are used.\r
+ +--------------------------------------------------------------------*/\r
+ srd r4,r4,r3\r
+ and r4,r4,r8\r
+ /*--------------------------------------------------------------------+\r
+ | Perform hash function.\r
+ +--------------------------------------------------------------------*/\r
+ xor r6,r6,r4\r
+ nand r6,r6,r6\r
+ /*--------------------------------------------------------------------+\r
+ | 11 lowest bits from hash function are used directly.\r
+ +--------------------------------------------------------------------*/\r
+ rlwinm r3,r6,7,14,24\r
+ /*--------------------------------------------------------------------+\r
+ | Shift output of the hash function by 11 bits.\r
+ +--------------------------------------------------------------------*/\r
+ sradi r4,r6,11\r
+ /*--------------------------------------------------------------------+\r
+ | Calculate mask from sdr1.htabsize and AND it with upper 28 bits \r
+ | of the hash function result.\r
+ +--------------------------------------------------------------------*/\r
+ rldicl r7,r5,0,59\r
+ addi r8,r0,0x0001\r
+ slw r8,r8,r7\r
+ addi r8,r8,-1\r
+ and r8,r8,r4\r
+ /*--------------------------------------------------------------------+\r
+ | Or in the 28+ 16 bits of the sdr1.htaborg.\r
+ +--------------------------------------------------------------------*/\r
+ rldicl r5,r5,0,2\r
+ addi r4,r0,0x0012\r
+ srd r5,r5,r4\r
+ or r4,r5,r8\r
+ rldicr r4,r4,18,46\r
+ or r3,r3,r4\r
+ blr\r
+ function_epilog(s_ptegg)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcLwsync.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcLwsync)\r
+ sync 1\r
+ blr\r
+ function_epilog(ppcLwsync)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcPtesync.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcPtesync)\r
+ sync 2\r
+ blr\r
+ function_epilog(ppcPtesync)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcTestandset. r3=address, r4=value.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcTestandset)\r
+..again:lwarx r5,r0,r3\r
+ cmpwi cr0,r5,0x0000\r
+ bne ..again\r
+ stwcx. r4,r0,r3\r
+ bne ..again\r
+ blr\r
+ function_epilog(ppcTestandset)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcSlbmte.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcSlbmte)\r
+ slbmte r3,r4\r
+ blr\r
+ function_epilog(ppcSlbmte)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcSlbie.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcSlbie)\r
+ slbie r3\r
+ blr\r
+ function_epilog(ppcSlbie)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcSlbia.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcSlbia)\r
+ slbia\r
+ blr\r
+ function_epilog(ppcSlbia)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcSlbmfev.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcSlbmfev)\r
+ slbmfev r3,r3\r
+ blr\r
+ function_epilog(ppcSlbmfev)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcSlbmfee.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcSlbmfee)\r
+ slbmfee r3,r3\r
+ blr\r
+ function_epilog(ppcSlbmfee)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| ppcTlbiel.\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcTlbiel)\r
+ TLBIEL(r3)\r
+ blr\r
+ function_epilog(ppcTlbiel)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcStvx\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcStvx)\r
+ rlwinm r3,r3,3,19,29\r
+ addi r3,r3,0x0010\r
+ mflr r6\r
+ bl ..vr_sett_lr\r
+..vr_sett_lr:\r
+ mflr r5\r
+ add r5,r5,r3\r
+ mtlr r5\r
+ blr\r
+ stvx 0,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 1,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 2,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 3,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 4,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 5,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 6,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 7,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 8,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 9,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 10,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 11,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 12,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 13,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 14,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 15,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 16,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 17,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 18,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 19,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 20,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 21,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 22,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 23,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 24,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 25,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 26,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 27,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 28,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 29,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 30,r0,r4\r
+ b ..ppcStvx_any_end\r
+ stvx 31,r0,r4\r
+ b ..ppcStvx_any_end\r
+..ppcStvx_any_end:\r
+ mtlr r6\r
+ blr\r
+ function_epilog(ppcStvx)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcLvxl\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcLvxl)\r
+ rlwinm r3,r3,3,19,29\r
+ addi r3,r3,0x0010\r
+ mflr r6\r
+ bl ..vr_gett_lr\r
+..vr_gett_lr:\r
+ mflr r5\r
+ add r5,r5,r3\r
+ mtlr r5\r
+ blr\r
+ lvxl 0,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 1,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 2,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 3,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 4,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 5,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 6,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 7,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 8,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 9,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 10,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 11,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 12,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 13,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 14,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 15,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 16,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 17,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 18,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 19,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 20,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 21,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 22,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 23,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 24,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 25,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 26,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 27,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 28,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 29,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 30,r0,r4\r
+ b ..ppcLvxl_any_end\r
+ lvxl 31,r0,r4\r
+ b ..ppcLvxl_any_end\r
+..ppcLvxl_any_end:\r
+ mtlr r6\r
+ blr\r
+ function_epilog(ppcLvxl)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMfvscr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMfvscr)\r
+ mfvscr 0\r
+ blr\r
+ function_epilog(ppcMfvscr)\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PpcMtvscr\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(ppcMtvscr)\r
+ mtvscr 0\r
+ blr\r
+ function_epilog(ppcMtvscr)\r
## linuxBIOS C code runs at this location in RAM
default _RAMBASE=0x00100000
+default CROSS_COMPILE="powerpc-405-linux-gnu-"
### End Options.lb
end
##
## Early board initialization, called from ppc_main()
##
-#initobject init.c
+initobject init.c
+initobject mainboard.c
+initobject boardutil.c
+initobject timerspeed.S
arch ppc end
chip northbridge/ibm/cpc925
device pci_domain 0 on
- device pci 00.0 on end
- device pci 00.1 on end
- device pci 01.0 on end
- device pci 02.0 on
- chip southbridge/intel/pxhd # pxhd1
- device pci 00.0 on end
- device pci 00.1 on end
- device pci 00.2 on
- chip drivers/generic/generic
- device pci 04.0 on end
- device pci 04.1 on end
- end
+ chip southbridge/amd/amd8131
+ device pci 01.0 on #PCI-X Bridge
+ chip drivers/pci/onboard #intel GD31244 chip
+ device pci 01.0 on end #SATA controller
+ end
+ end
+ device pci 01.1 on end #APIC controller
+ device pci 02.0 on end #PCI-X Bridge
+ device pci 02.1 on end #APIC controller
+ device pci 03.0 on #PCI-X Bridge
+ chip drivers/pci/onboard #intel i82546EB chip
+ device pci 01.0 on end #GB Ethernet 0
+ device pci 01.1 on end #GB Ethernet 1
end
- device pci 00.3 on end
end
- end
- device pci 06.0 on end
- chip southbridge/intel/ich5r # ich5r
- device pci 1d.0 on end
- device pci 1d.1 on end
- device pci 1d.2 on end
- device pci 1d.3 off end
- device pci 1d.7 on end
- device pci 1e.0 on
+ device pci 03.1 on end #APIC controller
+ device pci 04.0 on end #PCI-X Bridge
+ device pci 04.1 on end #APIC controller
+ end #amd8131
+
+ chip southbridge/amd/amd8111
+ device pci 5.0 on #PCI Bridge
+ device pci 0.0 on end #USB Controller 0
+ device pci 0.1 on end #USB Controller 1
+ device pci 0.2 on end #USB Controller 2
+ device pci 1.0 on end #10/100 Ethernet Controller
chip drivers/ati/ragexl
- device pci 0c.0 on end
+ device pci 3.0 on end # ATI Rage Video Controller
end
end
- device pci 1f.0 on
- chip superio/NSC/pc87427
+ device pci 6.0 on #ISA Bridge/LPC Controller
+ chip superio/NSC/pc87427 #NSC Super IO chip
device pnp 2e.0 off end
device pnp 2e.2 on
-# io 0x60 = 0x2f8
-# irq 0x70 = 3
- io 0x60 = 0x3f8
+ io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on
-# io 0x60 = 0x3f8
-# irq 0x70 = 4
- io 0x60 = 0x2f8
+ io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.4 off end
device pnp 2e.5 off end
device pnp 2e.6 on
- io 0x60 = 0x60
- io 0x62 = 0x64
+ io 0x60 = 0x60
+ io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.7 off end
device pnp 2e.f on end
device pnp 2e.10 off end
device pnp 2e.14 off end
- end
- end
- device pci 1f.1 on end
- device pci 1f.2 off end
- device pci 1f.3 on end
- device pci 1f.5 off end
- device pci 1f.6 off end
- register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
- register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
- register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
- end
- end
- device apic_cluster 0 on
- chip cpu/ppc/ppc970 # cpu 0
- end
- chip cpu/ppc/ppc970 # cpu 1
- end
- end
-end
-
+ end #NSC Super IO chip
+ end #ISA Bridge/LPC
+ device pci 6.1 on end #IDE Controller
+ device pci 6.2 on end #SMBus Controller
+ device pci 6.3 on end #ACPI
+ device pci 6.5 off end #AC97 Audio
+ device pci 6.6 off end #MC97 Modem
+ end #amd8111
+ end #pci domain 0
+end #cpc925
-chip cpu/ppc/ppc4xx
- device pci_domain 0 on
- device pci 0.0 on end
- chip southbridge/winbond/w83c553
- device pci 9.0 on end # ISA bridge
- device pci 9.1 on end # IDE contoller
- end
- device pci e.0 on end
- end
+chip cpu/ppc/ppc970
end
##
--- /dev/null
+/*
+ * Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * Do very early board initialization:
+ *
+ * - Configure External Bus (EBC)
+ * - Setup Flash
+ * - Setup NVRTC
+ * - Setup Board Control and Status Registers (BCSR)
+ * - Enable UART0 for debugging
+ */
+
+#include "boardutil.h"
+#include "ppc970lib.h"
+#include "ppc970.h"
+#include "stddef.h"
+#include "string.h"
+
+/*----------------------------------------------------------------------------+
+| What_platform.
++----------------------------------------------------------------------------*/
+int what_platform()
+{
+
+ #ifdef PPC970FX_EVB_LITE
+ return(PLATFORM_EVB_LITE);
+ #endif
+ #ifdef PPC970FX_EVB
+ return(PLATFORM_EVB_FINAL);
+ #endif
+}
+
+/*----------------------------------------------------------------------------+
+| Get_system_info. Cannot access any global variables in this function.
++----------------------------------------------------------------------------*/
+void get_system_info(board_cfg_data_t *board_cfg)
+{
+
+ unsigned long msr;
+ unsigned long data;
+
+ if (board_cfg==NULL) {
+ (void)ppcHalt();
+ }
+ msr=ppcAndMsr((unsigned long)~MSR_EE);
+ board_cfg->usr_config_ver[0]='1';
+ board_cfg->usr_config_ver[1]='.';
+ board_cfg->usr_config_ver[2]='0';
+ board_cfg->usr_config_ver[3]='\0';
+ /*-------------------------------------------------------------------------+
+ | Read power status register.
+ +-------------------------------------------------------------------------*/
+ data=read_psr()&SCOM_PSR_FREQ_MASK;
+ if (data==SCOM_PSR_FREQ_FULL) {
+ board_cfg->freq_ratio=1;
+ } else if (data==SCOM_PSR_FREQ_HALF) {
+ board_cfg->freq_ratio=2;
+ } else if (data==SCOM_PSR_FREQ_QUARTER) {
+ board_cfg->freq_ratio=4;
+ } else {
+ board_cfg->freq_ratio=0;
+ }
+ /*-------------------------------------------------------------------------+
+ | Read information passed from service processor.
+ +-------------------------------------------------------------------------*/
+ if (get_ei_ratio(&data)==0) {
+ board_cfg->ei_ratio=data;
+ } else {
+ board_cfg->ei_ratio=0;
+ }
+ if (get_sys_clk(&data)==0) {
+ board_cfg->sys_freq=data;
+ } else {
+ board_cfg->sys_freq=0;
+ }
+ if (get_pll_mult(&data)==0) {
+ if (board_cfg->freq_ratio!=0) {
+ board_cfg->cpu_freq=(board_cfg->sys_freq* data)/ board_cfg->freq_ratio;
+ } else {
+ board_cfg->cpu_freq=0;
+ }
+ } else {
+ data=0;
+ board_cfg->cpu_freq=0;
+ }
+ /*-------------------------------------------------------------------------+
+ | On some boards we have to execute with timers running on internal clock.
+ +-------------------------------------------------------------------------*/
+ if ((ppcMfspr_any(SPR_HID0)&HID0_EXT_TB_EN)==0) {
+ board_cfg->tmr_freq=(board_cfg->sys_freq* data)/ PPC970_TB_RATIO;
+ } else {
+ board_cfg->tmr_freq=EXT_TIME_BASE_FREQ;
+ }
+ /*-------------------------------------------------------------------------+
+ | If the above calculation did not yield valid timer speed try to estimate
+ | it.
+ +-------------------------------------------------------------------------*/
+ if (board_cfg->tmr_freq==0) {
+ board_cfg->tmr_freq=timebase_speed_calc(UART1_MMIO_BASE);
+ }
+ /*-------------------------------------------------------------------------+
+ | Read information passed from service processor.
+ +-------------------------------------------------------------------------*/
+ board_cfg->mem_size=sdram_size();
+ /*-------------------------------------------------------------------------+
+ | Assign rest of the information.
+ +-------------------------------------------------------------------------*/
+ board_cfg->ser_freq=UART_INPUT_CLOCK;
+ board_cfg->procver=ppcMfspr_any(SPR_PVR);
+ board_cfg->hid0=ppcMfspr_any(SPR_HID0);
+ board_cfg->hid1=ppcMfspr_any(SPR_HID1);
+ board_cfg->hid4=ppcMfspr_any(SPR_HID4);
+ board_cfg->hid5=ppcMfspr_any(SPR_HID5);
+ board_cfg->hior=ppcMfspr_any(SPR_HIOR);
+ board_cfg->sdr1=ppcMfspr_any(SPR_SDR1);
+ board_cfg->procstr[0]='9';
+ board_cfg->procstr[1]='7';
+ board_cfg->procstr[2]='0';
+ board_cfg->procstr[3]='F';
+ board_cfg->procstr[4]='X';
+ board_cfg->procstr[5]='\0';
+ board_cfg->reserved[0]='\0';
+ (void)get_hwd_addr((char *)board_cfg->hwaddr0, 0);
+ (void)ppcMtmsr(msr);
+ return;
+}
+
+/*----------------------------------------------------------------------------+
+| Get_hwd_addr.
++----------------------------------------------------------------------------*/
+int get_hwd_addr(char *dest,
+ int ethernet_num)
+{
+
+ bios_data_struct_t *bios_data;
+ char *src;
+ unsigned char nc;
+ int len;
+ int num;
+
+ bios_data=(bios_data_struct_t *)PIBS_DATABASE_ADDR;
+ if (ethernet_num!=0) {
+ for(len=0;len<ETHERNET_HW_ADDR_LEN;len++) {
+ dest[len]=(char)0xFF;
+ }
+ return(-1);
+ } else {
+ src=bios_data->bios_eth_hwd0;
+ }
+ len=0;
+ while((src[len]!='\0') && (len<(ETHERNET_HW_ADDR_LEN* 3))) {
+ len++;
+ }
+ if (len!=(ETHERNET_HW_ADDR_LEN* 2)) {
+ for(len=0;len<ETHERNET_HW_ADDR_LEN;len++) {
+ dest[len]=(char)0xFF;
+ }
+ return(-1);
+ }
+ for(len=0;len<(ETHERNET_HW_ADDR_LEN* 2);len++) {
+ nc=toupper((int)src[len]);
+ if ((nc>='0') && (nc<='9')) {
+ num=nc- '0';
+ } else if ((nc>='A') && (nc<='F')) {
+ num=nc- 'A'+ 0xA;
+ } else {
+ for(len=0;len<ETHERNET_HW_ADDR_LEN;len++) {
+ dest[len]=(char)0xFF;
+ }
+ return(-1);
+ }
+ if ((len%2)==0) {
+ dest[len/ 2]=(char)num;
+ } else {
+ dest[len/ 2]=(char)((dest[len/ 2]* 0x10)+ num);
+ }
+ }
+ return(0);
+}
+
+/*----------------------------------------------------------------------------+
+| Get_sys_clk.
++----------------------------------------------------------------------------*/
+int get_sys_clk(unsigned long *value)
+{
+
+ unsigned long data;
+
+ if (read_sp_data(SUPER_IO_NVRAM_DATA_VALID, 4, &data)!=0) {
+ return(-1);
+ }
+ if (data!=SUPER_IO_VALID_VALUE) {
+ return(-1);
+ }
+ if (read_sp_data(SUPER_IO_NVRAM_SYS_CLK, 4, &data)!=0) {
+ return(-1);
+ }
+ *value=data;
+ return(0);
+}
+
+/*----------------------------------------------------------------------------+
+| Get_pll_mult.
++----------------------------------------------------------------------------*/
+int get_pll_mult(unsigned long *value)
+{
+
+ unsigned long data;
+
+ if (read_sp_data(SUPER_IO_NVRAM_DATA_VALID, 4, &data)!=0) {
+ return(-1);
+ }
+ if (data!=SUPER_IO_VALID_VALUE) {
+ return(-1);
+ }
+ if (read_sp_data(SUPER_IO_NVRAM_CLK_MULT, 1, value)!=0) {
+ return(-1);
+ }
+ return(0);
+}
+
+/*----------------------------------------------------------------------------+
+| Get_ei_ratio.
++----------------------------------------------------------------------------*/
+int get_ei_ratio(unsigned long *value)
+{
+
+ unsigned long data;
+
+ if (read_sp_data(SUPER_IO_NVRAM_DATA_VALID, 4, &data)!=0) {
+ return(-1);
+ }
+ if (data!=SUPER_IO_VALID_VALUE) {
+ return(-1);
+ }
+ if (read_sp_data(SUPER_IO_NVRAM_EI_RATIO, 1, &data)!=0) {
+ return(-1);
+ }
+
+ if (data==0x0000000000000000) data=PPC970_EI_RATIO_000;
+ else if (data==0x0000000000000001) data=PPC970_EI_RATIO_001;
+ else if (data==0x0000000000000002) data=PPC970_EI_RATIO_010;
+ else if (data==0x0000000000000003) data=PPC970_EI_RATIO_011;
+ else if (data==0x0000000000000004) data=PPC970_EI_RATIO_100;
+ else if (data==0x0000000000000005) data=PPC970_EI_RATIO_101;
+ else if (data==0x0000000000000006) data=PPC970_EI_RATIO_110;
+ else return(-1);
+
+ *value=data;
+ return(0);
+}
+
+/*----------------------------------------------------------------------------+
+| Read_sp_data.
++----------------------------------------------------------------------------*/
+int read_sp_data(unsigned int offset,
+ unsigned int count, unsigned long *data)
+{
+
+ unsigned long addr_index;
+ unsigned long addr_data;
+ unsigned long addr;
+ unsigned int new_data;
+ unsigned int i;
+
+ /*-------------------------------------------------------------------------+
+ | If this is not a JS20 or EVB platform then just return.
+ +-------------------------------------------------------------------------*/
+ if (what_platform()==PLATFORM_EVB_FINAL) {
+ addr_index=NB_HT_IO_BASE_CPU+ SUPER_IO_ADDR_NVRAM;
+ addr_data=NB_HT_IO_BASE_CPU+ SUPER_IO_ADDR_NVRAM+ 1;
+ *data=0x0000000000000000;
+ for(i=0;i<count;i++) {
+ (void)outbyte(addr_index, offset+ i);
+ new_data=inbyte(addr_data);
+ *data|=new_data<<((count- i- 1)* 8);
+ }
+ return(0);
+ } else if (what_platform()==PLATFORM_EVB_LITE) {
+ addr=SB_NVRAM_ADDR;
+ *data=0x0000000000000000;
+ for(i=0;i<count;i++) {
+ new_data=inbyte(addr+ i+ offset);
+ *data|=new_data<<((count- i- 1)* 8);
+ }
+ return(0);
+ }
+ return(-1);
+}
+
+/*----------------------------------------------------------------------------+
+| Write_sp_data.
++----------------------------------------------------------------------------*/
+int write_sp_data(unsigned int offset,
+ unsigned int data)
+{
+
+ unsigned long addr_index;
+ unsigned long addr_data;
+ unsigned long addr;
+
+ /*-------------------------------------------------------------------------+
+ | If this is not a JS20 or EVB platform then just return.
+ +-------------------------------------------------------------------------*/
+ if (what_platform()==PLATFORM_EVB_FINAL) {
+ addr_index=NB_HT_IO_BASE_CPU+ SUPER_IO_ADDR_NVRAM;
+ addr_data=NB_HT_IO_BASE_CPU+ SUPER_IO_ADDR_NVRAM+ 1;
+ (void)outbyte(addr_index, offset);
+ (void)outbyte(addr_data, data);
+ return(0);
+ } else if (what_platform()==PLATFORM_EVB_LITE) {
+ addr=SB_NVRAM_ADDR;
+ (void)outbyte(addr+ offset, data);
+ return(0);
+ }
+ return(-1);
+}
+
+/*----------------------------------------------------------------------------+
+| Read_psr.
++----------------------------------------------------------------------------*/
+unsigned long read_psr()
+{
+
+ unsigned long msr;
+ unsigned long value;
+
+ msr=ppcAndMsr((unsigned long)~MSR_EE);
+ (void)ppcMtspr_any(SPR_SCOMC, SCOM_ADDR_PSR_READ);
+ (void)ppcIsync();
+ value=ppcMfspr_any(SPR_SCOMD);
+ (void)ppcIsync();
+ (void)ppcMtmsr(msr);
+ return(value);
+}
+
+/*----------------------------------------------------------------------------+
+| Write_pcr_pcrh.
++----------------------------------------------------------------------------*/
+void write_pcr_pcrh(unsigned long data)
+{
+
+ unsigned long msr;
+
+ msr=ppcAndMsr((unsigned long)~MSR_EE);
+ /*-------------------------------------------------------------------------+
+ | First write to PCR with all 0 (errata).
+ +-------------------------------------------------------------------------*/
+ (void)ppcMtspr_any(SPR_SCOMD, SCOM_ADDR_PCR_DATA_MASK);
+ (void)ppcIsync();
+ (void)ppcMtspr_any(SPR_SCOMC, SCOM_ADDR_PCR_WRITE);
+ (void)ppcIsync();
+ /*-------------------------------------------------------------------------+
+ | Write to PCRH.
+ +-------------------------------------------------------------------------*/
+ (void)ppcMtspr_any(SPR_SCOMD, 0x0000000000000000UL);
+ (void)ppcIsync();
+ (void)ppcMtspr_any(SPR_SCOMC, SCOM_ADDR_PCR_WRITE);
+ (void)ppcIsync();
+ /*-------------------------------------------------------------------------+
+ | Write to PCR.
+ +-------------------------------------------------------------------------*/
+ (void)ppcMtspr_any(SPR_SCOMD, data|SCOM_ADDR_PCR_DATA_MASK);
+ (void)ppcIsync();
+ (void)ppcMtspr_any(SPR_SCOMC, SCOM_ADDR_PCR_WRITE);
+ (void)ppcIsync();
+ (void)ppcMtmsr(msr);
+ return;
+}
+
+/*----------------------------------------------------------------------------+
+| Is_writable.
++----------------------------------------------------------------------------*/
+int is_writable(unsigned long addr,
+ unsigned long len)
+{
+
+ if ((addr>=BOOT_BASE) && (addr<SDRAM_UPPER_BASE)) {
+ return(0);
+ }
+ if ((addr+ len)>=BOOT_BASE) {
+ return(0);
+ }
+ return(1);
+}
+
--- /dev/null
+\r
+#ifndef _boardutil_h_\r
+#define _boardutil_h_\r
+\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Board specific defines.\r
++----------------------------------------------------------------------------*/\r
+#define FLASH_INTEL_SECTORSIZE 0x00020000\r
+#define FLASH_AMD_SECTORSIZE 0x00010000\r
+#define PIBS2_MAX_SIZE 0x000E0000\r
+#define PIBS_DATABASE_SIZE 0x00020000\r
+#define PIBS_DATABASE_ADDR 0x00000000FFFE0000UL\r
+\r
+#define PIBS_DATA_FIELDSIZE 256\r
+#define ETHERNET_HW_ADDR_LEN 6\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Current board settings.\r
++----------------------------------------------------------------------------*/\r
+typedef struct board_cfg_data {\r
+ char usr_config_ver[4];\r
+ unsigned char reserved[28];\r
+ unsigned long tmr_freq;\r
+ unsigned long mem_size;\r
+ unsigned long ei_ratio;\r
+ unsigned long sys_freq;\r
+ unsigned long cpu_freq;\r
+ unsigned long freq_ratio;\r
+ unsigned long ser_freq;\r
+ unsigned long procver;\r
+ unsigned long hid0;\r
+ unsigned long hid1;\r
+ unsigned long hid4;\r
+ unsigned long hid5;\r
+ unsigned long hior;\r
+ unsigned long sdr1;\r
+ char procstr[16];\r
+ unsigned char hwaddr0[ETHERNET_HW_ADDR_LEN];\r
+ unsigned char pad_size[2];\r
+} board_cfg_data_t;\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PIBS data CPU2.\r
++----------------------------------------------------------------------------*/\r
+typedef struct cpu_data {\r
+ unsigned long img_srr0;\r
+ unsigned long img_srr1;\r
+ unsigned long r3_value;\r
+ unsigned long img_valid;\r
+} cpu_data_t;\r
+\r
+/*----------------------------------------------------------------------------+\r
+| PIBS data.\r
++----------------------------------------------------------------------------*/\r
+typedef struct bios_data_struct {\r
+ /*-------------------------------------------------------------------------+\r
+ | Is this data section valid? [TRUE|FALSE] string.\r
+ +-------------------------------------------------------------------------*/\r
+ char bios_data_valid[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | Information about the main PIBS board image [TRUE|FALSE] string.\r
+ +-------------------------------------------------------------------------*/\r
+ char pibs2_valid[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | Autoboot configuration.\r
+ +-------------------------------------------------------------------------*/\r
+ char autoboot_parm[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | Configuration.\r
+ +-------------------------------------------------------------------------*/\r
+ char bios_eth_hwd0[PIBS_DATA_FIELDSIZE];\r
+ char ifconfig_parm0[PIBS_DATA_FIELDSIZE];\r
+ char route_parm[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | TFTP information.\r
+ +-------------------------------------------------------------------------*/\r
+ char bios_tftp_fname[PIBS_DATA_FIELDSIZE];\r
+ char bios_tftp_destip[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | Chip and board clocking information.\r
+ +-------------------------------------------------------------------------*/\r
+ char clocking_valid[PIBS_DATA_FIELDSIZE];\r
+ char clocking_parm[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | User data, alias list, autoboot delay, dhcp flag.\r
+ +-------------------------------------------------------------------------*/\r
+ char user_data[PIBS_DATA_FIELDSIZE];\r
+ char aliaslist[PIBS_DATA_FIELDSIZE];\r
+ char autoboot_delay[PIBS_DATA_FIELDSIZE];\r
+ char dhcp0[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | HT link optimization variable.\r
+ +-------------------------------------------------------------------------*/\r
+ char opthtlink[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | Indicates IDE cable type.\r
+ +-------------------------------------------------------------------------*/\r
+ char ide80wire[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | Automatically initialize IDE.\r
+ +-------------------------------------------------------------------------*/\r
+ char initide[PIBS_DATA_FIELDSIZE];\r
+ /*-------------------------------------------------------------------------+\r
+ | OpenFirmware interface private variable\r
+ +-------------------------------------------------------------------------*/\r
+ char openfirmware[PIBS_DATA_FIELDSIZE];\r
+} bios_data_struct_t;\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Function prototypes.\r
++----------------------------------------------------------------------------*/\r
+void get_system_info(\r
+ board_cfg_data_t *board_cfg );\r
+\r
+int get_hwd_addr(\r
+ char *dest,\r
+ int ethernet_num );\r
+\r
+int get_sys_clk(\r
+ unsigned long *value );\r
+\r
+int get_pll_mult(\r
+ unsigned long *value );\r
+\r
+int get_ei_ratio(\r
+ unsigned long *value );\r
+\r
+int read_sp_data(\r
+ unsigned int offset,\r
+ unsigned int count,\r
+ unsigned long *data );\r
+\r
+int write_sp_data(\r
+ unsigned int offset,\r
+ unsigned int data );\r
+\r
+unsigned long read_psr(\r
+ void );\r
+\r
+void write_pcr_pcrh(\r
+ unsigned long data );\r
+\r
+int is_writable(\r
+ unsigned long addr,\r
+ unsigned long len );\r
+\r
+void super_io_setup(\r
+ void );\r
+\r
+unsigned long sdram_size(\r
+ void );\r
+\r
+#endif /* _boardutil_h_ */\r
--- /dev/null
+/*
+ * Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * Do very early board initialization:
+ *
+ * - Setup SIO
+ */
+#include "ppc970.h"
+#include "boardutil.h"
+
+/*----------------------------------------------------------------------------+
+| Local defines.
++----------------------------------------------------------------------------*/
+#define BASE_MASK 0xFFFFFFFF
+
+void
+board_init(void)
+{
+ super_io_setup();
+}
+
+
+/*----------------------------------------------------------------------------+
+| Super_io_setup.
++----------------------------------------------------------------------------*/
+void super_io_setup()
+{
+
+ unsigned long io_base;
+ unsigned long sio_index;
+ unsigned long sio_data;
+ int platform;
+ unsigned int i;
+
+ /*-------------------------------------------------------------------------+
+ | If this is not a JS20 or EVB platform then just return.
+ +-------------------------------------------------------------------------*/
+ platform=what_platform();
+ if (platform==PLATFORM_EVB_FINAL) {
+ /*----------------------------------------------------------------------+
+ | Assign addresses.
+ +----------------------------------------------------------------------*/
+ io_base=(unsigned long)(NB_HT_IO_BASE_BYTE<<NB_HT_IO_BASE_BYTE_SH);
+ io_base&=BASE_MASK;
+ sio_index=io_base+ SUPER_IO_INDEX_OFF;
+ sio_data=io_base+ SUPER_IO_DATA_OFF;
+ /*----------------------------------------------------------------------+
+ | Serial 1 setup/enable.
+ +----------------------------------------------------------------------*/
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_SEL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_S1);
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_MSB);
+ (void)outbyte(sio_data, (unsigned int)((UART0_MMIO_BASE>>8)&0xFF));
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB);
+ (void)outbyte(sio_data, (unsigned int)((UART0_MMIO_BASE>>0)&0xFF));
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE);
+ /*----------------------------------------------------------------------+
+ | Serial 2 setup/enable.
+ +----------------------------------------------------------------------*/
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_SEL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_S2);
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_MSB);
+ (void)outbyte(sio_data, (unsigned int)((UART1_MMIO_BASE>>8)&0xFF));
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB);
+ (void)outbyte(sio_data, (unsigned int)((UART1_MMIO_BASE>>0)&0xFF));
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE);
+ /*----------------------------------------------------------------------+
+ | X-bus setup/enable.
+ +----------------------------------------------------------------------*/
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_SEL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_XBUS);
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_MSB);
+ (void)outbyte(sio_data, (SUPER_IO_ADDR_XBUS>>8)&0xFF);
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB);
+ (void)outbyte(sio_data, (SUPER_IO_ADDR_XBUS>>0)&0xFF);
+ (void)outbyte(sio_index, SUPER_IO_XBUS_CONFIG);
+ (void)outbyte(sio_data, SUPER_IO_BIOS_SIZE_1M);
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE);
+ for(i=0;i<16;i++) {
+ (void)outbyte(io_base+ SUPER_IO_XBUS_HOST_ACCESS, i);
+ }
+ /*----------------------------------------------------------------------+
+ | RTC setup/enable.
+ +----------------------------------------------------------------------*/
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_SEL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_RTC);
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_MSB);
+ (void)outbyte(sio_data, (SUPER_IO_ADDR_RTC>>8)&0xFF);
+ (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB);
+ (void)outbyte(sio_data, (SUPER_IO_ADDR_RTC>>0)&0xFF);
+ (void)outbyte(sio_index, SUPER_IO_EXT_DEV_MSB);
+ (void)outbyte(sio_data, (SUPER_IO_ADDR_NVRAM>>8)&0xFF);
+ (void)outbyte(sio_index, SUPER_IO_EXT_DEV_LSB);
+ (void)outbyte(sio_data, (SUPER_IO_ADDR_NVRAM>>0)&0xFF);
+ (void)outbyte(sio_index, SUPER_IO_RTC_DATE_ALARM_OFF);
+ (void)outbyte(sio_data, SUPER_IO_RTC_DATE_ALARM_LOC);
+ (void)outbyte(sio_index, SUPER_IO_RTC_MONTH_ALARM_OFF);
+ (void)outbyte(sio_data, SUPER_IO_RTC_MONTH_ALARM_LOC);
+ (void)outbyte(sio_index, SUPER_IO_RTC_CENTURY_ALARM_OFF);
+ (void)outbyte(sio_data, SUPER_IO_RTC_CENTURY_ALARM_LOC);
+ (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL);
+ (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE);
+ }
+ return;
+}
+
+void
+board_init2(void)
+{
+}
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_tyan_s2735_ops = {
+ CHIP_NAME("Momentum Apache mainboard")
+};
+#endif
+++ /dev/null
-/*bsp_970fx/include/ppc970fx_board.h, pibs_970, pibs_970_1.0 2/24/05 08:04:58*/
-/*----------------------------------------------------------------------------+
-| COPYRIGHT I B M CORPORATION 2000, 2004
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-| US Government Users Restricted Rights - Use, duplication or
-| disclosure restricted by GSA ADP Schedule Contract with
-| IBM Corp.
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| PPC970FX BSP for EPOS
-| Author: Maciej P. Tyrlik
-| Component: Include file.
-| File: ppc970fx_board.h
-| Purpose: Board chip dependent defines. Header file defining PPC970FX and
-| PPC970FX eval board constants. "#define" statements can be placed
-| in this file since it is included from assembler.
-| Changes:
-| Date Comment:
-| --------- --------
-| 14-Sep-00 Created MPT
-| 05-Jan-01 Added defines for "real serial port address" MPT
-| 09-Jan-01 Removed C++ defines that caused problems with XCOFF compilerMPT
-| 06-Mar-01 Chenged location of the serial ports MPT
-| 19-Mar-01 Chenged location of the serial ports MPT
-| 19-Jul-01 Chenged BRDC registr location and added ZMII address MPT
-| 14-Feb-02 Added DMA stuff MPT
-| 18-Jul-02 Port to 405LP Arctic MPT
-| 25-Jul-02 Added all the Core library definitions DWG
-| 29-Aug-02 Added all Ready Timeout Count (RTC) options to EBC0_CFG DWG
-| 30-Sep-02 Added new clocking bits for pass 2 MPT
-| 27-Jan-03 Port to 7XXFX MPT
-| 04-Feb-03 Add divisor for UART SCC
-| 04-Feb-03 Added MV64360 Reg Defines & Changed UART MMIO Base CRB
-| 24-Apr-03 Updated for CPLD revisions MPT
-| 29-May-03 Add PCI related defines SCC
-| 06-Aug-03 Port to Buckeye SCC
-| 08-Sep-03 More changes for MV64460 on Buckeye MCG
-| 12-Sep-03 Moved all PVR #defines here from other files MCG
-| 16-Sep-03 Added MV64460 MPP register offsets MCG
-| 31-Oct-03 Added SRAM_CFG bit definitions, Ethernet BAx bit defs MCG
-| 31-Oct-03 Lowered max RX burst length for Ethernet cache coherency MCG
-| 08-Dec-03 New defines PCI P2P regs, interrupt cause/mask regs MCG
-| 04-Feb-04 All new for PPC970FX MPT
-+----------------------------------------------------------------------------*/
-
-#ifndef _PPC970FX_H_
-#define _PPC970FX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------------+
-| Processor Version Register (PVR) values
-+----------------------------------------------------------------------------*/
-#define PVR_970 0x0039 /* 970 any revision*/
-#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */
-#define PVR_970FX 0x003C /* 970FX any revision*/
-#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */
-#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */
-#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */
-#define PVR_RESERVED 0x000000F0 /* reserved nibble */
-
-/*----------------------------------------------------------------------------+
-| Supported platforms.
-+----------------------------------------------------------------------------*/
-#define PLATFORM_G5 0
-#define PLATFORM_NEW_JS20 2
-#define PLATFORM_EVB_LITE 3
-#define PLATFORM_EVB_FINAL 4
-#define PLATFORM_APACHE 5
-
-/*----------------------------------------------------------------------------+
-| When timers are running based on CPU speed this is the timer to CPU frequency
-| ratio.
-+----------------------------------------------------------------------------*/
-#define PPC970_TB_RATIO 8
-
-/*----------------------------------------------------------------------------+
-| Cache line size.
-+----------------------------------------------------------------------------*/
-#define CACHE_LINE_SIZE_L1 128
-#define CACHE_LINE_SIZE_L2 128
-
-/*----------------------------------------------------------------------------+
-| SLB size.
-+----------------------------------------------------------------------------*/
-#define SLB_SIZE 64
-
-/*----------------------------------------------------------------------------+
-| TLB size.
-+----------------------------------------------------------------------------*/
-#define TLB_SIZE 1024
-
-/*----------------------------------------------------------------------------+
-| Partial memory map.
-+----------------------------------------------------------------------------*/
-#define SDRAM_BASE 0x0000000000000000UL
-#define SDRAM_SIZE 0x0000000080000000UL
-#define IO_BASE 0x0000000080000000UL
-#define IO_SIZE 0x0000000080000000UL
-#define PCI_BUS_MEM_BASE 0x0000000080000000UL
-#define PCI_BUS_MEM_SIZE 0x0000000070000000UL
-#define PCI0_BASE 0x00000000F0000000UL
-#define PCI0_SIZE 0x0000000002000000UL
-#define HT1_BASE 0x00000000F2000000UL
-#define HT1_SIZE 0x0000000003000000UL
-#define PPC925_BASE 0x00000000F8000000UL
-#define PPC925_SIZE 0x0000000001000000UL
-#define SB_IOAPIC_BASE 0x00000000FEC00000UL
-#define BOOT_BASE 0x00000000FF000000UL
-#define BOOT_BASE_AS 0x00000000FF000000
-#define BOOT_END 0x00000000FFFFFFFFUL
-#define FLASH_BASE_INTEL 0x00000000FF800000UL
-#define FLASH_BASE_INTEL_AS 0x00000000FF800000
-#define FLASH_BASE_AMD 0x00000000FFF00000UL
-#define FLASH_BASE_AMD_AS 0x00000000FFF00000
-#define SDRAM_UPPER_BASE 0x0000000100000000UL
-#define SDRAM_UPPER_SIZE 0x0000000F00000000UL
-
-/*----------------------------------------------------------------------------+
-| BOOT_STACK_ADDR is data used for stack before SDRAM is available. This data
-| will be written to memory after the SDRAM is initialized. All values here
-| must be less than 32 bits. Following 14 defines need to be changed when
-| changing the location of PIBS in SDRAM (the link file also need to be
-| changed in order to fully relocate PIBS.
-+----------------------------------------------------------------------------*/
-#define PIBS_BASE_ADDR 0x00C00000
-#define BOOT_STACK_ADDR 0x00CE0000
-#define BOOT_STACK_SIZE 0x00004000
-#define MEM_CHK_START_ADDR 0x00C40000
-#define MEM_CHK_SIZE 0x00008000
-
-/*----------------------------------------------------------------------------+
-| Address of a CPU0, CPU1 shared memory structure.
-+----------------------------------------------------------------------------*/
-#define CPU1_DATA_STRUCT_ADDR 0x00C00040
-#define CPU1_DATA_STRUCT_SRR0_OFF 0x00000000
-#define CPU1_DATA_STRUCT_SRR1_OFF 0x00000008
-#define CPU1_DATA_STRUCT_R3_OFF 0x00000010
-#define CPU1_DATA_STRUCT_VALID_OFF 0x00000018
-#define CPU1_DATA_STRUCT_DEL_VALID_OFF 0x00000020
-
-/*----------------------------------------------------------------------------+
-| Address of the memory location used for the test and set instruction
-| sequence.
-+----------------------------------------------------------------------------*/
-#define VM_TEST_AND_SET_ADDR 0x0000000000C000F0UL
-
-/*----------------------------------------------------------------------------+
-| Initial page table address.
-+----------------------------------------------------------------------------*/
-#define INITIAL_PAGE_TABLE_ADDR_CPU0 0x0000000000D00000
-#define INITIAL_PAGE_TABLE_ADDR_CPU1 0x0000000000D40000
-#define INITIAL_PAGE_TABLE_SIZE 0x0000000000040000
-
-/*----------------------------------------------------------------------------+
-| Initial stack size. Must be less than 32 bits in length.
-+----------------------------------------------------------------------------*/
-#define MY_MAIN_STACK_SIZE (8* 1024)
-
-/*----------------------------------------------------------------------------+
-| PCI prefetchable and non-prefetchable master memory windows.
-| The prefetchable region is large enough to cover 2GB of CPC925 attached
-| SDRAM plus space for other devices on the bus.
-+----------------------------------------------------------------------------*/
-#define PCI_MEM_PF_CPU_ADDR 0x00000000
-#define PCI_MEM_PF_PCI_ADDR 0x00000000
-#define PCI_MEM_PF_SIZE 0xA0000000
-#define PCI_MEM_NPF_CPU_ADDR 0xA0000000
-#define PCI_MEM_NPF_PCI_ADDR 0xA0000000
-#define PCI_MEM_NPF_SIZE 0x20000000
-
-/*----------------------------------------------------------------------------+
-| Serial port address. The base address must be programmed into super I/O. The
-| external time base is available only on JS20.
-+----------------------------------------------------------------------------*/
-#if defined(PPC970FX_EVB) || defined(PPC970FX_APACHE)
-#define UART1_MMIO_BASE 0xF40002F8UL
-#define UART0_MMIO_BASE 0xF40003F8UL
-#define UART1_MMIO_OFFSET 0x2F8;
-#define UART0_MMIO_OFFSET 0x3F8;
-#define UART_INPUT_CLOCK 1843200
-#define EXT_TIME_BASE_FREQ 0
-#define DIV_HIGH_9600 0x00
-#define DIV_LOW_9600 0x0C
-#endif
-
-#ifdef PPC970FX_EVB_LITE
-#define UART1_MMIO_BASE 0xF40002F8UL
-#define UART0_MMIO_BASE 0xF40003F8UL
-#define UART1_MMIO_OFFSET 0x2F8;
-#define UART0_MMIO_OFFSET 0x3F8;
-#define UART_INPUT_CLOCK 1843200
-#define EXT_TIME_BASE_FREQ 0
-#define DIV_HIGH_9600 0x00
-#define DIV_LOW_9600 0x0C
-#endif
-
-#ifdef PPC970FX_JS20
-#define UART1_MMIO_BASE 0xF40002F8UL
-#define UART0_MMIO_BASE 0xF40003F8UL
-#define UART1_MMIO_OFFSET 0x2F8;
-#define UART0_MMIO_OFFSET 0x3F8;
-#define UART_INPUT_CLOCK 1843200
-#define EXT_TIME_BASE_FREQ 14318000
-#define DIV_HIGH_9600 0x00
-#define DIV_LOW_9600 0x0C
-#endif
-
-/*----------------------------------------------------------------------------+
-| In case of G5 PCI serial card. G5 uses external time base frequency.
-+----------------------------------------------------------------------------*/
-#ifdef PPC970FX_G5
-#define UART1_MMIO_BASE 0xF40000F0UL
-#define UART0_MMIO_BASE 0xF4010000UL
-#define UART1_MMIO_OFFSET 0x000000F0;
-#define UART0_MMIO_OFFSET 0x00010000;
-#define UART_INPUT_CLOCK 14745600
-#define EXT_TIME_BASE_FREQ 33333333
-#define DIV_HIGH_9600 0x00
-#define DIV_LOW_9600 0x60
-#endif
-
-#define EXT_IRQ_COM1 EXT_SB_HT4
-#define EXT_IRQ_COM2 EXT_SB_HT3
-
-/*----------------------------------------------------------------------------+
-| Locations in Super I/O NVRAM where service processor stores information for
-| the PPC970FX CPU.
-+----------------------------------------------------------------------------*/
-#define SUPER_IO_NVRAM_TEMP0 16
-#define SUPER_IO_NVRAM_TEMP1 (SUPER_IO_NVRAM_TEMP0+ 4)
-#define SUPER_IO_NVRAM_TEMP2 (SUPER_IO_NVRAM_TEMP1+ 4)
-#define SUPER_IO_NVRAM_TEMP3 (SUPER_IO_NVRAM_TEMP2+ 4)
-#define SUPER_IO_NVRAM_TEMP4 (SUPER_IO_NVRAM_TEMP3+ 4)
-#define SUPER_IO_NVRAM_TEMP5 (SUPER_IO_NVRAM_TEMP4+ 4)
-#define SUPER_IO_NVRAM_TEMP6 (SUPER_IO_NVRAM_TEMP5+ 4)
-#define SUPER_IO_NVRAM_TEMP7 (SUPER_IO_NVRAM_TEMP6+ 4)
-#define SUPER_IO_NVRAM_TEMP_VALID (SUPER_IO_NVRAM_TEMP7+ 4)
-
-#define SUPER_IO_NVRAM_DATA_VALID 64
-#define SUPER_IO_NVRAM_SYS_CLK (SUPER_IO_NVRAM_DATA_VALID+ 0x04)
-#define SUPER_IO_NVRAM_CLK_MULT (SUPER_IO_NVRAM_SYS_CLK+ 0x04)
-#define SUPER_IO_NVRAM_EI_RATIO (SUPER_IO_NVRAM_CLK_MULT+ 0x01)
-
-#define SUPER_IO_VALID_VALUE 0x426F4F6D
-
-#define PPC970_EI_RATIO_000 2
-#define PPC970_EI_RATIO_001 3
-#define PPC970_EI_RATIO_010 4
-#define PPC970_EI_RATIO_011 6
-#define PPC970_EI_RATIO_100 8
-#define PPC970_EI_RATIO_101 12
-#define PPC970_EI_RATIO_110 16
-
-/*----------------------------------------------------------------------------+
-| Locations in Super I/O NVRAM where PPC970 store commands for service
-| processor. 0x01 is written by PPC970 to initiate action by the service
-| processor. This value is cleared by the service processor upon receiving
-| the command.
-+----------------------------------------------------------------------------*/
-#define SUPER_IO_NVRAM_POWER_OFF 96
-#define SUPER_IO_NVRAM_RESTART (SUPER_IO_NVRAM_POWER_OFF+ 0x2)
-
-/*----------------------------------------------------------------------------+
-| Default HID register settings.
-+----------------------------------------------------------------------------*/
-#define HID0_PREFEAR 0x0011008180000000
-#define HID1_PREFEAR 0xFD3C200000000000
-#define HID4_PREFEAR 0x0000001000000000
-#define HID5_PREFEAR 0x0000000000000080
-
-/*----------------------------------------------------------------------------+
-| Power control SCOM register definitions.
-+----------------------------------------------------------------------------*/
-#define SCOM_ADDR_PCR_WRITE 0x000000000AA00000UL
-#define SCOM_ADDR_PCR_WRITE_ASM 0x000000000AA00000
-#define SCOM_ADDR_PSR_READ 0x0000000040808000UL
-#define SCOM_ADDR_PSR_READ_ASM 0x0000000040808000
-
-#define SCOM_ADDR_PCR_DATA_MASK 0x0000000080000000UL
-#define SCOM_ADDR_PCR_DATA_MASK_ASM 0x0000000080000000
-
-#define SCOM_ADDR_PCR_FREQ_VALID 0x0000000000010000UL
-#define SCOM_ADDR_PCR_FREQ_FULL 0x0000000000000000UL
-#define SCOM_ADDR_PCR_FREQ_HALF 0x0000000000020000UL
-#define SCOM_ADDR_PCR_FREQ_QUARTER 0x0000000000040000UL
-
-#define SCOM_PSR_FREQ_MASK 0x0300000000000000UL
-#define SCOM_PSR_FREQ_FULL 0x0000000000000000UL
-#define SCOM_PSR_FREQ_HALF 0x0100000000000000UL
-#define SCOM_PSR_FREQ_QUARTER 0x0200000000000000UL
-#define SCOM_PSR_COMM_COMPLETED 0x1000000000000000UL
-#define SCOM_PSR_COMM_COMPLETED_ASM 0x1000000000000000
-
-/*----------------------------------------------------------------------------+
-| Serial port for CPU2
-+----------------------------------------------------------------------------*/
-#define CPU2_SERIAL_PORT 2
-#define CPU2_BAUD_RATE 115200
-
-/*----------------------------------------------------------------------------+
-| External interrupt assignments.
-+----------------------------------------------------------------------------*/
-#define EXT_I2C_MASTER 0
-#define EXT_VSP 1
-#define EXT_HT1_BRIDGE 2
-#define EXT_PCI0_AGP_BRIDGE 3
-#define EXT_SLEEP0 4
-#define EXT_SLEEP1 5
-#define EXT_SB_HT0 6
-#define EXT_SB_HT1 7
-#define EXT_SB_HT2 8
-#define EXT_SB_HT3 9
-#define EXT_SB_HT4 10
-#define EXT_SB_HT5 11
-#define EXT_SB_HT6 12
-#define EXT_SB_HT7 13
-#define EXT_SB_HT8 14
-#define EXT_SB_HT9 15
-#define EXT_SB_HT10 16
-#define EXT_SB_HT11 17
-#define EXT_SB_HT12 18
-#define EXT_SB_HT13 19
-#define EXT_SB_HT14 20
-#define EXT_SB_HT15 21
-#define EXT_SB_HT16 22
-#define EXT_SB_HT17 23
-#define EXT_SB_HT18 24
-#define EXT_SB_HT19 25
-#define EXT_SB_HT20 26
-#define EXT_SB_HT21 27
-#define EXT_SB_HT22 28
-#define EXT_SB_HT23 29
-#define EXT_SB_HT24 30
-#define EXT_SB_HT25 31
-#define EXT_SB_HT26 32
-#define EXT_SB_HT27 33
-#define EXT_SB_HT28 34
-#define EXT_SB_HT29 35
-#define EXT_SB_HT30 36
-#define EXT_SB_HT31 37
-#define EXT_SB_HT32 38
-#define EXT_SB_HT33 39
-#define EXT_SB_HT34 40
-#define EXT_SB_HT35 41
-#define EXT_SB_HT36 42
-#define EXT_SB_HT37 43
-#define EXT_SB_HT38 44
-#define EXT_SB_HT39 45
-#define EXT_SB_HT40 46
-#define EXT_SB_HT41 47
-#define EXT_SB_HT42 48
-#define EXT_SB_HT43 49
-#define EXT_SB_HT44 50
-#define EXT_SB_HT45 51
-#define EXT_SB_HT46 52
-#define EXT_SB_HT47 53
-#define EXT_SB_HT48 54
-#define EXT_SB_HT49 55
-#define EXT_SB_HT50 56
-#define EXT_SB_HT51 57
-#define EXT_SB_HT52 58
-#define EXT_SB_HT53 59
-#define EXT_SB_HT54 60
-#define EXT_SB_HT55 61
-#define EXT_SB_HT56 62
-#define EXT_SB_HT57 63
-#define EXT_SB_HT58 64
-#define EXT_SB_HT59 65
-#define EXT_SB_HT60 66
-#define EXT_SB_HT61 67
-#define EXT_SB_HT62 68
-#define EXT_SB_HT63 69
-#define EXT_SB_HT64 70
-#define EXT_SB_HT65 71
-#define EXT_SB_HT66 72
-#define EXT_SB_HT67 73
-#define EXT_SB_HT68 74
-#define EXT_SB_HT69 75
-#define EXT_SB_HT70 76
-#define EXT_SB_HT71 77
-#define EXT_SB_HT72 78
-#define EXT_SB_HT73 79
-#define EXT_SB_HT74 80
-#define EXT_SB_HT75 81
-#define EXT_SB_HT76 82
-#define EXT_SB_HT77 83
-#define EXT_SB_HT78 84
-#define EXT_SB_HT79 85
-#define EXT_SB_HT80 86
-#define EXT_SB_HT81 87
-#define EXT_SB_HT82 88
-#define EXT_SB_HT83 89
-#define EXT_SB_HT84 90
-#define EXT_SB_HT85 91
-#define EXT_SB_HT86 92
-#define EXT_SB_HT87 93
-#define EXT_SB_HT88 94
-#define EXT_SB_HT90 95
-#define EXT_SB_HT91 96
-#define EXT_SB_HT92 97
-#define EXT_SB_HT93 98
-#define EXT_SB_HT94 99
-#define EXT_SB_HT95 100
-#define EXT_SB_HT96 101
-#define EXT_SB_HT97 102
-#define EXT_SB_HT98 103
-#define EXT_SB_HT99 104
-#define EXT_SB_HT100 105
-#define EXT_SB_HT101 106
-#define EXT_SB_HT102 107
-#define EXT_SB_HT103 108
-#define EXT_SB_HT104 109
-#define EXT_SB_HT105 110
-#define EXT_SB_HT106 111
-#define EXT_SB_HT107 112
-#define EXT_SB_HT108 113
-#define EXT_SB_HT109 114
-#define EXT_SB_HT110 115
-#define EXT_SB_HT111 116
-#define EXT_SB_HT112 117
-#define EXT_SB_HT113 118
-#define EXT_SB_HT114 119
-#define EXT_SB_HT115 120
-#define EXT_SB_HT116 121
-#define EXT_SB_HT117 122
-#define EXT_SB_HT118 123
-#define EXT_IPI_0 124
-#define EXT_IPI_1 125
-#define EXT_MAX_IRQ_NUM 125
-
-/*----------------------------------------------------------------------------+
-| # # # ###### #######
-| # # # # # # #
-| # # # # # # #
-| # # # # ###### #
-| # # ####### # # #
-| # # # # # # #
-| ##### # # # # #
-+----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------+
-| Interrupt Enable Register. DLAB must be set to 0 access this register.
-+----------------------------------------------------------------------------*/
-#define asyncIER 1
-#define asyncIERModem 0x08
-#define asyncIERLine 0x04
-#define asyncIERTransmit 0x02
-#define asyncIERReceive 0x01
-#define asyncIERdisableAll 0x00
-
-/*----------------------------------------------------------------------------+
-| Interrupt Identification Register. Read only register.
-+----------------------------------------------------------------------------*/
-#define asyncIIR 2
-#define asyncIIRMask 0x0F
-#define asyncIIRFifoTimeout 0x0C
-#define asyncIIRLine 0x06
-#define asyncIIRReceive 0x04
-#define asyncIIRTransmit 0x02
-#define asyncIIRNoInterrupt 0x01
-#define asyncIIRModem 0x00
-
-/*----------------------------------------------------------------------------+
-| FIFO Control Register. Write only register.
-+----------------------------------------------------------------------------*/
-#define asyncFCR 2
-#define asyncFCRFifoTrigger14 0xC0
-#define asyncFCRFifoTrigger8 0x80
-#define asyncFCRFifoTrigger4 0x40
-#define asyncFCRFifoTrigger1 0x00
-#define asyncFCRDmaSet 0x08
-#define asyncFCRClearXmitFifo 0x04
-#define asyncFCRClearRcvFifo 0x02
-#define asyncFCRFifoEnable 0x01
-
-/*----------------------------------------------------------------------------+
-| Line Control Register.
-+----------------------------------------------------------------------------*/
-#define asyncLCR 3
-#define asyncLCRDLAB 0x80
-#define asyncLCRSetBreak 0x40
-#define asyncLCRStickParity 0x20
-#define asyncLCREvenParity 0x10
-#define asyncLCROddParity 0x00
-#define asyncLCRParityEnable 0x08
-#define asyncLCRParityDisable 0x00
-#define asyncLCRStopBitsTwo 0x04
-#define asyncLCRStopBitsOne 0x00
-#define asyncLCRWordLengthSel 0x03
-#define asyncLCRWordLength5 0x00
-#define asyncLCRWordLength6 0x01
-#define asyncLCRWordLength7 0x02
-#define asyncLCRWordLength8 0x03
-
-/*----------------------------------------------------------------------------+
-| Modem Control Register.
-+----------------------------------------------------------------------------*/
-#define asyncMCR 4
-#define asyncMCRLoop 0x10
-#define asyncMCROut2 0x08
-#define asyncMCROut1 0x04
-#define asyncMCRRTS 0x02
-#define asyncMCRDTR 0x01
-#define asyncMCRdisableAll 0x00
-
-/*----------------------------------------------------------------------------+
-| Line Status Register.
-+----------------------------------------------------------------------------*/
-#define asyncLSR 5
-#define asyncLSRRxFifoError 0x80
-#define asyncLSRTxEmpty 0x60
-#define asyncLSRTxShiftEmpty 0x40
-#define asyncLSRTxHoldEmpty 0x20
-#define asyncLSRBreakInterrupt 0x10
-#define asyncLSRFramingError 0x08
-#define asyncLSRParityError 0x04
-#define asyncLSROverrunError 0x02
-#define asyncLSRDataReady 0x01
-
-/*----------------------------------------------------------------------------+
-| Modem Status Register. Read only register.
-+----------------------------------------------------------------------------*/
-#define asyncMSR 6
-#define asyncMSRCD 0x80
-#define asyncMSRRI 0x40
-#define asyncMSRDSR 0x20
-#define asyncMSRCTS 0x10
-#define asyncMSRDeltaDCD 0x08
-#define asyncMSRDeltaRI 0x04
-#define asyncMSRDeltaDSR 0x02
-#define asyncMSRDeltaCTS 0x01
-
-/*----------------------------------------------------------------------------+
-| Miscellanies defines.
-+----------------------------------------------------------------------------*/
-#define asyncScratchReg 7
-#define asyncTxBuffer 0
-#define asyncRxBuffer 0
-#define asyncDLABLsb 0
-#define asyncDLABMsb 1
-
-/*----------------------------------------------------------------------------+
-| ##### ###### ##### ##### ##### #######
-| # # # # # # # # # # #
-| # # # # # # # #
-| # ###### # ###### ##### ######
-| # # # # # #
-| # # # # # # # # # #
-| ##### # ##### ##### ####### #####
-+----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------+
-| When performing PCI configuration read/write the configuration address
-| register must be written and then read before configuration data register is
-| accessed.
-| PCI type 0 Configuration address format is:
-| 0-20 id. sel., 21-23 function number, 24-29 register number|00
-+----------------------------------------------------------------------------*/
-#define NB_PCI_CONFIGURATION_ADDR 0x0F0800000UL
-#define NB_PCI_CONFIGURATION_DATA 0x0F0C00000UL
-
-/*----------------------------------------------------------------------------+
-| When performing HT configuration read/write the configuration address
-| register must be written and then read before configuration data register is
-| accessed.
-| HT type 0 Configuration address format is:
-| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|00
-| HT type 1 configuration address format is
-| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|01
-+----------------------------------------------------------------------------*/
-#define NB_HT_CONFIGURATION_ADDR 0x0F2800000UL
-#define NB_HT_CONFIGURATION_DATA 0x0F2C00000UL
-
-/*----------------------------------------------------------------------------+
-| HT Configuration Address Spaces.
-+----------------------------------------------------------------------------*/
-#define NB_HT_CONFIG_TYPE_0_BASE 0x0F2000000UL
-#define NB_HT_CONFIG_TYPE_1_BASE 0x0F3000000UL
-
-/*----------------------------------------------------------------------------+
-| HT I/O Space. NB_HT_IO_RESERVED is reserved for Super I/O peripherals. The
-| SuperI/O utilizes subtractive decode. All PCI I/0 addresses are translated
-| from 0xF4xxxxxx (CPU) to 0x00xxxxxx (PCI).
-+----------------------------------------------------------------------------*/
-#define NB_HT_IO_BASE_CPU 0x0F4000000UL
-#define NB_HT_IO_BASE_BYTE 0xF4
-#define NB_HT_IO_BASE_BYTE_SH 24
-#define NB_HT_IO_BASE_PCI 0x000000000UL
-#define NB_HT_IO_BASE_ASM 0xF4000000
-#define NB_HT_IO_SIZE 0x000400000UL
-#define NB_HT_IO_RESERVED 0x000010000UL
-
-/*----------------------------------------------------------------------------+
-| HT EOI Space.
-+----------------------------------------------------------------------------*/
-#define NB_HT_EOI_BASE 0x0F4400000UL
-#define NB_HT_EOI_SIZE 0x000400000UL
-
-/*----------------------------------------------------------------------------+
-| HT Device Header Regs. Big Endian.
-+----------------------------------------------------------------------------*/
-#define NB_HT_REG_BASE 0x0F8070000UL
-#define NB_HT_DID_VID 0x0F8070000UL
-#define NB_HT_STAT_CMD 0x0F8070010UL
-#define NB_HT_CLASS_REV 0x0F8070020UL
-#define NB_HT_BIST_HT 0x0F8070030UL
-#define NB_HT_CAP_PTR 0x0F80700D0UL
-#define NB_HT_INT_LINE 0x0F80700F0UL
-
-/*----------------------------------------------------------------------------+
-| HT Capabilities Block. Big Endian.
-+----------------------------------------------------------------------------*/
-#define NB_HT_CMD_PTR_ID 0x0F8070100UL
-#define HT_WARM_RESET 0x00010000
-#define NB_HT_LINK_CFG_CONTROL 0x0F8070110UL
-#define HT_CRC_ERR 0x00000F00
-#define HT_END_OF_CHAIN 0x00000040
-#define HT_INIT 0x00000020
-#define HT_LINK_FAIL 0x00000010
-#define HT_LINK_OUT_MASK 0x70000000
-#define HT_LINK_IN_MASK 0x07000000
-#define HT_LINK_MAX_OUT_MASK 0x00700000
-#define HT_LINK_MAX_IN_MASK 0x00070000
-#define HT_LINK_WIDTH_8_BIT 0x0
-#define HT_LINK_WIDTH_16_BIT 0x1
-#define HT_LINK_WIDTH_32_BIT 0x3
-#define HT_LINK_WIDTH_2_BIT 0x4
-#define HT_LINK_WIDTH_4_BIT 0x5
-#define NB_HT_LINK_FREQ_ERROR 0x0F8070120UL
-#define HT_LINK_FREQ_CAP_MASK 0xFFFF0000
-#define HT_LINK_FREQ_MASK 0x00000F00
-#define HT_LINK_FREQ_200 0x0
-#define HT_LINK_FREQ_300 0x1
-#define HT_LINK_FREQ_400 0x2
-#define HT_LINK_FREQ_500 0x3
-#define HT_LINK_FREQ_600 0x4
-#define HT_LINK_FREQ_800 0x5
-#define HT_LINK_FREQ_1000 0x6
-
-/*----------------------------------------------------------------------------+
-| HT Other registers. Big Endian.
-+----------------------------------------------------------------------------*/
-#define NB_HT_ADDRESS_MASK 0x0F8070200UL
-#define NB_HT_PROCESSOR_INT_CONTROL 0x0F8070210UL
-#define NB_HT_BRIDGE_CONTROL 0x0F8070300UL
-#define HT_SECBUSRESET 0x00400000
-#define NB_HT_TXCTL_DATABUFALLOC 0x0F8070310UL
-#define NB_HT_TXBUFCOUNTMAX 0x0F8070340UL
-
-/*----------------------------------------------------------------------------+
-| Accessed through AGP/PCI configuration space on PCI0 bus.
-+----------------------------------------------------------------------------*/
-#define NB_PCI_ADDRESS_MASK 0x48
-#define NB_PCI_ADDRESS_MASK_RVALUE 0x00000003
-
-/*----------------------------------------------------------------------------+
-| MPIC.
-+----------------------------------------------------------------------------*/
-#define NB_MPIC_TOGGLE 0x0F80000E0UL
-#define NB_MPIC_ENABLE_OUT 0x00000004
-#define NB_MPIC_RESET 0x00000002
-
-#define NB_MPIC_BASE 0x0F8040000UL
-#define NB_MPIC_SIZE 0x000040000UL
-
-#define NB_MPIC_FEATURE 0x0F8041000UL
-#define NB_MPIC_GLOBAL0 0x0F8041020UL
-#define NB_MPIC_GLOBAL0_MPIC_RESET 0x80000000U
-#define NB_MPIC_IPI0_VECT_PRIO 0x0F80410A0UL
-#define NB_MPIC_IPI1_VECT_PRIO 0x0F80410B0UL
-#define NB_MPIC_SPURIOUS_VECTOR 0x0F80410E0UL
-
-#define NB_MPIC_S0_VECT_PRIO 0x0F8050000UL
-#define NB_MPIC_VECT_PRIO_ADDER 0x00000020
-#define NB_MPIC_S0_DESINATION 0x0F8050010UL
-#define NB_MPIC_DESINATION_ADDER 0x00000020
-
-#define NB_MPIC_P0_IPI0_DISPATCH 0x0F8060040UL
-#define NB_MPIC_P0_IPI1_DISPATCH 0x0F8060050UL
-#define NB_MPIC_P0_TASK_PRIO 0x0F8060080UL
-#define NB_MPIC_P0_INT_ACK 0x0F80600A0UL
-#define NB_MPIC_P0_INT_ACK_AS 0x0F80600A0
-#define NB_MPIC_P0_EIO 0x0F80600B0UL
-#define NB_MPIC_P0_EIO_AS 0x0F80600B0
-#define NB_MPIC_P1_IPI0_DISPATCH 0x0F8061040UL
-#define NB_MPIC_P1_IPI1_DISPATCH 0x0F8061050UL
-#define NB_MPIC_P1_TASK_PRIO 0x0F8061080UL
-#define NB_MPIC_P1_INT_ACK 0x0F80610A0UL
-#define NB_MPIC_P1_INT_ACK_AS 0x0F80610A0
-#define NB_MPIC_P1_EIO 0x0F80610B0UL
-#define NB_MPIC_P1_EIO_AS 0x0F80610B0
-
-#define NB_MPIC_IPI_PRIO_MASK 0x000F0000
-#define NB_MPIC_IPI_PRIO_SH 16
-#define NB_MPIC_IPI_VECTOR_MASK 0x000000FF
-#define NB_MPIC_IPI_MASK 0x80000000U
-#define NB_MPIC_IPI_ACTIVE 0x40000000
-
-#define NB_MPIC_EXT_PRIO_MASK 0x000F0000
-#define NB_MPIC_EXT_PRIO_SH 16
-#define NB_MPIC_EXT_VECTOR_MASK 0x000000FF
-#define NB_MPIC_EXT_MASK 0x80000000U
-#define NB_MPIC_EXT_ACTIVE 0x40000000
-#define NB_MPIC_EXT_SENSE 0x00400000
-
-#define NB_MPIC_DEST_CPU0 0x00000001
-#define NB_MPIC_DEST_CPU1 0x00000002
-
-#define NB_MPIC_IPI_CPU0 0x00000001
-#define NB_MPIC_IPI_CPU1 0x00000002
-
-#define NB_MPIC_TASK_PRIO_MASK 0x0000000F
-
-#define NB_MPIC_C0_CASCADE 0x20000000
-
-/*----------------------------------------------------------------------------+
-| I2C.
-+----------------------------------------------------------------------------*/
-#define NB_IIC_MMIO_BASE 0xF8001000UL
-#define NB_IIC_MMIO_BASE_BYTE4 0xF8
-#define NB_IIC_MMIO_BASE_BYTE5 0x00
-#define NB_IIC_MMIO_BASE_BYTE6 0x10
-#define NB_IIC_MMIO_BASE_BYTE7 0x00
-#define NB_IIC_MMIO_BASE_MASK 0xFFFFFFFF
-#define NB_IIC_MMIO_SIZE 0x00001000UL
-#define NB_IIC_MODE 0x00
-#define NB_IIC_CNTRL 0x10
-#define NB_IIC_STATUS 0x20
-#define NB_IIC_ISR 0x30
-#define NB_IIC_IER 0x40
-#define NB_IIC_ADDR 0x50
-#define NB_IIC_SUBADDR 0x60
-#define NB_IIC_DATA 0x70
-#define NB_IIC_REV 0x80
-#define NB_IIC_RISETTIMECNT 0x90
-#define NB_IIC_BITTIMECNT 0xA0
-
-#define IIC_MODE_PORTSEL0 0x00000000
-#define IIC_MODE_PORTSEL1 0x00000010
-#define IIC_MODE_APMODE_MANUAL 0x00000000
-#define IIC_MODE_APMODE_STANDARD 0x00000004
-#define IIC_MODE_APMODE_SUBADDR 0x00000008
-#define IIC_MODE_APMODE_COMBINED 0x0000000C
-#define IIC_MODE_SPEED_25 0x00000002
-#define IIC_MODE_SPEED_50 0x00000001
-#define IIC_MODE_SPEED_100 0x00000000
-
-#define IIC_CNTRL_STOP 0x00000004
-#define IIC_CNTRL_XADDR 0x00000002
-#define IIC_CNTRL_AAK 0x00000001
-
-#define IIC_STATUS_LASTAAK 0x00000002
-
-#define IIC_ISR_ISTOP 0x00000004
-#define IIC_ISR_IADDR 0x00000002
-#define IIC_ISR_IDATA 0x00000001
-
-/*----------------------------------------------------------------------------+
-| DDR_SDRAM Controller.
-+----------------------------------------------------------------------------*/
-#define NB_SDRAM_BASE 0xF8002000UL
-#define NB_SDRAM_BASE_BYTE4 0xF8
-#define NB_SDRAM_BASE_BYTE5 0x00
-#define NB_SDRAM_BASE_BYTE6 0x20
-#define NB_SDRAM_BASE_BYTE7 0x00
-#define NB_SDRAM_BASE_MASK 0xFFFFFFFF
-#define NB_SDRAM_SIZE 0x00001000UL
-#define NB_SDRAM_MEMTIMINGPARAM 0x050
-#define NB_SDRAM_MEMPROGCNTL 0x0E0
-#define NB_SDRAM_MRS 0x0F0
-#define NB_SDRAM_MRSREGCNTL 0x0F0
-#define NB_SDRAM_EMRS 0x100
-#define NB_SDRAM_EMRSREGCNTL 0x100
-#define NB_SDRAM_MEMBUSCFG 0x190
-#define NB_SDRAM_MEMMODE0 0x1C0
-#define NB_SDRAM_MEMBOUNDAD0 0x1D0
-#define NB_SDRAM_MEMMODE1 0x1E0
-#define NB_SDRAM_MEMBOUNDAD1 0x1F0
-#define NB_SDRAM_MEMMODE2 0x200
-#define NB_SDRAM_MEMBOUNDAD2 0x210
-#define NB_SDRAM_MEMMODE3 0x220
-#define NB_SDRAM_MEMBOUNDAD3 0x230
-#define NB_SDRAM_MEMMODE4 0x240
-#define NB_SDRAM_MEMBOUNDAD4 0x250
-#define NB_SDRAM_MEMMODE5 0x260
-#define NB_SDRAM_MEMBOUNDAD5 0x270
-#define NB_SDRAM_MEMMODE6 0x280
-#define NB_SDRAM_MEMBOUNDAD6 0x290
-#define NB_SDRAM_MEMMODE7 0x2A0
-#define NB_SDRAM_MEMBOUNDAD7 0x2B0
-#define NB_SDRAM_MSCR 0x400
-#define NB_SDRAM_MSRSR 0x410
-#define NB_SDRAM_MSRER 0x420
-#define NB_SDRAM_MSPR 0x430
-#define NB_SDRAM_MCCR 0x440
-#define NB_SDRAM_MESR 0x470
-#define NB_SDRAM_MEMMODECNTL 0x500
-#define NB_SDRAM_DELMEASSTATE 0x510
-#define NB_SDRAM_CKDELADJ 0x520
-#define NB_SDRAM_IOMODECNTL 0x530
-#define NB_SDRAM_DQSDELADJ0 0x600
-#define NB_SDRAM_DQSDATADELADJ0 0x610
-
-#define SDRAM_MEMORY_MODE_256M_16Mx16 0x0A000000
-#define SDRAM_MEMORY_MODE_256M_32Mx8 0x0C000000
-#define SDRAM_MEMORY_MODE_512M_64Mx8 0x0E000000
-#define SDRAM_MEMORY_MODE_1G_64Mx16 0x10000000
-#define SDRAM_MEMORY_MODE_1G_128Mx8 0x12000000
-
-#define SDRAM_MEMMODE_BANKEN 0x40000000
-#define SDRAM_MEMMODE_BASEBANKADDR 0x01000000
-#define SDRAM_MEMMODE_LSSIDE 0x00800000
-#define SDRAM_MEMMODE_HSSIDE 0x00400000
-
-#define SDRAM_MEMBOUNDAD_BASEBANKADDR 0xFF000000
-
-#define SDRAM_MEMPROGCNTL_SL 0x80000000
-#define SDRAM_MEMPROGCNTL_WDR 0x40000000
-
-#define SDRAM_MTP_RCD_MASK 0xE0000000
-#define SDRAM_MTP_RP_MASK 0x1C000000
-#define SDRAM_MTP_RAS_MASK 0x03800000
-#define SDRAM_MTP_WRT 0x00400000
-#define SDRAM_MTP_RFC_MASK 0x003C0000
-#define SDRAM_MTP_WRCD 0x00020000
-#define SDRAM_MTP_CAS_RR_MASK 0x0001C000
-#define SDRAM_MTP_CAS_RW_MASK 0x00003800
-#define SDRAM_MTP_TRFCX2 0x00000400
-
-#define SDRAM_MTP_RCD_2 0x20000000
-#define SDRAM_MTP_RCD_3 0x40000000
-#define SDRAM_MTP_RCD_4 0x60000000
-#define SDRAM_MTP_RCD_5 0x80000000
-#define SDRAM_MTP_RCD_6 0xA0000000
-#define SDRAM_MTP_RP_2 0x04000000
-#define SDRAM_MTP_RP_3 0x08000000
-#define SDRAM_MTP_RP_4 0x0C000000
-#define SDRAM_MTP_RP_5 0x10000000
-#define SDRAM_MTP_RP_6 0x14000000
-#define SDRAM_MTP_RAS_4 0x00000000
-#define SDRAM_MTP_RAS_5 0x00800000
-#define SDRAM_MTP_RAS_6 0x01000000
-#define SDRAM_MTP_RAS_7 0x01800000
-#define SDRAM_MTP_RAS_8 0x02000000
-#define SDRAM_MTP_CAS_RR_2 0x00008000
-#define SDRAM_MTP_CAS_RR_3 0x0000C000
-#define SDRAM_MTP_CAS_RR_4 0x00010000
-#define SDRAM_MTP_CAS_RR_5 0x00014000
-#define SDRAM_MTP_CAS_RR_25 0x00018000
-#define SDRAM_MTP_CAS_RW_2 0x00001000
-#define SDRAM_MTP_CAS_RW_3 0x00001800
-#define SDRAM_MTP_CAS_RW_4 0x00002000
-#define SDRAM_MTP_CAS_RW_5 0x00002800
-#define SDRAM_MTP_CAS_RW_25 0x00003000
-
-#define SDRAM_MRS_LTMODE_MASK 0x00000070
-#define SDRAM_MRS_LTMODE_20 0x00000020
-#define SDRAM_MRS_LTMODE_30 0x00000030
-#define SDRAM_MRS_LTMODE_25 0x00000060
-#define SDRAM_MRS_BT 0x00000008
-#define SDRAM_MRS_BL4 0x00000002
-
-#define SDRAM_MMCR_REGISTERED_MASK 0x14400000
-
-#define SDRAM_MSCR_SCRUBMODOFF 0x00000000
-#define SDRAM_MSCR_SCRUBMODBACKG 0x40000000
-#define SDRAM_MSCR_SCRUBMODIMMED 0x80000000
-#define SDRAM_MSCR_SCRUBMODIMMEDFILL 0xC0000000
-#define SDRAM_MSCR_SI_MASK 0x00FF0000
-
-#define SDRAM_MCCR_ECC_EN 0x80000000
-#define SDRAM_MCCR_ECC_APP_DIS 0x40000000
-#define SDRAM_MCCR_EI_EN_H 0x20000000
-#define SDRAM_MCCR_EI_EN_L 0x10000000
-#define SDRAM_MCCR_ECC_UE_MASK_H 0x08000000
-#define SDRAM_MCCR_ECC_CE_MASK_H 0x04000000
-#define SDRAM_MCCR_ECC_UE_MASK_L 0x02000000
-#define SDRAM_MCCR_ECC_CE_MASK_L 0x01000000
-#define SDRAM_MCCR_EI_PAT_H 0x0000FF00
-#define SDRAM_MCCR_EI_PAT_L 0x000000FF
-
-/*----------------------------------------------------------------------------+
-| Power Management.
-+----------------------------------------------------------------------------*/
-#define NB_CLOCK_CTL 0xF8000F00UL
-#define HT_LOGIC_STOP_EN 0x00000010
-#define HT_CLK_EN 0x00000008
-#define NB_PLL2 0xF8000F60UL
-#define NB_PLL2_BYTE4 0xF8
-#define NB_PLL2_BYTE5 0x00
-#define NB_PLL2_BYTE6 0x0F
-#define NB_PLL2_BYTE7 0x60
-#define NB_PLL2_MASK 0xFFFFFFFF
-#define PLL2_FORCEPLLLOAD 0x40000000
-#define PLL2_VALUES_MASK 0x0F01F3FF
-#define PLL2_266 0x021082B8
-#define PLL2_300 0x021092B8
-#define PLL2_333 0x0210A2B8
-#define PLL2_FEEDBACK_MASK 0x0001F000
-#define PLL2_FEEDBACK_SPEED_266 0x00008000
-#define PLL2_FEEDBACK_SPEED_300 0x00009000
-#define PLL2_FEEDBACK_SPEED_333 0x0000A000
-#define PLL2_FEEDBACK_SPEED_366 0x0000B000
-#define PLL2_FEEDBACK_SPEED_400 0x0000C000
-#define PLL2_FEEDBACK_SPEED_433 0x0000D000
-#define PLL2_FEEDBACK_SPEED_466 0x0000E000
-#define PLL2_FEEDBACK_SPEED_500 0x0000F000
-#define NB_PLL4 0xF8000F80UL
-#define PLL4_FORCEPLLLOAD 0x40000000
-
-/*----------------------------------------------------------------------------+
-| CPC925 Control.
-+----------------------------------------------------------------------------*/
-#define NB_REVISION 0xF8000000UL
-#define CPC925_DD1_1 0x00000035
-#define NB_WHOAMI 0xF8000050UL
-#define NB_SEMAPHORE 0xF8000060UL
-#define NB_HW_INIT_STATE 0xF8000070UL
-#define NB_HW_INIT_STATE_ASM 0xF8000070
-
-/*----------------------------------------------------------------------------+
-| Processor Interface Registers.
-+----------------------------------------------------------------------------*/
-#define NB_PI_APIRDQCFG 0xF8030030UL
-#define NB_PI_APIRDQCFG_BYTE4 0xF8
-#define NB_PI_APIRDQCFG_BYTE5 0x03
-#define NB_PI_APIRDQCFG_BYTE6 0x00
-#define NB_PI_APIRDQCFG_BYTE7 0x30
-#define NB_PI_APIRDQCFG_MEMTADLY 0x0000000F
-#define NB_PI_APIEXCP 0xF8030060UL
-#define NB_PI_APIMASK 0xF8030070UL
-#define NB_PI_APIMASK_BYTE4 0xF8
-#define NB_PI_APIMASK_BYTE5 0x03
-#define NB_PI_APIMASK_BYTE6 0x00
-#define NB_PI_APIMASK_BYTE7 0x70
-#define NB_PI_APIMASK_ECC_MASK 0x00F00000
-#define NB_PI_APIMASK_DART 0x80000000
-#define NB_PI_APIMASK_AD0 0x40000000
-#define NB_PI_APIMASK_AD1 0x20000000
-#define NB_PI_APIMASK_STATUS 0x10000000
-#define NB_PI_APIMASK_DATA_ERROR 0x08000000
-#define NB_PI_APIMASK_ADDR0_ERROR 0x04000000
-#define NB_PI_APIMASK_ADDR1_ERROR 0x02000000
-
-/*----------------------------------------------------------------------------+
-| DART.
-+----------------------------------------------------------------------------*/
-#define NB_DART_BASE 0xF8033000UL
-#define NB_DART_SIZE 0x00007000UL
-
-/*----------------------------------------------------------------------------+
-| ##### # # ###### ####### ###### ### #######
-| # # # # # # # # # # # #
-| # # # # # # # # # # #
-| ##### # # ###### ##### ###### # # #
-| # # # # # # # # # #
-| # # # # # # # # # # #
-| ##### ##### # ####### # # ####### ### #######
-+----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------+
-| Configuration registers.
-+----------------------------------------------------------------------------*/
-#define SUPER_IO_INDEX_OFF 0x2E
-#define SUPER_IO_DATA_OFF 0x2F
-
-#define SUPER_SST_IO_INDEX_OFF 0x2E
-#define SUPER_SST_IO_DATA_OFF 0x2F
-
-#define SUPER_IO_DEVICE_SEL 0x07
-#define SUPER_IO_DEVICE_CONFIG3 0x23
-
-#define SUPER_IO_DEVICE_S1 3
-#define SUPER_IO_DEVICE_S2 2
-#define SUPER_IO_DEVICE_SWP 4
-#define SUPER_IO_DEVICE_XBUS 15
-#define SUPER_IO_DEVICE_RTC 16
-
-#define SUPER_IO_ADDR_XBUS 0x800
-#define SUPER_IO_ADDR_RTC 0x900
-#define SUPER_IO_ADDR_NVRAM 0x902
-#define SUPER_IO_SWC_BASE 0x700
-#define SUPER_IO_PM_EVT_BASE 0x720
-#define SUPER_IO_PM_CNT_BASE 0x740
-#define SUPER_IO_GPE_BLK_BASE 0x760
-#define SUPER_IO_SWC_LED_CTRL_OFF 0x0A
-#define SUPER_IO_SWC_LED_BLINK_OFF 0x0B
-
-#define SUPER_IO_DEVICE_CTRL 0x30
-#define SUPER_IO_BASE_DEV_MSB 0x60
-#define SUPER_IO_BASE_DEV_LSB 0x61
-#define SUPER_IO_EXT_DEV_MSB 0x62
-#define SUPER_IO_EXT_DEV_LSB 0x63
-#define SUPER_IO_SWP_PM1_CNT_MSB 0x64
-#define SUPER_IO_SWP_PM1_CNT_LSB 0x65
-#define SUPER_IO_SWP_GP1_CNT_MSB 0x66
-#define SUPER_IO_SWP_GP1_CNT_LSB 0x67
-#define SUPER_IO_INT_NUM 0x70
-#define SUPER_IO_INT_TYPE 0x71
-#define SUPER_IO_BASE_NVRAM_SIZE 128
-#define SUPER_IO_EXT_NVRAM_SIZE 128
-
-#define SUPER_IO_SERIAL_CONFIG 0xF0
-
-#define SUPER_IO_XBUS_CONFIG 0xF8
-#define SUPER_IO_BIOS_SIZE_16M 0x06
-#define SUPER_IO_BIOS_SIZE_1M 0x02
-
-#define SUPER_IO_XBUS_XBCNF (SUPER_IO_ADDR_XBUS+ 0x00)
-#define SUPER_IO_XBUS_SELECT_MODE0 (SUPER_IO_ADDR_XBUS+ 0x0F)
-#define SUPER_IO_XBUS_HOST_ACCESS (SUPER_IO_ADDR_XBUS+ 0x13)
-
-#define SUPER_IO_XBUS_TRANSPD 0x01
-#define SUPER_IO_TBXCS0 0x10
-
-#define SUPER_IO_RTC_DATE_ALARM_OFF 0xF1
-#define SUPER_IO_RTC_MONTH_ALARM_OFF 0xF2
-#define SUPER_IO_RTC_CENTURY_ALARM_OFF 0xF3
-
-#define SUPER_IO_RTC_DATE_ALARM_LOC 0x0D
-#define SUPER_IO_RTC_MONTH_ALARM_LOC 0x0E
-#define SUPER_IO_RTC_CENTURY_ALARM_LOC 0x0F
-
-#define SUPER_IO_DEVICE_ENABLE 0x01
-
-#define SUPER_IO_LED_FUNCTION 0x03
-
-#define SUPER_IO_LED_ON_DEF 0x31
-#define SUPER_IO_LED_RATE 0x65
-
-#define SUPER_IO_SST_START_CONFIG 0x55
-#define SUPER_IO_SST_STOP_CONFIG 0xAA
-
-#define SUPER_IO_SST_ID_INDEX 0x20
-#define SUPER_IO_SST_ID_VALUE 0x51
-
-#define SUPER_IO_SST_DEVICE_INDEX 0x07
-#define SUPER_IO_SST_DEVICE_S1 0x04
-#define SUPER_IO_SST_DEVICE_S2 0x05
-#define SUPER_IO_SST_DEVICE_RUNTIME 0x0A
-
-#define SUPER_IO_INT_SELECT 0x70
-#define SUPER_IO_INT_SERIAL_1 0x04
-#define SUPER_IO_INT_SERIAL_2 0x03
-
-#define SUPER_IO_SST_RUNTIME_REGS 0x100
-
-#define SUPER_IO_BASE_CLOCKL32 0xF0
-
-#define SUPER_IO_BASE_CLOCKL32_ALL_OFF 0x03
-
-#define SUPER_IO_SST_GPIO_52 0x41
-#define SUPER_IO_SST_GPIO_53 0x42
-
-#define SUPER_IO_SST_GPIO_60 0x47
-#define SUPER_IO_SST_GPIO_61 0x48
-
-#define SUPER_IO_SST_GPIO_LED1 0x5D
-#define SUPER_IO_SST_GPIO_LED2 0x5E
-
-#define SEPER_IO_SST_RX 0x05
-#define SEPER_IO_SST_TX 0x04
-
-#define SEPER_IO_SST_LED1 0x06
-#define SEPER_IO_SST_LED2 0x06
-
-#define SEPER_IO_SST_LED_ONE_HZ 0x01
-#define SEPER_IO_SST_LED_HALF_HZ 0x02
-
-/*----------------------------------------------------------------------------+
-| # # # ###### ##### # ##### #
-| # # ## ## # # # # ## # # ##
-| # # # # # # # # # # # # # # #
-| # # # # # # # ##### # ##### #
-| ####### # # # # # # # # #
-| # # # # # # # # # # # #
-| # # # # ###### ##### ##### ##### #####
-+----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------+
-| PCI register information.
-+----------------------------------------------------------------------------*/
-#define HTT_BRIDGE_ID ((unsigned int)0x7450)
-#define HTT_IOAPIC_ID ((unsigned int)0x7451)
-
-#define HTT_INDEX_OFF 0xB8
-#define HTT_DATA_OFF 0xBC
-#define HTT_IOAPIC_CTRL 0x44
-#define HTT_PREF_CONFIG_REG 0x4C
-#define HTT_LINK_CFG_A 0xC4
-#define HTT_LINK_CFG_B 0xC8
-#define HTT_LINK_FREQ_CAP_A 0xCC
-#define HTT_SEC_STATUS_REG 0xA0
-#define HTT_LINK_FREQ_CAP_B 0xD0
-
-/*----------------------------------------------------------------------------+
-| # # # ###### ##### # # #
-| # # ## ## # # # # ## ## ##
-| # # # # # # # # # # # # # # # #
-| # # # # # # # ##### # # #
-| ####### # # # # # # # # #
-| # # # # # # # # # # #
-| # # # # ###### ##### ##### ##### #####
-+----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------+
-| PCI register information.
-+----------------------------------------------------------------------------*/
-#define AMD_VENDOR_ID ((unsigned int)0x1022)
-#define SB_LPCB_DEV_ID ((unsigned int)0x7468)
-#define SB_SYSM_DEV_ID ((unsigned int)0x746B)
-#define SB_PCIB_DEV_ID ((unsigned int)0x7460)
-#define SB_USB_DEV_ID ((unsigned int)0x7464)
-#define SB_EHC_DEV_ID ((unsigned int)0x7463)
-#define SB_ENET_DEV_ID ((unsigned int)0x7462)
-#define SB_IDE_DEV_ID ((unsigned int)0x7469)
-#define SB_SMB_DEV_ID ((unsigned int)0x746A)
-#define SB_AC97AUDIO_DEV_ID ((unsigned int)0x746D)
-#define SB_AC97MODEM_DEV_ID ((unsigned int)0x746E)
-
-#define SB_R_IO_CTRL1 0x40
-#define SB_R_LEG_CTRL 0x42
-#define SB_R_ROM_DECODE 0x43
-#define SB_R_MISC_CTRL 0x47
-#define SB_R_FUNC_ENABLE 0x48
-#define SB_R_IOAPIC_C0 0x4A
-#define SB_R_IOAPIC_C1 0x4B
-#define SB_R_SCICONFIG 0x42
-#define SB_R_PNP_IRQ_SEL 0x44
-#define SB_R_SERIRQ_CONNF 0x4A
-#define SB_R_PCI_PREF_C0 0x50
-#define SB_R_PCI_PREF_C1 0x54
-#define SB_R_PCI_IRQ_ROUTE 0x56
-#define SB_R_NVCTRL 0x74
-
-#define SB_LPC_ROM_W 0x01
-#define SB_LPC_ROM_SIZE 0xC0
-#define SB_PCI_PR_C0 0x00000000
-#define SB_PCI_PR_C1 0x0000718D
-#define SB_NVRAM_EN 0xDE01
-
-#define SB_SYSM_CC_WRITE 0x60
-
-#define SB_NVRAM_ADDR (NB_HT_IO_BASE_CPU+ 0xDE00)
-#define SB_NVRAM_SIZE 0x100
-
-/*----------------------------------------------------------------------------+
-| IDE controller
-+----------------------------------------------------------------------------*/
-#define SB_IDE_PRI_BASE (NB_HT_IO_BASE_CPU+ 0x1F0)
-#define SB_IDE_SEC_BASE (NB_HT_IO_BASE_CPU+ 0x170)
-
-#define IDE_RANGE_LEGACY 0xCC00
-
-#define SB_EIDEC_CMD 0x04
-#define SB_EIDEC_PROG 0x08
-#define SB_EIDEC_INT 0x3C
-#define SB_EIDEC_CONFIG 0x40
-
-#define EIDEC_CMD_BMEN 0x00000004
-#define EIDEC_CMD_IOEN 0x00000001
-#define EIDEC_PROG_PROGIF2 0x00000400
-#define EIDEC_PROG_PROGIF0 0x00000100
-#define EIDEC_CONFIG_PRIEN 0x00000002
-#define EIDEC_CONFIG_SECEN 0x00000001
-
-/*----------------------------------------------------------------------------+
-| LPC bus.
-+----------------------------------------------------------------------------*/
-#define SB_LPC_FUNCENAB 0x48
-#define LPC_FUNCENAB_IDE 0x0002
-
-#define SB_RTC_LEG_ADDR 0x70
-#define SB_RTC_LEG_DATA 0x71
-
-/*----------------------------------------------------------------------------+
-| RTC.
-+----------------------------------------------------------------------------*/
-#define SB_RTC_ADDR_PORT70 (NB_HT_IO_BASE_CPU+ 0x70)
-#define SB_RTC_DATA_PORT71 (NB_HT_IO_BASE_CPU+ 0x71)
-#define SB_RTC_ADDR_PORT72 (NB_HT_IO_BASE_CPU+ 0x72)
-#define SB_RTC_DATA_PORT73 (NB_HT_IO_BASE_CPU+ 0x73)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _PPC970FX_H_ */
--- /dev/null
+#include <ppc970.h>\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Cycle counts ((1/ 9600)* 10) / (1/speed)) - 2%.\r
++----------------------------------------------------------------------------*/\r
+#define SPEED_6_25 (0x0000196E- (65* 2))\r
+#define SPEED_7_159 (0x00001D21- (74* 2))\r
+#define SPEED_8_33 (0x000021E5- (86* 2))\r
+#define SPEED_10_4 (0x00002A51- (108* 2))\r
+#define SPEED_14_318 (0x00003A42- (149* 2))\r
+#define SPEED_16_66 (0x000043D0- (173* 2))\r
+#define SPEED_25 (0x000065B9- (260* 2))\r
+#define SPEED_33 (0x000087A2- (347* 2))\r
+#define SPEED_40 (0x0000A2C2- (416* 2))\r
+#define SPEED_50 (0x0000CB73- (520* 2))\r
+#define SPEED_66 (0x00010C8E- (687* 2))\r
+#define SPEED_80 (0x00014585- (833* 2))\r
+#define SPEED_100 (0x000196E6- (1041* 2))\r
+#define SPEED_125 (0x0001FCA0- (1302* 2))\r
+#define SPEED_133 (0x00021D2D- (1385* 2))\r
+#define SPEED_150 (0x0002625A- (1562* 2))\r
+#define SPEED_166 (0x0002A374- (1729* 2))\r
+#define SPEED_175 (0x0002C813- (1822* 2))\r
+#define SPEED_200 (0x00032DCD- (2093* 2))\r
+#define SPEED_225 (0x00039387- (2343* 2))\r
+#define SPEED_250 (0x0003F940- (2604* 2))\r
+#define SPEED_275 (0x00045EFA- (2864* 2))\r
+#define SPEED_300 (0x0004C4B4- (3125* 2))\r
+#define SPEED_3375 (0x00055D4A- (3515* 2))\r
+#define SPEED_375 (0x0005F5E1- (3906* 2))\r
+#define SPEED_400 (0x00065B9A- (4166* 2))\r
+#define SPEED_433 (0x0006E1E1- (4510* 2))\r
+#define SPEED_466 (0x00076828- (4854* 2))\r
+#define SPEED_500 (0x0007F281- (5208* 2))\r
+\r
+/*----------------------------------------------------------------------------+\r
+| Timebase_speed_calc\r
++----------------------------------------------------------------------------*/\r
+ function_prolog(timebase_speed_calc)\r
+ mfmsr r10\r
+ rlwinm r11,r10,0,17,15\r
+ mtmsrd r11,1\r
+ isync\r
+ /*--------------------------------------------------------------------+\r
+ | Make sure that all the characters in the transmit buffer are sent.\r
+ +--------------------------------------------------------------------*/\r
+..sent: lbz r6,asyncLSR(r3)\r
+ andi. r6,r6,0x0060\r
+ cmpi cr0,1,r6,0x0060\r
+ bne ..sent\r
+ /*--------------------------------------------------------------------+\r
+ | Store current serial port settings in r11, r12.\r
+ | r11 BH (baud high), BL (baud low), LCR\r
+ | r12 MCR, IER, FCR\r
+ +--------------------------------------------------------------------*/\r
+ lbz r4,asyncLCR(r3)\r
+ ori r11,r4,0x0000\r
+ lbz r4,asyncFCR(r3)\r
+ ori r12,r4,0x0000\r
+ lbz r4,asyncIER(r3)\r
+ rlwimi r12,r4,8,16,23\r
+ lbz r4,asyncMCR(r3)\r
+ rlwimi r12,r4,16,8,15\r
+ /*--------------------------------------------------------------------+\r
+ | Store BH and BL and program new baud rate.\r
+ +--------------------------------------------------------------------*/\r
+ addi r4,r0,0x80 \r
+ stb r4,asyncLCR(r3)\r
+ lbz r4,asyncDLABMsb(r3)\r
+ rlwimi r11,r4,16,8,15\r
+ addi r4,r0,DIV_HIGH_9600\r
+ stb r4,asyncDLABMsb(r3)\r
+ lbz r4,asyncDLABLsb(r3)\r
+ rlwimi r11,r4,8,16,23\r
+ addi r4,r0,DIV_LOW_9600\r
+ stb r4,asyncDLABLsb(r3)\r
+ addi r4,r0,0x03 \r
+ stb r4,asyncLCR(r3)\r
+ /*--------------------------------------------------------------------+\r
+ | Put the serial port in loop-back mode.\r
+ +--------------------------------------------------------------------*/\r
+ addi r4,r0,0x00 \r
+ stb r4,asyncFCR(r3)\r
+ stb r4,asyncIER(r3)\r
+ addi r4,r0,0x10\r
+ stb r4,asyncMCR(r3)\r
+ lbz r4,asyncRxBuffer(r3)\r
+ addi r4,r0,0x0041 \r
+ /*--------------------------------------------------------------------+\r
+ | Again make sure there are no characters in transmit buffer.\r
+ +--------------------------------------------------------------------*/\r
+ addi r5,r0,0\r
+..again:lbz r6,asyncLSR(r3)\r
+ andi. r6,r6,0x0060\r
+ cmpi cr0,1,r6,0x0060\r
+ bne ..again\r
+ /*--------------------------------------------------------------------+\r
+ | Take a snapshot of the timebase.\r
+ +--------------------------------------------------------------------*/\r
+ mfspr r7,tblr\r
+ /*--------------------------------------------------------------------+\r
+ | Send a character while in loopback mode. This will be done twice.\r
+ | Once to get the instuctions into I-cache, the second time for the\r
+ | real measurement.\r
+ +--------------------------------------------------------------------*/\r
+ stb r4,asyncTxBuffer(r3)\r
+..spnlp:lbz r6,asyncLSR(r3)\r
+ andi. r6,r6,0x01\r
+ beq ..spnlp\r
+ mfspr r9,tblr\r
+ /*--------------------------------------------------------------------+\r
+ | Perform subtraction to determine how many timebase ticks it took\r
+ | to transmit the character.\r
+ +--------------------------------------------------------------------*/\r
+ subfc r9,r7,r9\r
+ /*--------------------------------------------------------------------+\r
+ | Consume the character sent in loopback mode.\r
+ +--------------------------------------------------------------------*/\r
+ lbz r4,asyncRxBuffer(r3)\r
+ eieio\r
+ /*--------------------------------------------------------------------+\r
+ | If the first character was just sent, go back and send a second.\r
+ +--------------------------------------------------------------------*/\r
+ cmpi cr0,1,r5,0x0000\r
+ addi r5,r5,1\r
+ beq ..again\r
+ /*--------------------------------------------------------------------+\r
+ | Restore serial port settings.\r
+ +--------------------------------------------------------------------*/\r
+ addi r4,r0,0x80 \r
+ stb r4,asyncLCR(r3)\r
+ rlwinm r4,r11,16,24,31\r
+ stb r4,asyncDLABMsb(r3)\r
+ rlwinm r4,r11,24,24,31\r
+ stb r4,asyncDLABLsb(r3)\r
+ rlwinm r4,r11,0,24,31\r
+ stb r4,asyncLCR(r3)\r
+ rlwinm r4,r12,16,24,31\r
+ stb r4,asyncMCR(r3)\r
+ rlwinm r4,r12,24,24,31\r
+ stb r4,asyncIER(r3)\r
+ rlwinm r4,r12,0,24,31\r
+ stb r4,asyncFCR(r3)\r
+ /*--------------------------------------------------------------------+\r
+ | Calculate timebase speed (r9 is the time we are referencing).\r
+ +--------------------------------------------------------------------*/\r
+ addis r4,r0,SPEED_7_159@h\r
+ ori r4,r4,SPEED_7_159@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq6 \r
+ addis r4,r0,SPEED_8_33@h\r
+ ori r4,r4,SPEED_8_33@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq7 \r
+ addis r4,r0,SPEED_10_4@h\r
+ ori r4,r4,SPEED_10_4@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq8 \r
+ addis r4,r0,SPEED_14_318@h\r
+ ori r4,r4,SPEED_14_318@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq10\r
+ addis r4,r0,SPEED_16_66@h\r
+ ori r4,r4,SPEED_16_66@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq14\r
+ addis r4,r0,SPEED_25@h\r
+ ori r4,r4,SPEED_25@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq16\r
+ addis r4,r0,SPEED_33@h\r
+ ori r4,r4,SPEED_33@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq25\r
+ addis r4,r0,SPEED_40@h\r
+ ori r4,r4,SPEED_40@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq33\r
+ addis r4,r0,SPEED_50@h\r
+ ori r4,r4,SPEED_50@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq40\r
+ addis r4,r0,SPEED_66@h\r
+ ori r4,r4,SPEED_66@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq50\r
+ addis r4,r0,SPEED_80@h\r
+ ori r4,r4,SPEED_80@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq66\r
+ addis r4,r0,SPEED_100@h\r
+ ori r4,r4,SPEED_100@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq80\r
+ addis r4,r0,SPEED_125@h\r
+ ori r4,r4,SPEED_125@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq100\r
+ addis r4,r0,SPEED_133@h\r
+ ori r4,r4,SPEED_133@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq125\r
+ addis r4,r0,SPEED_150@h\r
+ ori r4,r4,SPEED_150@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq133\r
+ addis r4,r0,SPEED_166@h\r
+ ori r4,r4,SPEED_166@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq150\r
+ addis r4,r0,SPEED_175@h\r
+ ori r4,r4,SPEED_175@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq166\r
+ addis r4,r0,SPEED_200@h\r
+ ori r4,r4,SPEED_200@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq175\r
+ addis r4,r0,SPEED_225@h\r
+ ori r4,r4,SPEED_225@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq200\r
+ addis r4,r0,SPEED_250@h\r
+ ori r4,r4,SPEED_250@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq225\r
+ addis r4,r0,SPEED_275@h\r
+ ori r4,r4,SPEED_275@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq250\r
+ addis r4,r0,SPEED_300@h\r
+ ori r4,r4,SPEED_300@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq275\r
+ addis r4,r0,SPEED_3375@h\r
+ ori r4,r4,SPEED_3375@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq300\r
+ addis r4,r0,SPEED_375@h\r
+ ori r4,r4,SPEED_375@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq3375\r
+ addis r4,r0,SPEED_400@h\r
+ ori r4,r4,SPEED_400@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq375\r
+ addis r4,r0,SPEED_433@h\r
+ ori r4,r4,SPEED_433@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq400\r
+ addis r4,r0,SPEED_466@h\r
+ ori r4,r4,SPEED_466@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq433\r
+ addis r4,r0,SPEED_500@h\r
+ ori r4,r4,SPEED_500@l\r
+ cmp cr0,r9,r4\r
+ blt ..freq466\r
+ b ..freq500\r
+..freq6:\r
+ addis r3,r0,0x005F\r
+ ori r3,r3,0x5e10\r
+ b ..end\r
+..freq7:\r
+ addis r3,r0,0x006D\r
+ ori r3,r3,0x3CD8\r
+ b ..end\r
+..freq8:\r
+ addis r3,r0,0x007F\r
+ ori r3,r3,0x2815\r
+ b ..end\r
+..freq10:\r
+ addis r3,r0,0x009e\r
+ ori r3,r3,0xb100\r
+ b ..end\r
+..freq14:\r
+ addis r3,r0,0x00da\r
+ ori r3,r3,0x79b0\r
+ b ..end\r
+..freq16:\r
+ addis r3,r0,0x00fe\r
+ ori r3,r3,0x502A\r
+ b ..end\r
+..freq25:\r
+ addis r3,r0,0x017D\r
+ ori r3,r3,0x7840\r
+ b ..end\r
+..freq33:\r
+ addis r3,r0,0x01FC\r
+ ori r3,r3,0xA055\r
+ b ..end\r
+..freq40:\r
+ addis r3,r0,0x0262\r
+ ori r3,r3,0x5A00\r
+ b ..end\r
+..freq50:\r
+ addis r3,r0,0x02FA\r
+ ori r3,r3,0xF080\r
+ b ..end\r
+..freq66:\r
+ addis r3,r0,0x03F9\r
+ ori r3,r3,0x40AA\r
+ b ..end\r
+..freq80:\r
+ addis r3,r0,0x04C4\r
+ ori r3,r3,0xB400\r
+ b ..end\r
+..freq100:\r
+ addis r3,r0,0x05F5\r
+ ori r3,r3,0xE100\r
+ b ..end\r
+..freq125:\r
+ addis r3,r0,0x0773\r
+ ori r3,r3,0x5940\r
+ b ..end\r
+..freq133:\r
+ addis r3,r0,0x07F2\r
+ ori r3,r3,0x8155\r
+ b ..end\r
+..freq150:\r
+ addis r3,r0,0x08F0\r
+ ori r3,r3,0xD180\r
+ b ..end\r
+..freq166:\r
+ addis r3,r0,0x09EF\r
+ ori r3,r3,0x21AA\r
+ b ..end\r
+..freq175:\r
+ addis r3,r0,0x0A6E\r
+ ori r3,r3,0x49C0\r
+ b ..end\r
+..freq200:\r
+ addis r3,r0,0x0BEB\r
+ ori r3,r3,0xC200\r
+ b ..end\r
+..freq225:\r
+ addis r3,r0,0x0D69\r
+ ori r3,r3,0x3A40\r
+ b ..end\r
+..freq250:\r
+ addis r3,r0,0x0EE6\r
+ ori r3,r3,0xB280\r
+ b ..end\r
+..freq275:\r
+ addis r3,r0,0x1064\r
+ ori r3,r3,0x2AC0\r
+ b ..end\r
+..freq300:\r
+ addis r3,r0,0x11E1\r
+ ori r3,r3,0xA300\r
+ b ..end\r
+..freq3375:\r
+ addis r3,r0,0x141D\r
+ ori r3,r3,0xD760\r
+ b ..end\r
+..freq375:\r
+ addis r3,r0,0x165A\r
+ ori r3,r3,0x0BC0\r
+ b ..end\r
+..freq400:\r
+ addis r3,r0,0x17D7\r
+ ori r3,r3,0x8400\r
+ b ..end\r
+..freq433:\r
+ addis r3,r0,0x19CF\r
+ ori r3,r3,0x0E40\r
+ b ..end\r
+..freq466:\r
+ addis r3,r0,0x1BC6\r
+ ori r3,r3,0x9880\r
+ b ..end\r
+..freq500:\r
+ addis r3,r0,0x1DCD\r
+ ori r3,r3,0x6500\r
+..end: mtmsrd r10,1\r
+ isync\r
+ blr\r
+ function_epilog(timebase_speed_calc)\r
initobject cpc925.o
initobject cpc925_pci.o
+initobject cpc925_sdram.o
object cpc925.o
object cpc925_pci.o
+object cpc925_sdram.o
driver cpc925_northbridge.o
--- /dev/null
+#include "ppc970.h"
+
+unsigned long sdram_size(void)
+{
+ unsigned long addr1, addr2;
+
+ addr1=inint(NB_SDRAM_BASE+NB_SDRAM_MEMMODE7)&SDRAM_MEMMODE_BASEBANKADDR;
+ addr1=addr1<<11;
+ addr2=inint(NB_SDRAM_BASE+NB_SDRAM_MEMBOUNDAD7)&SDRAM_MEMBOUNDAD_BASEBANKADDR;
+ addr2=addr2<<3;
+ return(addr1|addr2);
+
+}
projects / coreboot.git / commitdiff