indent (left in tree since last indent action)

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/tyan/s2850/auto.c b/src/mainboard/tyan/s2850/auto.c
index 8dc498ce14a9217f125990e09fd5cf0c4e0fafe5..ab6c1c4fba9681148cc9faa0394cf1ec60ce0588 100644 (file)
--- a/src/mainboard/tyan/s2850/auto.c
+++ b/src/mainboard/tyan/s2850/auto.c
@@ -17,51 +17,52 @@
 #include "lib/delay.c"
 #include "cpu/p6/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c" 
+#include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c" 
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 static void hard_reset(void)
 {
-        set_bios_reset();
-        
-        /* enable cf9 */
-        pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
+       set_bios_reset();
+
+       /* enable cf9 */
+       pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1);
+       /* reset */
+       outb(0x0e, 0x0cf9);
 }
 
 static void soft_reset(void)
 {
-        set_bios_reset();
-        pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
+       set_bios_reset();
+       pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
 }
- 
+
 #define REV_B_RESET 0
 static void memreset_setup(void)
 {
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+       if (is_cpu_pre_c0()) {
+               outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (0 << 0), SMBUS_IO_BASE + 0xc0 + 16);       //REVC_MEMRST_EN=0
+       } else {
+               outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 16);       //REVC_MEMRST_EN=1
+       }
+       outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
+            (0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
+       if (is_cpu_pre_c0()) {
+               udelay(800);
+               outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 17);       //REVB_MEMRST_L=1
+               udelay(90);
+       }
 }
 
 
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
+static unsigned int generate_row(uint8_t node, uint8_t row,
+                                uint8_t maxnodes)
 {
        /* Routing Table Node i 
         *
@@ -85,7 +86,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
         *     [3] Route to Link 2
         */
 
-       uint32_t ret=0x00010101; /* default row entry */
+       uint32_t ret = 0x00010101;      /* default row entry */
 
 
        return ret;
@@ -93,9 +94,9 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-        /* nothing to do */
+       /* nothing to do */
 }
- 
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -113,47 +114,47 @@ static void main(void)
         */
        static const struct mem_controller cpu[] = {
                {
-                       .node_id = 0,
-                       .f0 = PCI_DEV(0, 0x18, 0),
-                       .f1 = PCI_DEV(0, 0x18, 1),
-                       .f2 = PCI_DEV(0, 0x18, 2),
-                       .f3 = PCI_DEV(0, 0x18, 3),
-                       .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-                       .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-               },
+                .node_id = 0,
+                .f0 = PCI_DEV(0, 0x18, 0),
+                .f1 = PCI_DEV(0, 0x18, 1),
+                .f2 = PCI_DEV(0, 0x18, 2),
+                .f3 = PCI_DEV(0, 0x18, 3),
+                .channel0 = {(0xa << 3) | 0, (0xa << 3) | 2, 0, 0},
+                .channel1 = {(0xa << 3) | 1, (0xa << 3) | 3, 0, 0},
+                },
        };
-        
+
        int needs_reset;
-        enable_lapic();
-        init_timer();
-        if (cpu_init_detected()) {
-                asm("jmp __cpu_reset");
-        }
-        distinguish_cpu_resets();
-        if (!boot_cpu()) {
-                stop_this_cpu();
-        }
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
-        setup_default_resource_map();
-        needs_reset = setup_coherent_ht_domain();
-        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-                soft_reset();
-        }      
+       enable_lapic();
+       init_timer();
+       if (cpu_init_detected()) {
+               asm("jmp __cpu_reset");
+       }
+       distinguish_cpu_resets();
+       if (!boot_cpu()) {
+               stop_this_cpu();
+       }
+       w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       uart_init();
+       console_init();
+       setup_default_resource_map();
+       needs_reset = setup_coherent_ht_domain();
+       needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+       if (needs_reset) {
+               print_info("ht reset -\r\n");
+               soft_reset();
+       }
 #if 0
        print_pci_devices();
 #endif
        enable_smbus();
 #if 0
-//     dump_spd_registers(&cpu[0]);
+//      dump_spd_registers(&cpu[0]);
        dump_smbus_registers();
 #endif
 
        memreset_setup();
-       sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+       sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
 
 #if 0
        dump_pci_devices();