This patch is about some noticable bugs which was made by no reason.

1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
  (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
      In rpr 5.10.2, step 2, step 2.1 & step 2.6
  (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
      instead of PCIEIND_P: 0x20.
      In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index 7b6d8fed8fdc374e2b86026f92854201035a898f..aa75a64f4f8a101d896fac4047f52d1a8f510ffb 100644 (file)
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -49,7 +49,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
 u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
 {
        /*get BAR3 base address for nbcfg0x1c */
-       u32 addr = pci_read_config32(nb_dev, 0x1c);
+       u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
        printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
                     dev->path.pci.devfn);
        addr |= dev->bus->secondary << 20 |     /* bus num */
@@ -62,7 +62,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
        u32 reg_old, reg;
 
        /*get BAR3 base address for nbcfg0x1c */
-       u32 addr = pci_read_config32(nb_dev, 0x1c);
+       u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
        /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
                     dev->path.pci.devfn);*/
        addr |= dev->bus->secondary << 20 |     /* bus num */

diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index e0fc59d5cf92364eab811cf1bcc1963f38da19aa..12fea1f2c9d3e120aef00a46ca33650f8a711be4 100644 (file)
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -212,8 +212,8 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
        set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0);     /* no description in datasheet. */
 
        /* init GPPSB port */
-       /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 0*/
-       set_pcie_enable_bits(dev, 0x70, 7 << 16, 0xd << 16);
+       /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 1*/
+       set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0xd << 16);
        /* PCIE initialization 5.10.2: rpr 2.4 */
        set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14);
        /* Do not gate the electrical idle from the PHY and enables the escape from L1L23 */
@@ -240,7 +240,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
        }
 
        /* step 5: dynamic slave CPL buffer allocation */
-       set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
+       set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 11, 1 << 11);
 
        /* step 5a: Training for GPP devices */
        /* init GPP */