default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 65536
+default XIP_ROM_SIZE = 64 * 1024
default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
arch i386 end
driver mainboard.o
config chip.h
chip northbridge/intel/i82810 # Northbridge
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device apic 0 on end # APIC
+ end
+ end
device pci_domain 0 on
device pci 0.0 on end # Host bridge
device pci 1.0 off # Onboard video
# end
end
chip southbridge/intel/i82801xx # Southbridge
- device pci 1e.0 on # PCI bridge
- # chip drivers/pci/onboard
- # device pci 1.0 on end
- # register "rom_address" = "0xfff80000"
- # end
- end
- device pci 1f.0 on # ISA bridge
- chip superio/winbond/w83627hf
- device pnp 2e.8 on # Floppy
- # io 0x60 = 0x3f0
- io 0x60 = 0x3f2
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA/LPC bridge
+ chip superio/winbond/w83627hf # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 2e.9 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.a on # Parallel port
+ device pnp 2e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
- device pnp 2e.b on # PS/2 keyboard/mouse
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2 (only header on board)
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # PS/2 keyboard/mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # Keyboard interrupt
irq 0x72 = 12 # Mouse interrupt
end
- device pnp 2e.c on end # Game port
- device pnp 2e.d on end # MIDI / MPU401
+ device pnp 2e.6 on end # Consumer IR (TODO)
+ device pnp 2e.7 on # Game port / MIDI / GPIO 1
+ io 0x60 = 0x201
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 on end # GPIO 2
+ device pnp 2e.9 on end # GPIO 3
+ device pnp 2e.a on end # ACPI
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
end
end
device pci 1f.1 on end # IDE
device pci 1f.2 on end # USB
device pci 1f.3 on end # SMBus
device pci 1f.5 on end # AC'97 audio
- device pci 1f.6 off end # AC'97 modem
+ device pci 1f.6 on end # AC'97 modem
end
end
- chip cpu/intel/socket_PGA370 # CPU
- end
end
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
-default HAVE_PIRQ_TABLE = 0 # FIXME
-default IRQ_SLOT_COUNT = 4 # FIXME
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
+default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
+default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
-default STACK_SIZE = 0x2000
-default HEAP_SIZE = 0x4000
default _RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3
+default TTYS0_LCS = 0x3 # 8n1
default DEFAULT_CONSOLE_LOGLEVEL = 9
default MAXIMUM_CONSOLE_LOGLEVEL = 9
default CONFIG_UDELAY_TSC = 1
default CONFIG_PCI_ROM_RUN = 1
end
-
extern struct chip_operations mainboard_msi_ms6178_ops;
struct mainboard_msi_ms6178_config {
- int nothing;
};
--- /dev/null
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router device */
+ 0x1c00, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x7000, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x1a, /* Checksum */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x1e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+ {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
+ {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ {0x00,(0x1f<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
option ROM_SIZE = 512 * 1024
# option ROM_SIZE = (512 * 1024) - (32 * 1024)
+option MAINBOARD_VENDOR = "MSI"
+option MAINBOARD_PART_NUMBER = "MS-6178"
+
+option IRQ_SLOT_COUNT = 4
+
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+option CONFIG_CONSOLE_VGA = 1
+option CONFIG_PCI_ROM_RUN = 1
+
romimage "normal"
option USE_FALLBACK_IMAGE = 0
option LINUXBIOS_EXTRA_VERSION = ".0Normal"
projects / coreboot.git / commitdiff