fix some southbridge warnings (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig
index 25e2c3aa5f84b717939a0b91a6e985dd58a9c990..daee034f0b647824b65c05043eaad171d7e5169e 100644 (file)
--- a/src/southbridge/intel/i82801ax/Kconfig
+++ b/src/southbridge/intel/i82801ax/Kconfig
@@ -20,4 +20,6 @@
 
 config SOUTHBRIDGE_INTEL_I82801AX
        bool
+       select HAVE_HARD_RESET
+       select USE_WATCHDOG_ON_BOOT
 

diff --git a/src/southbridge/intel/i82801ax/i82801ax_reset.c b/src/southbridge/intel/i82801ax/i82801ax_reset.c
index 239a727968023338d9271010676d5eb027ebdf4b..b30db9d9c0085bac8c8c6dd79f04a85f167834f5 100644 (file)
--- a/src/southbridge/intel/i82801ax/i82801ax_reset.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_reset.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <reset.h>
 #include <arch/io.h>
 
 void hard_reset(void)

diff --git a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
index fb45f521c568635b1efa98844f51a79f7fe99b17..6a3d4947e8e810338b146f64db3245e87f08250f 100644 (file)
--- a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
@@ -22,6 +22,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <watchdog.h>
 
 /* TODO: I'm fairly sure the same functionality is provided elsewhere. */
 

diff --git a/src/southbridge/intel/i82870/p64h2_pcibridge.c b/src/southbridge/intel/i82870/p64h2_pcibridge.c
index 3c1d418fb580c0e1929d24658ec2f34710bc9525..a489fe53f99cb760126b27187637378715199972 100644 (file)
--- a/src/southbridge/intel/i82870/p64h2_pcibridge.c
+++ b/src/southbridge/intel/i82870/p64h2_pcibridge.c
@@ -8,13 +8,12 @@
 
 static void p64h2_pcix_init(device_t dev)
 {
-       uint32_t dword;
-       uint16_t word;
-       uint8_t byte;
+       u32 dword;
+       u8 byte;
 
-
-       /* The purpose of changes to HCCR, ACNF, and MTT is to speed up the 
-          PCI bus for cards having high speed transfers. */
+       /* The purpose of changes to HCCR, ACNF, and MTT is to speed
+        * up the PCI bus for cards having high speed transfers.
+        */
        dword = 0xc2040002;
        pci_write_config32(dev, HCCR, dword);
        dword = 0x0000c3bf;
@@ -37,4 +36,4 @@ static const struct pci_driver pcix_driver __pci_driver = {
         .vendor = PCI_VENDOR_ID_INTEL,
         .device = PCI_DEVICE_ID_INTEL_82870_1F0,
 };      
-  
+