Fix for Erratum 343 for AMD Fam10h CPUs.

Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 162680db733c7714863d6fef851b00e81ed47c3f..94990a66f7d133e88b523479fbde5622ec00da81 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -27,6 +27,8 @@
 /* for CAR_FAM10 */
 #define CacheSizeAPStack 0x400 /* 1K */
 
+#define MSR_FAM10      0xC001102A
+
 #define jmp_if_k8(x)   comisd  %xmm2, %xmm1; jb x
 
 #define CPUID_MASK             0x0ff00f00
@@ -122,6 +124,22 @@ CAR_FAM10_out:
        bts     $15, %eax
        wrmsr
 
+       /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
+
+       /* read-address has to be stored in the ecx register */
+       movl    $MSR_FAM10, %ecx
+
+       /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
+       rdmsr
+
+       /* Set bit 35 to 1 in EAX */
+       bts     $35, %eax
+
+       /* write back the modified register EDX:EAX to the MSR specified in ECX */
+       wrmsr
+
+       /* Erratum 343 end */
+
 CAR_FAM10_out_post_errata:
 
        /* Set MtrrFixDramModEn for clear fixed mtrr */

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index ce8ef19647025c31c2034c79fe187b47ea9f6fa0..89366e0e3307f784c06e8b13cf6a7542f212ee33 100644 (file)
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -23,7 +23,19 @@ static void inline __attribute__((always_inline))  memcopy(void *dest, const voi
                 : "S" (src), "D" (dest), "c" ((bytes)>>2)
                 );
 }
+/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
 
+static void vErrata343(void)
+{
+    msr_t msr;
+    unsigned int uiMask = 0xFFFFFFF7;
+
+#ifdef BU_CFG2_MSR
+    msr = rdmsr(BU_CFG2_MSR);
+    msr.hi &= uiMask; // set bit 35 to 0
+    wrmsr(BU_CFG2_MSR, msr);
+#endif
+}
 
 static void post_cache_as_ram(void)
 {
@@ -56,6 +68,8 @@ static void post_cache_as_ram(void)
        print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
 
        /* from here don't store more data in CAR */
+       vErrata343();
+
 #if 0
         __asm__ volatile (
                "pushl  %eax\n\t"

diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h
index db3019c54d7031f038113a9a673daba76187f06c..c885493ef0756af3f3d861f437eb705ff05ca98c 100644 (file)
--- a/src/include/cpu/amd/model_10xxx_msr.h
+++ b/src/include/cpu/amd/model_10xxx_msr.h
@@ -26,6 +26,7 @@
 #define IC_CFG_MSR                     0xC0011021
 #define DC_CFG_MSR                     0xC0011022
 #define BU_CFG_MSR                     0xC0011023
+#define BU_CFG2_MSR                    0xC001102A
 
 #define CPU_ID_FEATURES_MSR            0xC0011004
 #define CPU_ID_HYPER_EXT_FEATURES      0xC001100d