/* **/
/* ***************************************************************************/
static void
-BIST(void){
+BIST(void)
+{
int msrnum;
msr_t msr;
msrnum = CPU_DM_BIST;
wrmsr(msrnum, msr);
- outb(POST_CPU_DM_BIST_FAILURE , 0x80); /* 0x29*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
+ outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
msr.lo &= 0x0F3FF0000;
if (msr.lo != 0xfeff0000)
goto BISTFail;
msrnum = CPU_FP_UROM_BIST;
wrmsr(msrnum, msr);
- outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
- inb(0x80); /* IO delay*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
+ outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
+ inb(0x80); /* IO delay*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
while ((msr.lo&0x884) != 0x884)
- msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
+ msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
if ((msr.lo&0x642) != 0x642)
goto BISTFail;
-
- msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
+ msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
msrnum = CPU_FP_UROM_BIST;
wrmsr(msrnum, msr);
-
/* BTB*/
msr.lo = 0x000000303;
msr.hi = 0x000000000;
msrnum = CPU_PF_BTBRMA_BIST;
wrmsr(msrnum, msr);
- outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
+ outb(POST_CPU_BTB_BIST_FAILURE, 0x80); /* 0x8A*/
+ msr = rdmsr(msrnum); /* read back for pass fail*/
if ((msr.lo & 0x3030) != 0x3030)
goto BISTFail;
return;
-
BISTFail:
print_err("BIST failed!\n");
while(1);
}
+
+void BTM_enable(void)
+{
+ int msrnum;
+ msr_t msr;
+ /* Set Diagnostic Mode */
+ msrnum = CPU_GLD_MSR_DIAG;
+ msr.hi = 0;
+ msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
+ wrmsr(msrnum, msr);
+
+ /* Set up GLCP to grab BTM data.*/
+ msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
+ msr.hi = 0x0;
+ msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
+ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
+
+ /* ;Turn off debug clock*/
+ msrnum = 0x04C000016; /* DBG_CLK_CTL*/
+ msr.lo = 0x00; /* No clock*/
+ msr.hi = 0x00;
+ wrmsr(msrnum, msr);
+
+ /* ;Set debug clock to CPU*/
+ msrnum = 0x04C000016; /* DBG_CLK_CTL*/
+ msr.lo = 0x01; /* CPU CLOCK*/
+ msr.hi = 0x00;
+ wrmsr(msrnum, msr);
+
+ /* ;Set fifo ctl to BTM bits wide*/
+ msrnum = 0x04C00005E; /* FIFO_CTL*/
+ msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit,
+ * 01= 32 bit, 00 = 16bit),
+ * Bit [23:21] are position (100 = CPU downto0)*/
+ wrmsr(msrnum, msr); /* */
+ /* Bit [19] sets it up in slow data mode.*/
+
+ /* ;enable fifo loading - BTM sizing will constrain*/
+ /* ; only valid BTM packets to load - this action should always be on*/
+ msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
+ msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
+ msr.hi = 0x000000000; /* */
+ wrmsr(msrnum, msr);
+
+ /* ;start storing diag data in the fifo*/
+ msrnum = 0x04C00005F; /* DIAG CTL*/
+ msr.lo = 0x080000000; /* enable actions*/
+ msr.hi = 0x000000000;
+ wrmsr(msrnum, msr);
+
+ /* Set up delay on data lines, so that the hold time*/
+ /* is 1 ns.*/
+ msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
+ msr.lo = 0x082b5ad68;
+ msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
+ wrmsr(msrnum, msr);
+
+ /* Set up DF to output diag information on DF pins.*/
+ msrnum = DF_GLD_MSR_MASTER_CONF;
+ msr.lo = 0x0220;
+ msr.hi = 0;
+ wrmsr(msrnum, msr);
+
+ msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
+ msr.hi = 0x0;
+ msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
+ wrmsr(msrnum, msr);
+ /* end of code for BTM */
+}
+
/* ***************************************************************************/
/* * cpuRegInit*/
/* ***************************************************************************/
void
-cpuRegInit (void){
+cpuRegInit (void)
+{
int msrnum;
msr_t msr;
/* Turn on BTM for early debug based on setup. */
/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
{
- /* Set Diagnostic Mode */
- msrnum = CPU_GLD_MSR_DIAG;
- msr.hi = 0;
- msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
- wrmsr(msrnum, msr);
-
- /* Set up GLCP to grab BTM data.*/
- msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
- msr.hi = 0x0;
- msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
- wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
-
- /* ;Turn off debug clock*/
- msrnum = 0x04C000016; /* DBG_CLK_CTL*/
- msr.lo = 0x00; /* No clock*/
- msr.hi = 0x00;
- wrmsr(msrnum, msr);
-
- /* ;Set debug clock to CPU*/
- msrnum = 0x04C000016; /* DBG_CLK_CTL*/
- msr.lo = 0x01; /* CPU CLOCK*/
- msr.hi = 0x00;
- wrmsr(msrnum, msr);
-
- /* ;Set fifo ctl to BTM bits wide*/
- msrnum = 0x04C00005E; /* FIFO_CTL*/
- msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
- wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
- /* Bit [19] sets it up in slow data mode.*/
-
- /* ;enable fifo loading - BTM sizing will constrain*/
- /* ; only valid BTM packets to load - this action should always be on*/
-
- msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
- msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
- msr.hi = 0x000000000; /* */
- wrmsr(msrnum, msr);
-
- /* ;start storing diag data in the fifo*/
- msrnum = 0x04C00005F; /* DIAG CTL*/
- msr.lo = 0x080000000; /* enable actions*/
- msr.hi = 0x000000000;
- wrmsr(msrnum, msr);
-
- /* Set up delay on data lines, so that the hold time*/
- /* is 1 ns.*/
- msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
- msr.lo = 0x082b5ad68;
- msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
- wrmsr(msrnum, msr);
-
- /* Set up DF to output diag information on DF pins.*/
- msrnum = DF_GLD_MSR_MASTER_CONF;
- msr.lo = 0x0220;
- msr.hi = 0;
- wrmsr(msrnum, msr);
-
- msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
- msr.hi = 0x0;
- msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
- wrmsr(msrnum, msr);
- /* end of code for BTM */
+ BTM_enable();
}
/* Enable Suspend on Halt*/
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
-
-/* Only do this if we are building for 5535*/
-/* */
-/* FooGlue Setup*/
-/* */
-#if 1
- /* Enable CIS mode B in FooGlue*/
+ /* Enable CIS mode C */
msrnum = MSR_FG + 0x10;
msr = rdmsr(msrnum);
msr.lo &= ~3;
- msr.lo |= 2; /* ModeB*/
+ msr.lo |= 2;
wrmsr(msrnum, msr);
-#endif
-/* */
-/* Disable DOT PLL. Graphics init will enable it if needed.*/
-/* */
+ /* Disable DOT PLL. Graphics init will enable it if needed.*/
msrnum = GLCP_DOTPLL;
msr = rdmsr(msrnum);
msr.lo |= DOTPPL_LOWER_PD_SET;
wrmsr(msrnum, msr);
-/* */
-/* Enable RSDC*/
-/* */
+ /* Enable RSDC and other SMM instructions */
msrnum = 0x1301 ;
msr = rdmsr(msrnum);
msr.lo |= 0x08;
wrmsr(msrnum, msr);
-
-/* */
-/* BIST*/
-/* */
+ /* BIST*/
/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
{
-// BIST();
+ //BIST();
}
-
-/* */
-/* Enable BTB*/
-/* */
+ /* Enable BTB*/
/* I hate to put this check here but it doesn't really work in cpubug.asm*/
msrnum = MSR_GLCP+0x17;
msr = rdmsr(msrnum);
wrmsr(msrnum, msr);
}
-/* */
-/* FPU impercise exceptions bit*/
-/* */
+ /* FPU impercise exceptions bit*/
/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
{
msrnum = CPU_FPU_MSR_MODE;
wrmsr(msrnum, msr);
}
-/* */
-/* Cache Overides*/
-/* */
+ /* Cache Overides*/
/* Allow NVRam to override DM Setup*/
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
{
}
}
-
-
-
/* ***************************************************************************/
/* **/
/* * MTestPinCheckBX*/
/* **/
/* ***************************************************************************/
static void
-MTestPinCheckBX (void){
+MTestPinCheckBX (void)
+{
int msrnum;
msr_t msr;
__asm__ volatile (
"push %ax\n"
"mov $0x5000, %ax\n"
+ /* smint */
".byte 0x0f, 0x38\n"
"pop %ax\n"
);
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Enable the local cpu apics */
- //setup_lapic();
-
+ /* send SYS_END_OF_POST to VSM */
vsm_end_post_smi();
printk_debug("model_gx2_init DONE\n");
-/* ***************************************************************************/
-/* **/
-/* * StartTimer1*/
-/* **/
-/* * Entry: none*/
-/* * Exit: Starts Timer 1 for port 61 use*/
-/* * Destroys: Al,*/
-/* **/
-/* ***************************************************************************/
void
-StartTimer1(void){
+StartTimer1(void)
+{
outb(0x56, 0x43);
outb(0x12, 0x41);
}
void
-SystemPreInit(void){
+SystemPreInit(void)
+{
/* they want a jump ... */
__asm__("jmp .+2\ninvd\njmp.+2\n");
/* This is chip specific!*/
#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
-#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
-#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/
+#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
+#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/
#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO*/
#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO*/
#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/
#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/
-#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/
-#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/
+#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/
+#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/
#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/
#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/
-#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/
+#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/
/* definitions that are "once you are mostly up, start VSA" type things */
#define SMM_OFFSET 0x40400000
}
static void enable_shadow(device_t dev)
-{
-
+{
}
static void northbridge_init(device_t dev)
while (gl->desc_type != GL_END){
switch(gl->desc_type){
default:
- printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported type: ", __FUNCTION__,
- gl->desc_name, gl->desc_type, gl->hi, gl->hi);
- printk_err("Must be %x, %x, %x, %x, %x, or %x\n", SC_SHADOW,R_SYSMEM,BMO_DMM,
- BM_DMM, BMO_SMM,BM_SMM);
-
+ printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported type: ",
+ __FUNCTION__, gl->desc_name, gl->desc_type, gl->hi, gl->hi);
+ printk_err("Must be %x, %x, %x, %x, %x, or %x\n",
+ SC_SHADOW,R_SYSMEM,BMO_DMM, BM_DMM, BMO_SMM,BM_SMM);
case SC_SHADOW: /* Check for a Shadow entry*/
ShadowInit(gl);
break;
SysmemInit(gl);
break;
- case BMO_DMM: /* check for a DMM entry*/
+ case BMO_DMM: /* check for a DMM entry*/
DMMGL0Init(gl);
break;
#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
/* build initializer for P2D MSR */
-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}
-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}
-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}
-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}
-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}
-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}
-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, .hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}
-
-
+#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \
+ {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}
+#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \
+ {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}
+#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \
+ {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}
+#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \
+ {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}
+#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \
+ {msr, .hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}
+#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \
+ {msr, .hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}
+#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \
+ {msr, .hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}
struct msr_defaults {
int msr_no;
//{0x1811, .hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)},
//{0x1812, .hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)},
//{0x1813, .hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)},
- /* now for GLPCI routing */
+
+ /* GeodeLink Routing */
/* GLIU0 */
- P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
+ /* Traditional Memory 0kB-512kB goes to GLIU port 1, Memory Controller */
+ P2D_BM(0x10000020, 0x1, 0x0, 0x00000, 0xfff80),
+ /* Traditional Memory 512kB-1MB goes to GLIU port 1, Memory Controller */
P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0x3),
+ /* Extended Memory, 0xC0000-0x100000, disable write,
+ * enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
+ * goest to GLIU Port 1, Memory Controller */
+ P2D_SC(0x1000002c, 0x1, 0x0, 0x0000, 0xff03, 0x3),
/* GLIU1 */
- P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
+ /* Traditional Memory 0kB-512kB goes to GLIU port 1, link to GLIU0 */
+ P2D_BM(0x40000020, 0x1, 0x0, 0x00000, 0xfff80),
+ /* Traditional Memory 512kB-1MB goes to GLIU port 1, link to GLIU0 */
P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0x3),
+ /* Extended Memory, 0xC0000-0x100000, disable write,
+ * enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
+ * goest to GLIU Port 1, Memory Controller */
+ P2D_SC(0x4000002d, 0x1, 0x0, 0x0000, 0xff03, 0x3),
+ /* end of table */
{0}
};
#define SMM_OFFSET 0x40400000
#define SMM_SIZE 256
-/* we have to do this here. We have not found a nicer way to do it */
+/*
+ * FixME: MSR 0x10000028, 0x40000029 are reprogrammed by SysmemInit()
+ * 0x10000026 and 0x400000023 are reprogrammed by SMMGL0Init() and SMMGL1Init()
+ */
void
setup_gx2(void)
{
membytes = sizem * 1048576;
/* we need to set 0x10000028 and 0x40000029 */
- // print_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
+ //print_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
msr.hi = 0x20000000 | membytes>>24;
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
wrmsr(0x10000028, msr);
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
wrmsr(0x40000029, msr);
msr = rdmsr(0x10000028);
- // print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
+ //print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
msr = rdmsr(0x40000029);
- // print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
-
+ //print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
/* fixme: SMM MSR 0x10000026 and 0x400000023 */
/* calculate the OFFSET field */
/* calculate the PBASE and PMASK fields */
tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
- // print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+ //print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
msr.hi = tmp;
msr.lo = tmp2;
wrmsr(0x10000026, msr);
msr.lo = 0xfbf00100;
wrmsr(0x10000028, msr);
msr = rdmsr(0x10000028);
- // print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
+ //print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
wrmsr(0x40000029, msr);
msr = rdmsr(0x40000029);
- // print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
+ //print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
msr.hi = 0x2cfbc040;
msr.lo = 0x400fffc0;
wrmsr(0x10000026, msr);
msr = rdmsr(0x10000026);
- // print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
+ //print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
msr.hi = 0x22fffc02;
msr.lo = 0x10ffbf00;
wrmsr(0x1808, msr);
msr = rdmsr(0x1808);
- // print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
+ //print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
#endif
/* now do the default MSR values */
* MSR 0x51400014 bit 18:16
* 3. Enable UART controller
* MSR 0x5140003A bit 0, 1
- * 4. IRQ routing on IRQ Mapper
+ * 4. IRQ routing on IRQ Mapper (before loading OS)
* MSR 0x51400021 bit [27:24]
*/
msr_t msr;
projects / coreboot.git / commitdiff