* src/vm/jit/sparc64/codegen.h: Removed asserts for stores with sethi.

* src/vm/jit/sparc64/codegen.c: Added code to fill with nops when a patcher is right at the
end of a basic block.

* src/vm/jit/sparc64/asmpart.S (asm_vm_call_method_end): Returning 0 when an exception occurs.

* src/vm/jit/sparc64/md.c (md_get_method_patch_address): Improved handling of mptr loads when
a sethi is involved.

diff --git a/src/vm/jit/sparc64/asmpart.S b/src/vm/jit/sparc64/asmpart.S
index ce7a16fda60822ab24b3c126edff6710207803b3..975b4860e3052eb4f6a74f4412d1f24b825f1360 100644 (file)
--- a/src/vm/jit/sparc64/asmpart.S
+++ b/src/vm/jit/sparc64/asmpart.S
@@ -67,6 +67,8 @@
  *                                                                         *
  * This function calls a Java-method (which possibly needs compilation)    *
  *
+ * If the java method is throwing an exception, NULL will be returned.
+ *
  * C-prototype:
  *  java_objectheader *asm_vm_call_method(methodinfo *m, s4 vmargscount,
  *                                              vm_arg *vmargs);
@@ -213,7 +215,7 @@ asm_vm_call_method_exception_handler:
        nop
        return  %i7 + 8                          /* implicit window restore */
 asm_vm_call_method_end:
-       nop
+       mov    zero,%o0                  /* delay: return NULL      */
        
 
 

diff --git a/src/vm/jit/sparc64/codegen.c b/src/vm/jit/sparc64/codegen.c
index df4212e37183a491ab8972c64d3ff9750880a551..74912fbab76053efd529ddcaebdde4ab43e96a74 100644 (file)
--- a/src/vm/jit/sparc64/codegen.c
+++ b/src/vm/jit/sparc64/codegen.c
@@ -179,7 +179,7 @@ bool codegen_emit(jitdata *jd)
        */
 
        if (checksync && (m->flags & ACC_SYNCHRONIZED))
-               (void) dseg_add_unique_s4(cd, (rd->memuse + 1) * 8); /* IsSync        */
+               (void) dseg_add_unique_s4(cd, JITSTACK + (rd->memuse + 1) * 8); /* IsSync */
        else
 #endif
                (void) dseg_add_unique_s4(cd, 0);                  /* IsSync          */
@@ -2978,8 +2978,19 @@ gen_method:
        } /* switch */
                
        } /* for instruction */
+
+       MCODECHECK(64);
        
+       /* At the end of a basic block we may have to append some nops,
+          because the patcher stub calling code might be longer than the
+          actual instruction. So codepatching does not change the
+          following block unintentionally. */
 
+       if (cd->mcodeptr < cd->lastmcodeptr) {
+               while (cd->mcodeptr < cd->lastmcodeptr) {
+                       M_NOP;
+               }
+       }
                
        } /* if (bptr -> flags >= BBREACHED) */
        } /* for basic block */

diff --git a/src/vm/jit/sparc64/codegen.h b/src/vm/jit/sparc64/codegen.h
index 2f4820066cf69684230cf830c9dbb7d428e91204..9acf13b8b6a11bac0b70deed87a3630f297ab1f6 100644 (file)
--- a/src/vm/jit/sparc64/codegen.h
+++ b/src/vm/jit/sparc64/codegen.h
@@ -494,8 +494,7 @@ s4   get_lopart_disp(s4 disp);
         } \
         else { \
             DO_SETHI_PART(disp,rs,REG_ITMP3); \
-            M_STX_INTERN(rd,REG_ITMP3,setlo_part(disp)); \
-                       assert(0); \
+            M_STX_INTERN(rd,REG_ITMP3,get_lopart_disp(disp)); \
         } \
     } while (0)
 
@@ -508,8 +507,7 @@ s4   get_lopart_disp(s4 disp);
        } \
         else { \
             DO_SETHI_PART(disp,rs,REG_ITMP3); \
-            M_IST_INTERN(rd,REG_ITMP3,setlo_part(disp)); \
-                       assert(0); \
+            M_IST_INTERN(rd,REG_ITMP3,get_lopart_disp(disp)); \
         } \
     } while (0)
 

diff --git a/src/vm/jit/sparc64/md.c b/src/vm/jit/sparc64/md.c
index efb6f9f21c70df82920ae8df2d423b8ec4238e5a..af5c148fe7cccbb28c10037cae10c4d8b5942134 100644 (file)
--- a/src/vm/jit/sparc64/md.c
+++ b/src/vm/jit/sparc64/md.c
@@ -151,7 +151,6 @@ u1 *md_codegen_get_pv_from_pc(u1 *ra)
 {
        u1 *pv;
        u8  mcode;
-       u4  mcode_masked;
        s4  offset;
 
        pv = ra;
@@ -197,73 +196,84 @@ u1 *md_codegen_get_pv_from_pc(u1 *ra)
 
    INVOKESTATIC/SPECIAL:
 
-   dfdeffb8    ldx      [i5 - 72],o5
-   03c0f809    jmp      o5
-   00000000    nop
+   ????????    ldx      [i5 - 72],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
+
+   w/ sethi (mptr in dseg out of 13-bit simm range)
+
+   ????????    sethi    hi(0x2000),o5
+   ????????    sub      i5,o5,o5
+   ????????    ldx      [o5 - 72],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
 
    INVOKEVIRTUAL:
 
-   dc990000    ld       t9,0(a0)
-   df3e0000    ld       [g2 + 0],o5
-   03c0f809    jmp      o5
-   00000000    nop
+   ????????    ldx      [o0 + 0},g2
+   ????????    ldx      [g2 + 0],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
 
    INVOKEINTERFACE:
 
-   dc990000    ld       t9,0(a0)
-   df39ff90    ld       [g2 - 112],g2
-   df3e0018    ld       [g2 + 24],o5
-   03c0f809    jmp      o5
-   00000000    nop
+   ????????    ldx      [o0 + 0},g2
+   ????????    ldx      [g2 - 112],g2
+   ????????    ldx      [g2 + 24],o5
+   ????????    jmp      o5             <-- ra
+   ????????    nop
 
 *******************************************************************************/
 
 u1 *md_get_method_patch_address(u1 *ra, stackframeinfo *sfi, u1 *mptr)
 {
-       u4  mcode, mcode_masked;
+       u4  mcode, mcode_sethi, mcode_masked;
        s4  offset;
        u1 *pa, *iptr;
 
        /* go back to the location of a possible sethi (3 instruction before jump) */
        /* note: ra is the address of the jump instruction on SPARC                */
-       iptr = ra - 3 * 4;
 
-       /* get first instruction word on current PC */
-
-       mcode = *((u4 *) iptr);
+       mcode_sethi = *((u4 *) (ra - 3 * 4));
 
        /* check for sethi instruction */
 
-       if (IS_SETHI(mcode)) {
-               /* XXX write a regression for this */
+       if (IS_SETHI(mcode_sethi)) {
+               u4 mcode_sub, mcode_ldx;
+
+               mcode_sub = *((u4 *) (ra - 2 * 4));
+               mcode_ldx = *((u4 *) (ra - 1 * 4));
+
+               /* make sure the sequence of instructions is a loadhi */
+               if ((IS_SUB(mcode_sub)) && (IS_LDX_IMM(mcode_ldx)))
+               {
+
 
                /* get 22-bit immediate of sethi instruction */
 
-               offset = (s4) (mcode & 0x3fffff);
+               offset = (s4) (mcode_sethi & 0x3fffff);
                offset = offset << 10;
                
                /* goto next instruction */
-               iptr += 4;
-               mcode = *((u4 *) iptr);
                
                /* make sure it's a sub instruction (pv - big_disp) */
-               assert(IS_SUB(mcode));
+               assert(IS_SUB(mcode_sub));
                offset = -offset;
 
                /* get displacement of load instruction */
 
-               mcode = *((u4 *) (ra - 1 * 4));
-               assert(IS_LDX_IMM(mcode));
+               assert(IS_LDX_IMM(mcode_ldx));
 
-               offset += decode_13bit_imm(mcode);
+               offset += decode_13bit_imm(mcode_ldx);
                
                pa = sfi->pv + offset;
 
                return pa;
+               }
        }
 
-
-       /* simple (one-instruction) load */
+       /* we didn't find a sethi, or it didn't belong to a loadhi */
+       /* check for simple (one-instruction) load */
        iptr = ra - 1 * 4;
        mcode = *((u4 *) iptr);
 
@@ -324,6 +334,8 @@ void md_cacheflush(u1 *addr, s4 nbytes)
 void md_dcacheflush(u1 *addr, s4 nbytes)
 {
        /* XXX don't know yet */        
+       /* printf("md_dcacheflush\n"); */
+       __asm__ __volatile__ ( "membar 0x7F" : : : "memory" );
 }