object acpi_tables.o
makerule dsdt.c
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
- action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
+ action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
+ action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
action "mv $(CURDIR)/dsdt.hex dsdt.c"
end
object ./dsdt.o
device pci_domain 0 on
device pci 00.0 on end # host bridge
- device pci 01.0 off end # i945 PCIe root port
+ # autodetect 0:1.0 because it might or might not be there.
+ # device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard
device pci 02.0 on end # vga controller
# register "rom_address" = "0xfffc0000" # 256 KB image
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1"
+ register "gpe0_en" = "0x00000400"
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
config MAINBOARD_PART_NUMBER
string
- default "986LCD-M/mITX"
+ default "986LCD-M"
depends on BOARD_KONTRON_986LCD_M
config MMCONF_BASE_ADDRESS
ifdef POST_EVALUATION
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ $(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src)/mainboard/$(MAINBOARDDIR) $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl -o $(obj)/dsdt.asl
+ iasl -p dsdt -tc $(obj)/dsdt.asl
mv dsdt.hex $@
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## CONFIG_DEBUG 8 debug-level messages
+## DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
{
Name(_HID, EISAID("PNP0501"))
Name(_UID, 1)
+ Name(_DDN, "COM1")
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ } EndDependentFn()
+ })
+
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ })
+ }
// Some methods need an implementation here:
// missing: _STA, _DIS, _CRS, _PRS,
// missing: _SRS, _PS0, _PS3
{
Name(_HID, EISAID("PNP0501"))
Name(_UID, 2)
+ Name(_DDN, "COM2")
+
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ } EndDependentFn()
+ })
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ })
+ }
// Some methods need an implementation here:
// missing: _STA, _DIS, _CRS, _PRS,
// missing: _SRS, _PS0, _PS3
#include <cpu/x86/msr.h>
#include "dmi.h"
-#define OLD_ACPI 0
-
extern unsigned char AmlCode[];
#if HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
void generate_cpu_entries(void); // from cpu/intel/speedstep
-unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
-
-#if OLD_ACPI
-typedef struct acpi_oemb {
- acpi_header_t header;
- u8 ss;
- u16 iost;
- u32 topm;
- u32 roms;
- u32 mg1b;
- u32 mg1l;
- u32 mg2b;
- u32 mg2l;
- u8 rsvd;
- u8 dmax;
- u32 hpta;
- u32 cpb0;
- u32 cpb1;
- u32 cpb2;
- u32 cpb3;
- u8 assb;
- u8 aotb;
- u32 aaxb;
- u8 smif;
- u8 dtse;
- u8 dts1;
- u8 dts2;
- u8 mpen;
-} __attribute__((packed)) acpi_oemb_t;
-#endif
-
-typedef struct acpi_gnvs {
- // 0x00
- u16 osys;
- u8 smif;
- u8 reserved[13];
- // 0x10
- u8 mpen;
-} __attribute__((packed)) acpi_gnvs_t;
-
-#if OLD_ACPI
-void acpi_create_oemb(acpi_oemb_t *oemb)
-{
- acpi_header_t *header = &(oemb->header);
- unsigned long tolud;
-
- memset (oemb, 0, sizeof(*oemb));
-
- /* fill out header fields */
- memcpy(header->signature, "OEMB", 4);
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, "COREBOOT", 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
-
- header->length = sizeof(acpi_oemb_t);
- header->revision = 1;
-
- oemb->ss = 0x09; // ss1 + ss 4
- oemb->iost = 0x0403; // ??
-
- tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c);
- oemb->topm = tolud;
-
- oemb->roms = 0xfff00000; // 1M hardcoded
-
- oemb->mg1b = 0x000d0000;
- oemb->mg1l = 0x00010000;
- oemb->mg2b = tolud;
- oemb->mg2l = 0-tolud;
-
- oemb->dmax = 0x87;
- oemb->hpta = 0x000e36c0;
-
- header->checksum =
- acpi_checksum((void *) oemb, sizeof(acpi_oemb_t));
-
-};
-#endif
-
-void acpi_create_gnvs(acpi_gnvs_t *gnvs)
+#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
- gnvs->mpen = 1;
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+
+ /* Enable both COM ports */
+ gnvs->cmap = 0x01;
+ gnvs->cmbp = 0x01;
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
}
-void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
{
#define HPET_ADDR 0xfed00000ULL
acpi_header_t *header = &(hpet->header);
#if HAVE_ACPI_SLIC
acpi_header_t *slic;
#endif
-#if OLD_ACPI
- acpi_oemb_t *oemb;
-#endif
- acpi_gnvs_t *gnvs;
acpi_header_t *ssdt;
acpi_header_t *dsdt;
ALIGN_CURRENT;
acpi_add_table(rsdp, mcfg);
-#if OLD_ACPI
- printk_debug("ACPI: * OEMB\n");
- oemb=(acpi_oemb_t *)current;
- current += sizeof(acpi_oemb_t);
- ALIGN_CURRENT;
- acpi_create_oemb(oemb);
- acpi_add_table(rsdp, oemb);
-#endif
-
printk_debug("ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
memcpy((void *) dsdt, (void *) AmlCode,
((acpi_header_t *) AmlCode)->length);
-#if OLD_ACPI
- for (i=0; i < dsdt->length; i++) {
- if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBEEF) {
- printk_debug("ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb);
- *(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb;
- break;
- }
- }
-#endif
-
ALIGN_CURRENT;
/* Pack GNVS into the ACPI table area */
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#include "southbridge/intel/i82801gx/i82801gx.h"
static void setup_ich7_gpios(void)
{
- /* TODO: This is highly board specific and should be moved */
printk_debug(" GPIOS...");
/* General Registers */
outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
dev=PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
+
+ pnp_write_config(dev, 0x29, 0x43); // GPIO settings
+ pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
+
+ dev=PNP_DEV(0x2e, W83627THG_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
static void rcba_config(void)
{
+ u32 reg32;
+
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
+ /* Now, this is a bit ugly. As per PCI specification, function 0 of a
+ * device always has to be implemented. So disabling ethernet port 1
+ * would essentially disable all three ethernet ports of the mainboard.
+ * It's possible to rename the ports to achieve compatibility to the
+ * PCI spec but this will confuse all (static!) tables containing
+ * interrupt routing information.
+ * To avoid this, we enable (unused) port 6 and swap it with port 1
+ * in the case that ethernet port 1 is disabled. Since no devices
+ * are connected to that port, we don't have to worry about interrupt
+ * routing.
+ */
+ int port_shuffle = 0;
+
/* Disable unused devices */
- RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
- RCBA32(0x3418) |= (1 << 0); // Required.
+ reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
+ reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
+
+ if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) {
+ printk_debug("Disabling ethernet adapter 1.\n");
+ reg32 |= FD_PCIE1;
+ }
+ if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) {
+ printk_debug("Disabling ethernet adapter 2.\n");
+ reg32 |= FD_PCIE2;
+ } else {
+ if (reg32 & FD_PCIE1)
+ port_shuffle = 1;
+ }
+ if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) {
+ printk_debug("Disabling ethernet adapter 3.\n");
+ reg32 |= FD_PCIE3;
+ } else {
+ if (reg32 & FD_PCIE1)
+ port_shuffle = 1;
+ }
+
+ if (port_shuffle) {
+ /* Enable PCIE6 again */
+ reg32 &= ~FD_PCIE6;
+ /* Swap PCIE6 and PCIE1 */
+ RCBA32(RPFN) = 0x00043215;
+ }
+
+ reg32 |= 1;
+
+ RCBA32(0x3418) = reg32;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
#include "southbridge/intel/i82801gx/cmos_failover.c"
#endif
+#include <cbmem.h>
+
+// Now, this needs to be included because it relies on the symbol
+// __ROMCC_ being set during CAR stage (in order to compile the
+// BSS free versions of the functions). Either rewrite the code
+// to be always BSS free, or invent a flag that's better suited than
+// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+//
+#include "lib/cbmem.c"
+
void real_main(unsigned long bist)
{
u32 reg32;
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk_debug("PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
-#if HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME
printk_debug("Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+
#else
printk_debug("Resume from S3 detected, but disabled.\n");
#endif
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
+#if !CONFIG_HAVE_ACPI_RESUME
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
#if defined(DEBUG_RAM_SETUP)
sdram_dump_mchbar_registers();
printk_debug("TOM: 0x%08x\n", tom);
ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, tom);
+ //ram_check(0x00100000, tom);
}
#endif
+#endif
+
MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Start address of high memory tables */
+ unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+ if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+ /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+ * through stage 2. We could keep stuff like stack and heap in high tables
+ * memory completely, but that's a wonderful clean up task for another
+ * day.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ }
+#endif
}
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
# coreboot config options: bootloader
416 512 s 0 boot_devices
-#928 80 r 0 unused
+#928 40 r 0 unused
+
+# coreboot config options: mainboard specific options
+948 2 e 8 cpufan_cruise_control
+950 2 e 8 sysfan_cruise_control
+952 4 e 9 cpufan_speed
+#956 4 e 10 cpufan_temperature
+960 4 e 9 sysfan_speed
+#964 4 e 10 sysfan_temperature
+
+968 1 e 2 ethernet1
+969 1 e 2 ethernet2
+970 1 e 2 ethernet3
+
+#971 13 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
7 0 Disable
7 1 Enable
7 2 Keep
-
+# Fan Cruise Control
+8 0 Disabled
+8 1 Speed
+#8 2 Thermal
+# Fan Speed (Rotations per Minute)
+9 0 5625
+9 1 5192
+9 2 4753
+9 3 4326
+9 4 3924
+9 5 3552
+9 6 3214
+9 7 2909
+9 8 2636
+9 9 2393
+9 10 2177
+9 11 1985
+9 12 1814
+9 13 1662
+9 14 1527
+9 15 1406
+#
+# Temperature (°C/°F)
+#10 0 30/86
+#10 1 33/91
+#10 2 36/96
+#10 3 39/102
+#10 4 42/107
+#10 5 45/113
+#10 6 48/118
+#10 7 51/123
+#10 8 54/129
+#10 9 57/134
+#10 10 60/140
+#10 11 63/145
+#10 12 66/150
+#10 13 69/156
+#10 14 72/161
+#10 15 75/167
# -----------------------------------------------------------------
checksums
)
{
// Some generic macros
- Include ("acpi/platform.asl")
+ #include "acpi/platform.asl"
// global NVS and variables
- Include ("../../../southbridge/intel/i82801gx/acpi/globalnvs.asl")
+ #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl"
// General Purpose Events
- //include ("acpi/gpe.asl")
+ //#include "acpi/gpe.asl"
- //include ("acpi/thermal.asl")
+ //#include "acpi/thermal.asl"
Scope (\_SB) {
Device (PCI0)
{
- Include ("../../../northbridge/intel/i945/acpi/i945.asl")
- include ("../../../southbridge/intel/i82801gx/acpi/ich7.asl")
+ #include "../../../northbridge/intel/i945/acpi/i945.asl"
+ #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl"
}
}
/* Chipset specific sleep states */
- include ("../../../southbridge/intel/i82801gx/acpi/sleepstates.asl")
+ #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl"
}
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#include <device/pci.h>
#include <arch/acpi.h>
-/* FIXME: This needs to go into a separate .h file
+/* FIXME: This needs to go into a separate .h file
* to be included by the ich7 smi handler, ich7 smi init
* code and the mainboard fadt.
*/
#define APM_CNT 0xb2
-#define CST_CONTROL 0x00 // 0xe3 crashes the box
-#define PST_CONTROL 0x00 // 0xe2 crashes the box
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
#define ACPI_DISABLE 0x1e
#define ACPI_ENABLE 0xe1
#define GNVS_UPDATE 0xea
fadt->acpi_disable = ACPI_DISABLE;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = PST_CONTROL;
-
+
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + 0x4;
fadt->century = 0x00;
fadt->iapc_boot_arch = 0x03;
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
+
fadt->reset_reg.space_id = 0;
fadt->reset_reg.bit_width = 0;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0x0;
fadt->reset_reg.addrh = 0x0;
-
+
fadt->reset_value = 0;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
-
+
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pmbase;
fadt->x_pm1a_evt_blk.addrh = 0x0;
-
+
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
-
+
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
+
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
+
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
fadt->x_pm2_cnt_blk.addrh = 0x0;
-
+
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
-
+
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 64;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pmbase + 0x28;
fadt->x_gpe0_blk.addrh = 0x0;
-
+
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* MA 02110-1301 USA
*/
-
+#include <types.h>
#include <device/device.h>
#include <console/console.h>
#include <boot/tables.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
#include "chip.h"
int add_northbridge_resources(struct lb_memory *mem);
return add_northbridge_resources(mem);
}
+/* Hardware Monitor */
+
+static u16 hwm_base = 0xa00;
+
+static void hwm_write(u8 reg, u8 value)
+{
+ outb(reg, hwm_base + 0x05);
+ outb(value, hwm_base + 0x06);
+}
+
+static void hwm_bank(u8 bank)
+{
+ hwm_write(0x4e, bank);
+}
+
+#define FAN_CRUISE_CONTROL_DISABLED 0
+#define FAN_CRUISE_CONTROL_SPEED 1
+#define FAN_CRUISE_CONTROL_THERMAL 2
+
+#define FAN_SPEED_5625 0
+//#define FAN_TEMPERATURE_30DEGC 0
+
+struct fan_speed {
+ u8 fan_in;
+ u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+ { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+ { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+ { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+ { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+ u8 deg_celsius;
+ u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+ { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
+ { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+ { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+ { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+static void hwm_setup(void)
+{
+ int cpufan_control = 0, sysfan_control = 0;
+ int cpufan_speed = 0, sysfan_speed = 0;
+ int cpufan_temperature = 0, sysfan_temperature = 0;
+
+ if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
+ cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&cpufan_speed, "cpufan_speed") < 0)
+ cpufan_speed = FAN_SPEED_5625;
+ //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
+ // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
+ sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&sysfan_speed, "sysfan_speed") < 0)
+ sysfan_speed = FAN_SPEED_5625;
+ //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
+ // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ // hwm_write(0x31, 0x20); // AVCC high limit
+ // hwm_write(0x34, 0x06); // VIN2 low limit
+
+ hwm_bank(0);
+ hwm_write(0x59, 0x20); // Diode Selection
+ hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+ hwm_bank(4);
+ hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+ hwm_write(0x55, 0x19); // CPUTIN temperature offset
+ hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+ hwm_bank(0x80); // Default
+
+ u8 fan_config = 0;
+ // 00 FANOUT is Manual Mode
+ // 01 FANOUT is Thermal Cruise Mode
+ // 10 FANOUT is Fan Speed Cruise Mode
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
+ }
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
+ }
+ // This register must be written first
+ hwm_write(0x04, fan_config);
+
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk_debug("Fan Cruise Control setting CPU fan to %d RPM\n",
+ fan_speeds[cpufan_speed].fan_speed);
+ hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk_debug("Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+ temperatures[cpufan_temperature].deg_celsius,
+ temperatures[cpufan_temperature].deg_fahrenheit);
+ hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
+ break;
+ }
+
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk_debug("Fan Cruise Control setting system fan to %d RPM\n",
+ fan_speeds[sysfan_speed].fan_speed);
+ hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk_debug("Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+ temperatures[sysfan_temperature].deg_celsius,
+ temperatures[sysfan_temperature].deg_fahrenheit);
+ hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+ break;
+ }
+
+ hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+ hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+ hwm_write(0x47, 0xaf); // FAN divisor register
+ hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+ hwm_write(0x40, 0x01); // Init, but no SMI#
+}
+
+/* Audio Setup */
+
+extern u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+ // Default VERB is fine on this mainboard.
+ cim_verb_data = NULL;
+ cim_verb_data_size = 0;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+ hwm_setup();
+}
+
struct chip_operations mainboard_ops = {
CHIP_NAME("Kontron 986LCD-M Mainboard")
+ .enable_dev = mainboard_enable,
};
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include "i945.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
if (!dev)
return current;
- pciexbar_reg=pci_read_config32(dev, 0x48);
+ pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))
* MA 02110-1301 USA
*/
-Include ("../../../northbridge/intel/i945/acpi/i945_hostbridge.asl")
+#include "../../../northbridge/intel/i945/acpi/i945_hostbridge.asl"
+#include "../../../northbridge/intel/i945/i945.h"
/* PCI Device Resource Consumption */
Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
- Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
- Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
- Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
- Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
}
// PCIe graphics port 0:1.0
-Include ("../../../northbridge/intel/i945/acpi/i945_peg.asl")
+#include "../../../northbridge/intel/i945/acpi/i945_peg.asl"
// Integrated graphics 0:2.0
-Include ("../../../northbridge/intel/i945/acpi/i945_igd.asl")
+#include "../../../northbridge/intel/i945/acpi/i945_igd.asl"
Scope (\)
{
// backlight control, display switching, lid
- Include ("acpi/video.asl")
+ #include "acpi/video.asl"
}
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
+Name(_ADR, 0)
+Name(_BBN, 0)
+
Device (MCHC)
{
Name(_ADR, 0x00000000) // 0:0.0
}
/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-Include ("acpi/i945_pci_irqs.asl")
+#include "acpi/i945_pci_irqs.asl"
reg32 &= ~(1 << 8);
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32);
+ /* We have no success with querying the usual PCIe registers
+ * for link setup success on the i945. Hence we assign a temporary
+ * PCI bus 0x0a and check whether we find a device on 0:a.0
+ */
+
+ /* First we reset the secondary bus */
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
+ reg16 |= (1 << 6);
+ pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+ /* Read back and clear reset bit. */
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
+ reg16 &= ~(1 << 6);
+ pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
+ printk_debug("SLOTSTS: %04x\n", reg16);
+ if (!(reg16 & 0x48)) {
+ goto disable_pciexpress_x16_link;
+ }
+ reg16 |= (1 << 4) | (1 << 0);
+ pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);
+
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a);
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a);
+
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
reg32 &= ~(1 << 8);
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
/* Wait for training to succeed */
- printk_debug("Wait for PCIe x16 link training ...");
- timeout = 0x7fff;
+ printk_debug("PCIe link training ...");
+ timeout = 0x7ffff;
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
- if (!timeout) {
- printk_debug("timeout!\n");
+
+ reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
+ if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
+ printk_debug(" Detected PCIe device %04x:%04x\n",
+ reg32 & 0xffff, reg32 >> 16);
+ } else {
+ printk_debug(" timeout!\n");
printk_debug("Restrain PCIe port to x1\n");
reg16 &= ~(1 << 6);
pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
- printk_debug("Wait for PCIe x1 link training ...");
- timeout = 0x7fff;
+ printk_debug("PCIe link training ...");
+ timeout = 0x7ffff;
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
- if (!timeout) {
- printk_debug("timeout!\n");
+
+ reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
+ if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
+ printk_debug(" Detected PCIe x1 device %04x:%04x\n",
+ reg32 & 0xffff, reg32 >> 16);
+ } else {
+ printk_debug(" timeout!\n");
printk_debug("Disabling PCIe x16 port completely.\n");
goto disable_pciexpress_x16_link;
- } else {
- printk_debug("ok\n");
}
- } else {
- printk_debug("ok\n");
}
reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2);
// TODO
}
+ reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
+ printk_debug("PCIe device class: %06x\n", reg32);
+ if (reg32 == 0x030000) {
+ printk_debug("PCIe device is VGA. Disabling IGD.\n");
+ reg16 = (1 << 1);
+ pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
+
+ /* DEVEN */
+ reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), 0x54);
+ reg32 &= ~((1 << 3) | (1 << 4));
+ pci_write_config32(PCI_DEV(0, 0x0, 0), 0x54, reg32);
+
+ /* Set VGA enable bit in PCIe bridge */
+ reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e);
+ reg16 |= (1 << 3);
+ pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16);
+ }
+
/* Enable GPEs */
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec);
reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */
#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__
#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1
+/* Northbridge BARs */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#define DEFAULT_X60BAR 0xfed13000
+#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
+#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
#define DMIBAR 0x4c
#define X60BAR 0x60
-/* Northbridge BARs */
-#define DEFAULT_PCIEXBAR 0xf0000000 /* 4 KB per PCIe device */
-#define DEFAULT_X60BAR 0xfed13000
-#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
-#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
-#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-
#define GGC 0x52 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
#define DMIDRCCFG 0xeb4 /* 32bit */
#endif
+#endif
if (!dev)
return 0;
- pciexbar_reg = pci_read_config32(dev, 0x48);
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
return 0;
}
-/* in arch/i386/boot/tables.c */
-extern uint64_t high_tables_base, high_tables_size;
-
/* IDG memory */
uint64_t uma_memory_base=0, uma_memory_size=0;
}
#if CONFIG_WRITE_HIGH_TABLES==1
-#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+#define HIGH_TABLES_SIZE 1024 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
}
}
+#if CONFIG_HAVE_ACPI_RESUME
+extern u8 acpi_slp_type;
+
+static void northbridge_init(struct device *dev)
+{
+ switch (pci_read_config32(dev, SKPAD)) {
+ case 0xcafebabe:
+ printk_debug("Normal boot.\n");
+ acpi_slp_type=0;
+ break;
+ case 0xcafed00d:
+ printk_debug("S3 Resume.\n");
+ acpi_slp_type=3;
+ break;
+ default:
+ printk_debug("Unknown boot method, assuming normal.\n");
+ acpi_slp_type=0;
+ break;
+ }
+}
+#endif
+
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
.read_resources = mc_read_resources,
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = 0,
+#if CONFIG_HAVE_ACPI_RESUME
+ .init = northbridge_init,
+#endif
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
{
MCHBAR32(REPC) |= (1 << 0);
+ /* enable upper CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
/* Program Receive Enable Timings */
if (sysinfo->boot_path == BOOT_PATH_RESUME) {
sdram_recover_receive_enable();
sdram_thermal_management();
/* Normal Operations */
- if (boot_path == BOOT_PATH_NORMAL) {
- sdram_init_complete();
- }
+ sdram_init_complete();
/* Program Receive Enable Timings */
sdram_program_receive_enable(&sysinfo);
sdram_setup_processor_side();
}
+unsigned long get_top_of_ram(void)
+{
+ /* This will not work if TSEG is in place! */
+ u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+
+ return (unsigned long) tom;
+}
+
PPCM, 8, // 0x2c - Max. PPC state
/* Super I/O & CMOS config */
Offset (0x32),
- NATP, 8, // 0x32 - ...
+ NATP, 8, // 0x32 -
+ CMAP, 8, // 0x33 -
+ CMBP, 8, // 0x34 -
+ LPTP, 8, // 0x35 - LPT Port
+ FDCP, 8, // 0x36 - Floppy Disk Controller
+ RFDV, 8, // 0x37 -
+ HOTK, 8, // 0x38 -
+ RTCF, 8, // 0x39 -
+ UTIL, 8, // 0x3a -
+ ACIN, 8, // 0x3b -
/* Integrated Graphics Device */
Offset (0x3c),
IGDS, 8, // 0x3c - IGD state (primary = 1)
/* Mainboard Specific (TODO move elsewhere) */
Offset (0xf0),
DOCK, 8, // 0xf0 - Docking Status
+ BTEN, 8, // 0xf1 - Bluetooth Enable
}
* MA 02110-1301 USA
*/
-/* Intel i82801G support
- */
+/* Intel 82801Gx support */
Scope(\)
{
}
// ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
- // this doesn't work as ACPI initializes regions and packages first, devices second.
- // use dynamic operation region? if so, how? XXX
- //OperationRegion(PMIO, SystemIO, And(\_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80)
- OperationRegion(PMIO, SystemIO, 0x500, 0x80)
+ OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
Field(PMIO, ByteAcc, NoLock, Preserve)
{
Offset(0x42), // General Purpose Control
}
// ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
- OperationRegion(GPIO, SystemIO, 0x1180, 0x3c)
+ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // GPIO Use Select
GIO2, 8,
GIO3, 8,
Offset(0x0c), // GPIO Level
- GL00, 8,
- GL01, 8,
- , 3,
- GP27, 1, // SATA_PWR_EN #0
- GP28, 1, // SATA_PWR_EN #1
- , 3,
+ GL00, 6,
+ GP07, 1, // GDET
+ GP08, 1,
+ GP09, 1,
+ GP10, 1, // HPMU
+ GP11, 1, // GPSE
+ GP12, 1,
+ GP13, 1, // WLED
+ GP14, 1, // BLED
+ GP15, 1, // GLED
+ GP16, 1, // GDIS
+ GP17, 1,
+ GP18, 1,
+ GP19, 1, // SPCI
+ GP20, 1, // TSDT
+ GP21, 1, // SCPU
+ GP22, 1,
+ GP23, 1,
+ GP24, 1, // LANP
+ GP25, 1, // DKLR
+ GP26, 1, // WLAN
+ GP27, 1, // SATA_PWR_EN #0 / SPOF
+ GP28, 1, // SATA_PWR_EN #1 / SPMU
+ GP29, 1,
+ GP30, 1,
+ GP31, 1,
Offset(0x18), // GPIO Blink
GB00, 8,
GB01, 8,
GIO6, 8,
GIO7, 8,
Offset(0x38), // GPIO Level 2
- , 5,
- GP37, 1, // PATA_PWR_EN
- GP38, 1, // Battery / Power (?)
- GP39, 1, // ??
+ GP32, 1,
+ GP33, 1, // CREN
+ GP34, 1, // CRRS
+ GP35, 1,
+ GP36, 1, // STAD
+ GP37, 1, // PATA_PWR_EN / HDDE
+ GP38, 1, // Battery / Power (?) / MB00
+ GP39, 1, // ?? / MB01
GL05, 8,
GL06, 8,
GL07, 8
// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
- OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000)
+ OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve)
{
Offset(0x0000), // Backbone
}
// 0:1b.0 High Definition Audio (Azalia)
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl"
// PCI Express Ports
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl"
// USB
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl"
// PCI Bridge
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl"
// AC97 Audio and Modem
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl"
// LPC Bridge
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl"
// PATA
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl"
// SATA
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl"
// SMBus
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl"
RCBA, 18,
}
- Include ("../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl")
+ #include "../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl"
- Include ("acpi/ec.asl")
+ #include "acpi/ec.asl"
Device (DMAC) // DMA Controller
{
IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
- // IO (Decode16, 0x680, 0x680, 0x1, 0x70) // IO ???
IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
- IO (Decode16, 0x0500, 0x0500, 0x1, 0x80) // ICH7-M ACPI
- IO (Decode16, 0x0480, 0x0480, 0x1, 0x40) // ICH7-M GPIO
- // IO (Decode16, 0x1640, 0x1640, 0x1, 0x10) // IO ???
+ IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI
+ IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO
})
}
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
- IRQNoFlags() { 8 }
+// Disable as Windows doesn't like it, and systems don't seem to use it.
+// IRQNoFlags() { 8 }
})
}
})
}
- Include ("acpi/superio.asl")
+ #include "acpi/superio.asl"
+
+#ifdef ENABLE_TPM
+ Device (TPM) // Trusted Platform Module
+ {
+ Name(_HID, EISAID("IFX0102"))
+ Name(_CID, 0x310cd041)
+ Name(_UID, 1)
+
+ Method(_STA, 0)
+ {
+ If (TPMP) {
+ Return (0xf)
+ }
+ Return (0x0)
+ }
+
+ Name(_CRS, ResourceTemplate() {
+ IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
+ IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
+ IRQ (Edge, Activehigh, Exclusive) { 6 }
+ })
+ }
+#endif
Device (PS2K) // Keyboard
{
}
}
+#ifdef ENABLE_FDC
Device (FDC0) // Floppy controller
{
Name (_HID, EisaId ("PNP0700"))
})
}
+#endif
}
Method (_PRT)
{
- Include ("acpi/ich7_pci_irqs.asl")
+ #include "acpi/ich7_pci_irqs.asl"
}
}
Device (RP01)
{
NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
Device (RP02)
{
NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
Device (RP03)
{
NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
Device (RP04)
{
NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
Device (RP05)
{
NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
Device (RP06)
{
NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
I2CE, 1
}
- /*
OperationRegion (SMBI, SystemIO, 0x400, 0x20)
Field (SMBI, ByteAcc, NoLock, Preserve)
{
NDLH, 8, // Notify Data High Byte
}
+#ifdef ENABLE_SMBUS_METHODS
// Kill all SMBus communication
Method (KILL, 0, Serialized)
{
Return (0xffff)
}
- */
-
- // Todo: Does anyone ever use these?
- // Missing: Read / Write Word
- // Missing: Read / Write Block
+#endif
}
* MA 02110-1301 USA
*/
-Name(\_S0, Package(4){0x0,0x0,0,0})
-Name(\_S1, Package(4){0x1,0x0,0,0})
-Name(\_S3, Package(4){0x5,0x0,0,0})
-Name(\_S4, Package(4){0x6,0x0,0,0})
-Name(\_S5, Package(4){0x7,0x0,0,0})
+Name(\_S0, Package(){0x0,0x0,0,0})
+Name(\_S1, Package(){0x1,0x0,0,0})
+Name(\_S3, Package(){0x5,0x0,0,0})
+Name(\_S4, Package(){0x6,0x0,0,0})
+Name(\_S5, Package(){0x7,0x0,0,0})
uint8_t gpi14_routing;
uint8_t gpi15_routing;
+ uint32_t gpe0_en;
+ uint16_t alt_gp_smi_en;
+
/* IDE configuration */
uint32_t ide_legacy_combined;
uint32_t ide_enable_primary;
uint32_t ide_enable_secondary;
uint32_t sata_ahci;
-
- /* Azalia Configuration */
- uint32_t hda_viddid;
};
extern struct chip_operations southbridge_intel_i82801gx_ops;
#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
#define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
+/*
+ * It does not matter where we put the SMBus I/O base, as long as we
+ * keep it consistent and don't interfere with other devices. Stage2
+ * will relocate this anyways.
+ * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * again. But handling static BARs is a generic problem that should be
+ * solved in the device allocator.
+ */
+#define SMBUS_IO_BASE 0x0400
+/* TODO Make sure these don't get changed by stage2 */
+#define DEFAULT_GPIOBASE 0x0480
+#define DEFAULT_PMBASE 0x0500
+#define HPET_ADDR 0xfed00000
+#define DEFAULT_RCBA 0xfed1c000
+
+#ifndef __ACPI__
+#define DEBUG_PERIODIC_SMIS 0
/* __ROMCC__ is set by auto.c to make sure
* none of the stage2 data structures are included.
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
-#define SIG_MODE_NORMAL (0 << 16)
-#define SIG_MODE_TRISTATE (1 << 16)
-#define SIG_MODE_DRIVELOW (2 << 16)
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
#define FAST_PCB1 (1 << 13)
#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
#define PCB1 (1 << 1)
#define PCB0 (1 << 0)
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
-/* SMBus I/O bits.
- * It does not matter where we put the SMBus I/O base, as long as we
- * keep it consistent and don't interfere with other devices. Stage2
- * will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
- * again. But handling static BARs is a generic problem that should be
- * solved in the device allocator.
- */
-#define SMBUS_IO_BASE 0x0400
-
+/* SMBus I/O bits. */
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
#define SMBUS_TIMEOUT (10 * 1000 * 100)
-/* HPET, if present */
-#define HPET_ADDR 0xfed0000
/* Southbridge IO BARs */
-/* TODO Make sure these don't get changed by stage2 */
#define GPIOBASE 0x48
-#define DEFAULT_GPIOBASE 0x480
#define PMBASE 0x40
-#define DEFAULT_PMBASE 0x500
/* Root Complex Register Block */
#define RCBA 0xf0
-#define DEFAULT_RCBA 0xfed1c000
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
#define FD_SATA (1 << 2)
#define FD_PATA (1 << 1)
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL 0x00
+#define GP_IO_SEL 0x04
+#define GP_LVL 0x0c
+#define GPO_BLINK 0x18
+#define GPI_INV 0x2c
+#define GPIO_USE_SEL2 0x30
+#define GP_IO_SEL2 0x34
+#define GP_LVL2 0x38
+
+/* ICH7 PMBASE */
+#define PM1_STS 0x00
+#define PM1_EN 0x02
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP (7 << 10)
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define PROC_CNT 0x10
+#define LV2 0x14
+#define LV3 0x15
+#define LV4 0x16
+#define PM2_CNT 0x20 // mobile only
+#define GPE0_STS 0x28
+#define GPE0_EN 0x2c
+#define PME_B0_EN (1 << 13)
+#define SMI_EN 0x30
+#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
+#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
+#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define MCSMI_EN (1 << 11) // Trap microcontroller range access
+#define BIOS_RLS (1 << 7) // asserts SCI on bit set
+#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
+#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
+#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
+#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
+#define EOS (1 << 1) // End of SMI (deassert SMI#)
+#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
+#define SMI_STS 0x34
+#define ALT_GP_SMI_EN 0x38
+#define ALT_GP_SMI_STS 0x3a
+#define GPE_CNTL 0x42
+#define DEVACT_STS 0x44
+#define SS_CNT 0x50
+#define C3_RES 0x54
+
+#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */
return 0;
}
-static u32 cim_verb_data[] = {
- 0x00172000,
- 0x00172100,
- 0x001722EC,
- 0x00172310,
-
- /* Pin Complex (NID 0x12) */
- 0x01271CF0,
- 0x01271D11,
- 0x01271E11,
- 0x01271F41,
- /* Pin Complex (NID 0x14) */
- 0x01471C10,
- 0x01471D01,
- 0x01471E13,
- 0x01471F99,
- /* Pin Complex (NID 0x15) */
- 0x01571C20,
- 0x01571D40,
- 0x01571E21,
- 0x01571F01,
- /* Pin Complex (NID 0x16) */
- 0x01671CF0,
- 0x01671D11,
- 0x01671E11,
- 0x01671F41,
- /* Pin Complex (NID 0x18) */
- 0x01871C30,
- 0x01871D98,
- 0x01871EA1,
- 0x01871F01,
- /* Pin Complex (NID 0x19) */
- 0x01971C31,
- 0x01971D09,
- 0x01971EA3,
- 0x01971F99,
- /* Pin Complex (NID 0x1A) */
- 0x01A71C3F,
- 0x01A71D98,
- 0x01A71EA1,
- 0x01A71F02,
- /* Pin Complex (NID 0x1B) */
- 0x01B71C1F,
- 0x01B71D40,
- 0x01B71E21,
- 0x01B71F02,
- /* Pin Complex (NID 0x1C) */
- 0x01C71CF0,
- 0x01C71D11,
- 0x01C71E11,
- 0x01C71F41,
- /* Pin Complex (NID 0x1D) */
- 0x01D71CF0,
- 0x01D71D11,
- 0x01D71E11,
- 0x01D71F41,
- /* Pin Complex (NID 0x1E) */
- 0x01E71CF0,
- 0x01E71D11,
- 0x01E71E11,
- 0x01E71F41,
- /* Pin Complex (NID 0x1F) */
- 0x01F71CF0,
- 0x01F71D11,
- 0x01F71E11,
- 0x01F71F41,
-};
+u32 * cim_verb_data = NULL;
+u32 cim_verb_data_size = 0;
-static unsigned find_verb(struct device *dev, u32 viddid, u32 ** verb)
+static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
{
- config_t *config = dev->chip_info;
-
- if (config == NULL) {
- printk_err("\ni82801gx_azalia: Not mentioned in mainboard's Config.lb!\n");
- return 0;
+ int idx=0;
+
+ while (idx < (cim_verb_data_size / sizeof(u32))) {
+ u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
+ if (cim_verb_data[idx] != viddid) {
+ idx += verb_size + 3; // skip verb + header
+ continue;
+ }
+ *verb = &cim_verb_data[idx+3];
+ return verb_size;
}
- printk_debug("Azalia: dev=%s\n", dev_path(dev));
- printk_debug("Azalia: Default viddid=%x\n", (u32)config->hda_viddid);
- printk_debug("Azalia: Reading viddid=%x\n", viddid);
-
- if (viddid != config->hda_viddid)
- return 0;
-
- *verb = (u32 *) cim_verb_data;
-
- return sizeof(cim_verb_data) / sizeof(u32);
+ /* Not all codecs need to load another verb */
+ return 0;
}
/**
static int wait_for_valid(u8 *base)
{
+ u32 reg32;
+
+ /* Send the verb to the codec */
+ reg32 = readl(base + 0x68);
+ reg32 |= (1 << 0) | (1 << 1);
+ writel(reg32, base + 0x68);
+
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- u32 reg32 = readl(base + HDA_ICII_REG);
+ reg32 = readl(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
udelay(1);
}
- return 1;
+ return -1;
}
static void codec_init(struct device *dev, u8 * base, int addr)
u32 verb_size;
int i;
+ printk_debug("Azalia: Initializing codec #%d\n", addr);
+
/* 1 */
if (wait_for_ready(base) == -1)
return;
printk_debug("Azalia: No verb!\n");
return;
}
-
printk_debug("Azalia: verb_size: %d\n", verb_size);
+
/* 3 */
for (i = 0; i < verb_size; i++) {
if (wait_for_ready(base) == -1)
printk_debug("i82801gx_ide: initializing... ");
if (config == NULL) {
printk_err("\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
- // Trying to set somewhat save defaults instead of bailing out.
+ // Trying to set somewhat safe defaults instead of bailing out.
enable_primary = enable_secondary = 1;
} else {
enable_primary = config->ide_enable_primary;
pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
/* Set IDE I/O Configuration */
+ reg32 = 0;
+ /* FIXME: only set FAST_* for ata/100, only ?CBx for ata/66 */
+ if (enable_primary)
+ reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1;
if (enable_secondary)
- reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- else
- reg32 = SIG_MODE_NORMAL | FAST_PCB1 | PCB1;
+ reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1;
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Set Interrupt Line */
typedef struct southbridge_intel_i82801gx_config config_t;
-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-#define PIRQA 0x03
-#define PIRQB 0x05
-#define PIRQC 0x06
-#define PIRQD 0x07
-#define PIRQE 0x09
-#define PIRQF 0x0A
-#define PIRQG 0x0B
-#define PIRQH 0x0C
-
static void i82801gx_enable_apic(struct device *dev)
{
int i;
u16 reg16, pmbase;
u32 reg32;
char *state;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
- get_option(&pwr_on, "power_on_after_fail");
+ if (get_option(&pwr_on, "power_on_after_fail") < 0)
+ pwr_on = MAINBOARD_POWER_ON;
+
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 &= 0xfe;
switch (pwr_on) {
reg16 &= ~((3 << 0) | (1 << 10));
reg16 |= (1 << 3) | (1 << 5);
reg16 |= (1 << 2); // CLKRUN_EN
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
+ * periodic SMIs.
+ */
+ reg16 |= (3 << 0); // Periodic SMI every 8s
+#endif
pci_write_config16(dev, GEN_PMCON_1, reg16);
// Set the board's GPI routing.
i82801gx_gpi_routing(dev);
- /* Set up power management block and determine sleep mode */
pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+ outl(config->gpe0_en, pmbase + GPE0_EN);
+ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
+
+ /* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); // PM1_CNT
+#if 0
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0;
printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n",
reg32, acpi_slp_type);
+#endif
#endif
reg32 |= (1 << 1); // enable C3->C0 transition on bus master
reg32 |= 1; // SCI_EN
setup_i8259();
+ /* The OS should do this? */
+ // i8259_configure_irq_trigger(9, 1);
+
#if CONFIG_HAVE_SMI_HANDLER
i82801gx_lock_smm(dev);
#endif
u8 rsvd4[5];
/* Super I/O & CMOS config */
u8 natp; /* 0x32 - SIO type */
- u8 cmap;
- u8 cmbp;
- u8 lptp;
- u8 fdcp;
- u8 rfdv;
- u8 hotk;
+ u8 cmap; /* 0x33 - */
+ u8 cmbp; /* 0x34 - */
+ u8 lptp; /* 0x35 - LPT port */
+ u8 fdcp; /* 0x36 - Floppy Disk Controller */
+ u8 rfdv; /* 0x37 - */
+ u8 hotk; /* 0x38 - Hot Key */
u8 rtcf;
u8 util;
u8 acin;
u8 rsvd12[8];
/* Mainboard specific */
u8 dock; /* 0xf0 - Docking Status */
- u8 rsvd13[15];
+ u8 bten;
+ u8 rsvd13[14];
} __attribute__((packed)) global_nvs_t;
pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
/* Set IDE I/O Configuration */
- reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Combine IDE - SATA configuration */
pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
/* Set IDE I/O Configuration */
- reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Set Sata Controller Mode. */
pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
/* Set IDE I/O Configuration */
- reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Port 0 & 1 enable XXX */
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-/* ICH7 */
-#define PM1_STS 0x00
-#define PM1_EN 0x02
-#define PM1_CNT 0x04
-#define PM1_TMR 0x08
-#define PROC_CNT 0x10
-#define LV2 0x14
-#define LV3 0x15
-#define LV4 0x16
-#define PM2_CNT 0x20 // mobile only
-#define GPE0_STS 0x28
-#define GPE0_EN 0x2c
-#define SMI_EN 0x30
-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define MCSMI_EN (1 << 11) // Trap microcontroller range access
-#define BIOS_RLS (1 << 7) // asserts SCI on bit set
-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
-#define EOS (1 << 1) // End of SMI (deassert SMI#)
-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
-#define SMI_STS 0x34
-#define ALT_GP_SMI_EN 0x38
-#define ALT_GP_SMI_STS 0x3a
-#define GPE_CNTL 0x42
-#define DEVACT_STS 0x44
-#define SS_CNT 0x50
-#define C3_RES 0x54
-
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
*/
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
*/
- outl(smi_en | (TCO_EN | APMC_EN | SLP_SMI_EN | BIOS_EN |
- EOS | GBL_SMI_EN), pmbase + SMI_EN);
+
+ smi_en = 0; /* reset SMI enables */
+ smi_en |= TCO_EN;
+ smi_en |= APMC_EN;
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
+ * periodic SMIs.
+ */
+ smi_en |= PERIODIC_EN;
+#endif
+ smi_en |= SLP_SMI_EN;
+ smi_en |= BIOS_EN;
+
+ /* The following need to be on for SMIs to happen */
+ smi_en |= EOS | GBL_SMI_EN;
+
+ outl(smi_en, pmbase + SMI_EN);
/**
* There are several methods of raising a controlled SMI# via
#define G_SMRANE (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-/* ICH7 */
-#define PM1_STS 0x00
-#define PM1_EN 0x02
-#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define GBL_RLS (1 << 2)
-#define BM_RLD (1 << 1)
-#define SCI_EN (1 << 0)
-#define PM1_TMR 0x08
-#define PROC_CNT 0x10
-#define LV2 0x14
-#define LV3 0x15
-#define LV4 0x16
-#define PM2_CNT 0x20 // mobile only
-#define GPE0_STS 0x28
-#define GPE0_EN 0x2c
-#define PME_B0_EN (1 << 13)
-#define SMI_EN 0x30
-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define MCSMI_EN (1 << 11) // Trap microcontroller range access
-#define BIOS_RLS (1 << 7) // asserts SCI on bit set
-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
-#define EOS (1 << 1) // End of SMI (deassert SMI#)
-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
-#define SMI_STS 0x34
-#define ALT_GP_SMI_EN 0x38
-#define ALT_GP_SMI_STS 0x3a
-#define GPE_CNTL 0x42
-#define DEVACT_STS 0x44
-#define SS_CNT 0x50
-#define C3_RES 0x54
-
#include "i82801gx_nvs.h"
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
*/
u16 pmbase = DEFAULT_PMBASE;
+u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
static void dump_pm1_status(u16 pm1_sts)
{
- printk_debug("PM1_STS: ");
- if (pm1_sts & (1 << 15)) printk_debug("WAK ");
- if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
- if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
- if (pm1_sts & (1 << 10)) printk_debug("RTC ");
- if (pm1_sts & (1 << 8)) printk_debug("PWRBTN ");
- if (pm1_sts & (1 << 5)) printk_debug("GBL ");
- if (pm1_sts & (1 << 4)) printk_debug("BM ");
- if (pm1_sts & (1 << 0)) printk_debug("TMROF ");
- printk_debug("\n");
+ printk_spew("PM1_STS: ");
+ if (pm1_sts & (1 << 15)) printk_spew("WAK ");
+ if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK ");
+ if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR ");
+ if (pm1_sts & (1 << 10)) printk_spew("RTC ");
+ if (pm1_sts & (1 << 8)) printk_spew("PWRBTN ");
+ if (pm1_sts & (1 << 5)) printk_spew("GBL ");
+ if (pm1_sts & (1 << 4)) printk_spew("BM ");
+ if (pm1_sts & (1 << 0)) printk_spew("TMROF ");
+ printk_spew("\n");
}
/**
switch (smif) {
case 0x32:
printk_debug("OS Init\n");
+ /* gnvs->smif:
+ * On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ */
gnvs->smif = 0;
- break;
- default:
- /* Not handled */
- return 0;
+ return 1; /* IO trap handled */
}
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1; /* IO trap handled */
+ /* Not handled */
+ return 0;
}
/**
printk_debug("SMI#: ACPI enabled.\n");
break;
case GNVS_UPDATE:
+ if (smm_initialized) {
+ printk_debug("SMI#: SMM structures already initialized!\n");
+ return;
+ }
gnvs = *(global_nvs_t **)0x500;
tcg = *(void **)0x504;
smi1 = *(void **)0x508;
+ smm_initialized = 1;
printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
break;
default:
dump_gpe0_status(gpe0_sts);
}
+static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u16 reg16;
+ reg16 = inw(pmbase + ALT_GP_SMI_STS);
+ outl(reg16, pmbase + ALT_GP_SMI_STS);
+
+ reg16 &= inw(pmbase + ALT_GP_SMI_EN);
+ if (reg16)
+ printk_debug("GPI (mask %04x)\n",reg16);
+}
+
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
{
u32 reg32;
NULL, // [7] reserved
southbridge_smi_pm1, // [8] PM1_STS
southbridge_smi_gpe0, // [9] GPE0_STS
- NULL, // [10] GPI_STS
+ southbridge_smi_gpi, // [10] GPI_STS
southbridge_smi_mc, // [11] MCSMI_STS
NULL, // [12] DEVMON_STS
southbridge_smi_tco, // [13] TCO_STS
projects / coreboot.git / commitdiff