$(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL)
$(Q)rm -f $@
$(Q)$(CBFSTOOL) $@ create $(shell expr 1024 \* $(CONFIG_COREBOOT_ROMSIZE_KB)) 131072 $(obj)/coreboot.bootblock
- $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram normal/coreboot_ram $(CBFS_COMPRESS_FLAG)
$(Q)if [ -f fallback/coreboot_apc ]; \
then \
$(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \
else
printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
$(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_COMPRESS_FLAG)
- printf " PAYLOAD $(CONFIG_NORMAL_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
- $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_NORMAL_PAYLOAD_FILE) normal/payload $(CBFS_COMPRESS_FLAG)
$(CBFSTOOL) ./build/coreboot.rom print
endif
depends on BOARD_AMD_SERENGETI_CHEETAH
config HAVE_HARD_RESET
- int
- default 1
+ bool
+ default y
depends on BOARD_AMD_SERENGETI_CHEETAH
config IOAPIC
- int
- default 1
+ bool
+ default y
depends on BOARD_AMD_SERENGETI_CHEETAH
config SB_HT_CHAIN_ON_BUS0
depends on BOARD_AMD_SERENGETI_CHEETAH
config SERIAL_CPU_INIT
- int
- default 0
+ bool
+ default n
depends on BOARD_AMD_SERENGETI_CHEETAH
config AP_CODE_IN_CAR