The new CBFS based build system requires the whole ROM to be accessible

in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:

  Uncompressing coreboot to RAM.
  Jumping to image.
  Check CBFS header at fffedfe0
  magic is ffffffff
  ERROR: No valid CBFS header found!
  CBFS:  Could not find file fallback/coreboot_ram
  Jumping to image.

This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).

Build-tested and runtime-tested on ASUS P2B-F.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/a-trend/atc-6220/auto.c b/src/mainboard/a-trend/atc-6220/auto.c
index fa027e112783c1cb713db9416dec9e68d698f0b9..85e5f47cc78c57d094da4606070c6ecea3dc7471 100644 (file)
--- a/src/mainboard/a-trend/atc-6220/auto.c
+++ b/src/mainboard/a-trend/atc-6220/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/a-trend/atc-6240/auto.c b/src/mainboard/a-trend/atc-6240/auto.c
index 756d0e0709bfe22bb51a694cfad0cb4430efb4c4..cd0799880761790859b8e18c47bbf6e236de0810 100644 (file)
--- a/src/mainboard/a-trend/atc-6240/auto.c
+++ b/src/mainboard/a-trend/atc-6240/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/abit/be6-ii_v2_0/auto.c b/src/mainboard/abit/be6-ii_v2_0/auto.c
index 70beca92ac8607ab74a90bce7f3f00dd280cca96..7d323821ff34808d0fb4704183e96c2001caea16 100644 (file)
--- a/src/mainboard/abit/be6-ii_v2_0/auto.c
+++ b/src/mainboard/abit/be6-ii_v2_0/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/asus/p2b-d/auto.c b/src/mainboard/asus/p2b-d/auto.c
index 4857cd540f8922c57d21afcd95a7d090a0c6a596..7371ba787056acedf85989e49f266b346aada22b 100644 (file)
--- a/src/mainboard/asus/p2b-d/auto.c
+++ b/src/mainboard/asus/p2b-d/auto.c
@@ -31,6 +31,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/asus/p2b-ds/auto.c b/src/mainboard/asus/p2b-ds/auto.c
index 141f444684e26cd37ca2a5d6907bebd0aad3fbbc..810d7e352bf5b5855e0f42b28ac6ae0d83e16949 100644 (file)
--- a/src/mainboard/asus/p2b-ds/auto.c
+++ b/src/mainboard/asus/p2b-ds/auto.c
@@ -31,6 +31,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/asus/p2b-f/auto.c b/src/mainboard/asus/p2b-f/auto.c
index 86b07599493793336834d918a7404c5bd70f1e01..76d14ae15de60d689ea043be23c1174741a8bdde 100644 (file)
--- a/src/mainboard/asus/p2b-f/auto.c
+++ b/src/mainboard/asus/p2b-f/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/asus/p2b/auto.c b/src/mainboard/asus/p2b/auto.c
index fa027e112783c1cb713db9416dec9e68d698f0b9..2dfdb2432f04b728924c0bae53c96e9eb1df5e14 100644 (file)
--- a/src/mainboard/asus/p2b/auto.c
+++ b/src/mainboard/asus/p2b/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/asus/p3b-f/auto.c b/src/mainboard/asus/p3b-f/auto.c
index c9c64fc8e55ffe0fa9363f62f0d24939ed262336..fb3169f8adb73291f8a5c292dec36322541da1f6 100644 (file)
--- a/src/mainboard/asus/p3b-f/auto.c
+++ b/src/mainboard/asus/p3b-f/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/azza/pt-6ibd/auto.c b/src/mainboard/azza/pt-6ibd/auto.c
index 65a7fcc1f9b6132e5835210d9c8f36ec71c3eb81..b2b323b30f03a9dcc2f8afb871fa3a0607b6a04e 100644 (file)
--- a/src/mainboard/azza/pt-6ibd/auto.c
+++ b/src/mainboard/azza/pt-6ibd/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/biostar/m6tba/auto.c b/src/mainboard/biostar/m6tba/auto.c
index 4e018bd5b67fbaeb2584c537b7202b637a15e023..b956d3cb99bffa6c529a300ad31932eef94dc003 100644 (file)
--- a/src/mainboard/biostar/m6tba/auto.c
+++ b/src/mainboard/biostar/m6tba/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -59,6 +60,10 @@ static void main(unsigned long bist)
        console_init();
        report_bist_failure(bist);
        enable_smbus();
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        /* dump_spd_registers(); */
        sdram_set_registers();
        sdram_set_spd_registers();

diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
index 238231e8c5c8496eac138e431fcadfdf0f5f20fc..dee0ad418f7566378b741238f6c754bdb11fd1d5 100644 (file)
--- a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/gigabyte/ga-6bxc/auto.c b/src/mainboard/gigabyte/ga-6bxc/auto.c
index 79662ad5779b8b59e6a415333da5648b331d2c89..e12daacd9e227a07ef4f030dd0d643072636a934 100644 (file)
--- a/src/mainboard/gigabyte/ga-6bxc/auto.c
+++ b/src/mainboard/gigabyte/ga-6bxc/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/msi/ms6119/auto.c b/src/mainboard/msi/ms6119/auto.c
index 899b3bc601eb5eb3fe5c904721b74c6503975b09..5d8cdd13ad451901cf6514966a6dc0368c6ba34a 100644 (file)
--- a/src/mainboard/msi/ms6119/auto.c
+++ b/src/mainboard/msi/ms6119/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/msi/ms6147/auto.c b/src/mainboard/msi/ms6147/auto.c
index 30398bef7234c582464d824c5131bd9cb14f850d..a9616c4f4ec8d09808188e441750cbec8d8a939e 100644 (file)
--- a/src/mainboard/msi/ms6147/auto.c
+++ b/src/mainboard/msi/ms6147/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c
index 81241ac553d1dd8fc42501d5d4ee14f94108c3a5..72c5f588319ca5359662640c1f85ea36889ff854 100644 (file)
--- a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c
index 68eca0eedad6dce7cad0ea90d0320ead8538c0bb..64af6923492413db7a2367f696a74ba897afe069 100644 (file)
--- a/src/mainboard/tyan/s1846/auto.c
+++ b/src/mainboard/tyan/s1846/auto.c
@@ -30,6 +30,7 @@
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
        report_bist_failure(bist);
+
+       /* Enable access to the full ROM chip, needed very early by CBFS. */
+       i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
        enable_smbus();
        /* dump_spd_registers(); */
        sdram_set_registers();

diff --git a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
new file mode 100644 (file)
index 0000000..5b12e46
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include "i82371eb.h"
+
+static void i82371eb_enable_rom(device_t dev)
+{
+       u16 reg16;
+
+       /* Enable access to the whole ROM, disable ROM write access. */
+       reg16 = pci_read_config16(dev, XBCS);
+       reg16 |= LOWER_BIOS_ENABLE;
+       reg16 |= EXT_BIOS_ENABLE;
+       reg16 |= EXT_BIOS_ENABLE_1MB;
+       reg16 &= ~(WRITE_PROTECT_ENABLE);       /* Disable ROM write access. */
+       pci_write_config16(dev, XBCS, reg16);
+}

diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c
index a521d86bb0cf7d4cc4272122c2a3d8d40072a5c5..6a8de8d80e286875a000ca0ba54dbd04269e0624 100644 (file)
--- a/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -35,14 +35,6 @@ static void isa_init(struct device *dev)
        /* Initialize the real time clock (RTC). */
        rtc_init(0);
 
-       /* Enable access to all BIOS regions. */
-       reg16 = pci_read_config16(dev, XBCS);
-       reg16 |= LOWER_BIOS_ENABLE;
-       reg16 |= EXT_BIOS_ENABLE;
-       reg16 |= EXT_BIOS_ENABLE_1MB;
-       reg16 &= ~(WRITE_PROTECT_ENABLE);       /* Disable ROM write access. */
-       pci_write_config16(dev, XBCS, reg16);
-
        /*
         * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
         * bus, which is a subset of ISA. We select the full ISA bus here.