/* code generation functions **************************************************/
-/* emit_load_s1 ****************************************************************
+/* emit_load *******************************************************************
- Emits a possible load of the first source operand.
+ Emits a possible load of an operand.
*******************************************************************************/
-s4 emit_load_s1(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+s4 emit_load(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
{
codegendata *cd;
s4 disp;
return reg;
}
+/* emit_load_s1 ****************************************************************
-/* emit_load_s2 ****************************************************************
-
- Emits a possible load of the second source operand.
+ Emits a possible load of the first source operand.
*******************************************************************************/
-s4 emit_load_s2(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+s4 emit_load_s1(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
{
- codegendata *cd;
- s4 disp;
- s4 reg;
+ stackptr src;
+ s4 reg;
- /* get required compiler data */
+ src = iptr->s1.var;
- cd = jd->cd;
+ reg = emit_load(jd, iptr, src, tempreg);
- if (src->flags & INMEMORY) {
- COUNT_SPILLS;
+ return reg;
+}
- disp = src->regoff * 8;
- if (IS_FLT_DBL_TYPE(src->type)) {
- if (IS_2_WORD_TYPE(src->type))
- M_DLD(tempreg, REG_SP, disp);
- else
- M_FLD(tempreg, REG_SP, disp);
- } else
- M_LLD(tempreg, REG_SP, disp);
+/* emit_load_s2 ****************************************************************
- reg = tempreg;
- } else
- reg = src->regoff;
+ Emits a possible load of the second source operand.
+
+*******************************************************************************/
+
+s4 emit_load_s2(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
+{
+ stackptr src;
+ s4 reg;
+
+ src = iptr->sx.s23.s2.var;
+
+ reg = emit_load(jd, iptr, src, tempreg);
return reg;
}
s4 emit_load_s3(jitdata *jd, instruction *iptr, stackptr src, s4 tempreg)
{
- codegendata *cd;
- s4 disp;
- s4 reg;
-
- /* get required compiler data */
-
- cd = jd->cd;
+ stackptr src;
+ s4 reg;
- if (src->flags & INMEMORY) {
- COUNT_SPILLS;
-
- disp = src->regoff * 8;
-
- if (IS_FLT_DBL_TYPE(src->type)) {
- if (IS_2_WORD_TYPE(src->type))
- M_DLD(tempreg, REG_SP, disp);
- else
- M_FLD(tempreg, REG_SP, disp);
- } else
- M_LLD(tempreg, REG_SP, disp);
+ src = iptr->sx.s23.s3.var;
- reg = tempreg;
- } else
- reg = src->regoff;
+ reg = emit_load(jd, iptr, src, tempreg);
return reg;
}
/* emit_store ******************************************************************
- XXX
+ Emits a possible store to variable.
*******************************************************************************/
}
}
+/* emit_store_dst **************************************************************
+
+ Emits a possible store to the destination operand of an instruction.
+
+*******************************************************************************/
+
+void emit_store_dst(jitdata *jd, instruction *iptr, s4 d)
+{
+ emit_store(jd, iptr, iptr->dst.var, d);
+}
+
/* emit_copy *******************************************************************
cd = jd->cd;
rd = jd->rd;
+ stackptr src;
+ s4 reg;
+
+ src = iptr->sx.s23.s3.var;
+
+ reg = emit_load(jd, iptr, src, tempreg);
+
+ return reg;
if ((src->regoff != dst->regoff) ||
((src->flags ^ dst->flags) & INMEMORY)) {
d = codegen_reg_of_var(rd, iptr->opc, dst, REG_IFTMP);