* src/vm/jit/sparc64/codegen.h: Fixed big disp handling.

* src/vm/jit/sparc64/codegen.c: Likewise.

diff --git a/src/vm/jit/sparc64/codegen.c b/src/vm/jit/sparc64/codegen.c
index 98198029d0816649f81a1d3d8e7682dd0823f803..b0aee2ab66dacc1eced400e200e29f41b9d8579e 100644 (file)
--- a/src/vm/jit/sparc64/codegen.c
+++ b/src/vm/jit/sparc64/codegen.c
@@ -71,6 +71,12 @@
  */
 #define REG_PV REG_PV_CALLEE
 
+bool fits_13(s4 disp)
+{
+       /*  printf("fits disp %d?\n", disp); */
+
+       return (disp >= -4096) && (disp <= 4095);
+}
 
 /* codegen *********************************************************************
 
@@ -2505,7 +2511,7 @@ gen_method:
                        M_NOP;
                        disp = (s4) (cd->mcodeptr - cd->mcodebase);
                        /* REG_RA holds the value of the jmp instruction, therefore +8 */
-                       M_LDA(REG_ZERO, REG_RA_CALLER, -disp + 8); 
+                       M_LDA(4, REG_RA_CALLER, -disp + 8); 
 
 
                        /* actually only used for ICMD_BUILTIN */
@@ -2701,10 +2707,9 @@ gen_method:
                                M_ALD(rd->argintregs[1], REG_PV, disp);
                                disp = dseg_add_functionptr(cd, BUILTIN_arraycheckcast);
                                M_ALD(REG_ITMP3, REG_PV, disp);
-                               M_LDA(REG_SP, -6*8, REG_SP); /* PARAMARRAY SLOTS */
+                               /* XXX jit-c-call */
                                M_JMP(REG_RA_CALLER, REG_ITMP3, REG_ZERO);
                                M_NOP;
-                               M_LDA(REG_SP, 6*8, REG_SP);
 
                                s1 = emit_load_s1(jd, iptr, REG_ITMP1);
                                M_BEQZ(REG_RESULT_CALLER, 0);

diff --git a/src/vm/jit/sparc64/codegen.h b/src/vm/jit/sparc64/codegen.h
index fed19216866e34a5fe4128df95a0e784ab433d63..f35f8cc198303fbe76553872cae37dc0e77b89a3 100644 (file)
--- a/src/vm/jit/sparc64/codegen.h
+++ b/src/vm/jit/sparc64/codegen.h
@@ -44,6 +44,8 @@
 
 #include "md-abi.h" /* for INT_NATARG_CNT */
 
+#include <assert.h>
+
 /* from md-abi.c */
 s4 nat_argintregs[INT_NATARG_CNT];
 
@@ -204,13 +206,13 @@ s4 nat_argintregs[INT_NATARG_CNT];
  #define M_FMT4(op,op3,rd,rs2,cond,cc2,cc1,cc0,imm) \
        do { \
                *((u4 *) cd->mcodeptr) =  ( (((s4)(op)) << 30) | ((op3) << 19) | ((rd) << 25) | ((cc2) << 18) |  ((cond) << 14) | \
-                       ((imm) << 13) | ((cc1) << 12) | ((cc0) << 11) | ((rs2) << 0) ); \
+                       ((imm) << 13) | ((cc1) << 12) | ((cc0) << 11) | ((rs2) & 0x7ff) ); \
                cd->mcodeptr += 4; \
        } while (0)
 
 
-#define FR_X(r) (((r)<<1) + 1)
-#define DR_X(r) (((r)<<1)|((r)>>5))
+#define FR_X(r) (((r)<<1) + 1) /* transpose macro for floats which reside in upper half of double word */
+#define DR_X(r) (((r)<<1)|((r)>>5)) /* double float packing, see SPARC spec. */
 
 /* 3-address-floating-point-operation
  *   op .... opcode
@@ -284,8 +286,6 @@ s4 nat_argintregs[INT_NATARG_CNT];
                cd->mcodeptr += 4; \
        } while (0)
 
-
-
 #define M_NOP M_SETHI(0,0)      /* nop */
 
 #define M_AND(rs1,rs2,rd)       M_OP3(0x02,0x01,rd,rs1,rs2,REG)     /* 64b c = a &  b */
@@ -381,21 +381,54 @@ s4 nat_argintregs[INT_NATARG_CNT];
 #define M_CMOVRGE_IMM(rs1,rs2,rd) M_OP3C(0x2,0x2f,0x7,rd,rs1,rs2,IMM)  /* rs1>=0 ? rd=rs2 */
 
 
-/**** load/store operations ********/
+/**** big constant helpers *********/
+
+/* #define FITS_13BIT_IMM(x)       ((x >= -4096) && (x <= 4095)) */
+
+bool fits13(s4 disp);
+
+#define sethi_part(x) ((x)>>10)
+#define setlo_part(x) ((x) & 0x3ff)
+
+#define DO_SETHI_REG(c,rd) \
+       do { \
+               if (c > 0) { \
+                       M_SETHI(sethi_part(c), rd); \
+                       if (setlo_part(c)) { \
+                               M_OR_IMM(rd, setlo_part(c), rd); \
+                       } \
+               } \
+               else { \
+                       M_SETHI(sethi_part(~c), rd); \
+                       M_XOR_IMM(rd, setlo_part(c) | 0xffffffffffff1c00, rd); \
+               } \
+       } while (0)
+       
+#define DO_SETHI_PART(c,rs,rd) \
+       do { \
+               M_SETHI(sethi_part(c), rd); \
+               if (c > 0) { \
+                       M_ADD(rs,rd,rd); \
+               } \
+               else { \
+                       M_SUB(rs,rd,rd); \
+               } \
+       } while (0)
+               
 
 #define M_LDA(rd,rs,disp) \
     do { \
-        s4 lo = (short) (disp); \
-        s4 hi = (short) (((disp) - lo) >> 13); \
-        if (hi == 0) { \
-            M_AADD_IMM(rs,lo,rd); \
-        } else { \
-            M_SETHI(hi&0x3ffff8,rd); \
-            M_AADD_IMM(rd,lo,rd); \
+        if (fits_13(disp)) { \
+            M_AADD_IMM(rs,disp,rd); \
+        } \
+        else { \
+            DO_SETHI_REG(disp,rd); \
             M_AADD(rd,rs,rd); \
         } \
     } while (0)
 
+/**** load/store operations ********/
+
 #define M_SLDU(rd,rs,disp)      M_OP3(0x03,0x02,rd,rs,disp,IMM)        /* 16-bit load, uns*/
 #define M_SLDS(rd,rs,disp)      M_OP3(0x03,0x0a,rd,rs,disp,IMM)        /* 16-bit load, sig*/
 #define M_BLDS(rd,rs,disp)      M_OP3(0x03,0x09,rd,rs,disp,IMM)        /* 8-bit load, sig */
@@ -404,28 +437,27 @@ s4 nat_argintregs[INT_NATARG_CNT];
 #define M_LDX_INTERN(rd,rs,disp) M_OP3(0x03,0x0b,rd,rs,disp,IMM)       /* 64-bit load, sig*/
 #define M_LDX(rd,rs,disp) \
        do { \
-        s4 lo = (short) (disp); \
-        s4 hi = (short) (((disp) - lo) >> 13); \
-        if (hi == 0) { \
-            M_LDX_INTERN(rd,rs,lo); \
-        } else { \
-            M_SETHI(hi&0x3ffff8,rd); \
-            M_AADD(rs,rd,rd); \
-            M_LDX_INTERN(rd,rd,lo); \
+        if (fits_13(disp)) { \
+            M_LDX_INTERN(rd,rs,disp); \
+        } \
+        else { \
+                       printf("ldx imm = %d\n", disp); \
+            DO_SETHI_PART(disp,rs,rd); \
+            M_LDX_INTERN(rd,rd,setlo_part(disp)); \
+                       assert(0); \
         } \
     } while (0)
 
 #define M_ILD_INTERN(rd,rs,disp) M_OP3(0x03,0x08,rd,rs,disp,IMM)       /* 32-bit load, sig */
 #define M_ILD(rd,rs,disp) \
        do { \
-        s4 lo = (short) (disp); \
-        s4 hi = (short) (((disp) - lo) >> 13); \
-        if (hi == 0) { \
-            M_ILD_INTERN(rd,rs,lo); \
-        } else { \
-            M_SETHI(hi&0x3ffff8,rd); \
-            M_AADD(rs,rd,rd); \
-            M_ILD_INTERN(rd,rd,lo); \
+        if (fits_13(disp)) { \
+            M_ILD_INTERN(rd,rs,disp); \
+       } \
+        else { \
+            DO_SETHI_PART(disp,rs,rd); \
+            M_ILD_INTERN(rd,rd,setlo_part(disp)); \
+                       assert(0); \
         } \
     } while (0)
 
@@ -441,14 +473,13 @@ s4 nat_argintregs[INT_NATARG_CNT];
 #define M_STX_INTERN(rd,rs,disp) M_OP3(0x03,0x0e,rd,rs,disp,IMM)       /* 64-bit store    */
 #define M_STX(rd,rs,disp) \
        do { \
-        s4 lo = (short) (disp); \
-        s4 hi = (short) (((disp) - lo) >> 13); \
-        if (hi == 0) { \
-            M_STX_INTERN(rd,rs,lo); \
-        } else { \
-            M_SETHI(hi&0x3ffff8,REG_ITMP3); /* sethi has a 22bit imm, only set upper 19 bits */ \
-            M_AADD(rs,REG_ITMP3,REG_ITMP3); \
-            M_STX_INTERN(rd,REG_ITMP3,lo); \
+        if (fits_13(disp)) { \
+            M_STX_INTERN(rd,rs,disp); \
+        } \
+        else { \
+            DO_SETHI_PART(disp,rs,REG_ITMP3); \
+            M_STX_INTERN(rd,REG_ITMP3,setlo_part(disp)); \
+                       assert(0); \
         } \
     } while (0)
 
@@ -456,14 +487,13 @@ s4 nat_argintregs[INT_NATARG_CNT];
 #define M_IST_INTERN(rd,rs,disp) M_OP3(0x03,0x04,rd,rs,disp,IMM)       /* 32-bit store    */
 #define M_IST(rd,rs,disp) \
     do { \
-        s4 lo = (short) (disp); \
-        s4 hi = (short) (((disp) - lo) >> 13); \
-        if (hi == 0) { \
-            M_IST_INTERN(rd,rs,lo); \
-        } else { \
-            M_SETHI(hi&0x3ffff8,REG_ITMP3); /* sethi has a 22bit imm, only set upper 19 bits */ \
-            M_AADD(rs,REG_ITMP3,REG_ITMP3); \
-            M_IST_INTERN(rd,REG_ITMP3,lo); \
+        if (fits_13(disp)) { \
+            M_IST_INTERN(rd,rs,disp); \
+       } \
+        else { \
+            DO_SETHI_PART(disp,rs,REG_ITMP3); \
+            M_IST_INTERN(rd,REG_ITMP3,setlo_part(disp)); \
+                       assert(0); \
         } \
     } while (0)