Convert 12 more boards to use include statements in Config.lb.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/config/nofailovercalculation128.lb b/src/config/nofailovercalculation128.lb
new file mode 100644 (file)
index 0000000..a817a68
--- /dev/null
+++ b/src/config/nofailovercalculation128.lb
@@ -0,0 +1,38 @@
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+       default ROM_SECTION_SIZE   = FALLBACK_SIZE
+       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+       default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The coreboot bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreboot will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE = 128 * 1024
+default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
+
+## This is needed to work around a parser bug.
+if USE_FALLBACK_IMAGE
+end
+

diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index 62206abdfbd2cb57388a4f2aeccdccd83957fce9..0c39e4b7edce6260c89274e2d908c85f9d7c12a6 100644 (file)
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb
index 936552227f63afd99071dc595dc7bf36a8405f29..91264fdb8499772ccfae6d5069f8bf796117bab6 100644 (file)
--- a/src/mainboard/dell/s1850/Config.lb
+++ b/src/mainboard/dell/s1850/Config.lb
@@ -3,39 +3,7 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
index 07a5b39ad544d531a1fbe6ea86a77b72cd793cbf..8cc6e160e0927eb965c4c1bccb69d2b80bcedaa1 100644 (file)
--- a/src/mainboard/intel/jarrell/Config.lb
+++ b/src/mainboard/intel/jarrell/Config.lb
@@ -3,39 +3,7 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/intel/mtarvon/Config.lb b/src/mainboard/intel/mtarvon/Config.lb
index fb95201ff9036c75dd381a19d2f94f07f2bb52db..70dcc2360d66e9994f7f2d2ce6c7e7f4d9520b3e 100644 (file)
--- a/src/mainboard/intel/mtarvon/Config.lb
+++ b/src/mainboard/intel/mtarvon/Config.lb
@@ -17,38 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot ROM chip
-##
-if USE_FALLBACK_IMAGE
-        default ROM_SECTION_SIZE = FALLBACK_SIZE
-        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-        default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
-        default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of the coreboot bootloader
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot ROM
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/intel/truxton/Config.lb b/src/mainboard/intel/truxton/Config.lb
index 4d843ef7061ffc0e45f0e68aeba948c983a6fb1c..edfefb968f40c61b0efb9c05e45982fae83d4b28 100644 (file)
--- a/src/mainboard/intel/truxton/Config.lb
+++ b/src/mainboard/intel/truxton/Config.lb
@@ -17,38 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot ROM chip
-##
-if USE_FALLBACK_IMAGE
-        default ROM_SECTION_SIZE = FALLBACK_SIZE
-        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-        default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
-        default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of the coreboot bootloader
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot ROM
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb
index 5f5c9b8078beb8f5df0e26d83b5297b758fd2fef..84c5dcea4b1476d5ee3fe78ca3a032ca33988492 100644 (file)
--- a/src/mainboard/intel/xe7501devkit/Config.lb
+++ b/src/mainboard/intel/xe7501devkit/Config.lb
@@ -1,39 +1,4 @@
-##################################################################
-## BEGIN BOILERPLATE - DO NOT EDIT
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus payload) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
-
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-
-else
-# The normal image goes at the beginning of the coreboot ROM region
-# and uses all the remaining space
-
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-default XIP_ROM_SIZE = 65536
-default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )
-
-## END BOILERPLATE
-##################################################################
+include /config/nofailovercalculation128.lb
 
 arch i386 end 
 

diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb
index 86daad94e9b49ba2a8a6352fdcec981838d09658..a3eeea177847606ac58525e84d95ee5439f70e6a 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/Config.lb
+++ b/src/mainboard/kontron/986lcd-m/Config.lb
@@ -28,39 +28,7 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-        default ROM_SECTION_SIZE   = FALLBACK_SIZE
-        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-        default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-        default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=(64*1024)
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb
index 003e74b1e09303b2550c95ed8e19f9643dc1d998..3fca8b51a13a16265fb665745dacee3712a554b1 100644 (file)
--- a/src/mainboard/supermicro/x6dai_g/Config.lb
+++ b/src/mainboard/supermicro/x6dai_g/Config.lb
@@ -3,39 +3,7 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can be cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb
index 756ed4472b2aaa0e2e08c6e52d53e39985a35f7b..c2efe3f90cad4ea77e8e1c1e58005fc065ba0079 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g/Config.lb
@@ -3,39 +3,8 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE       =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+include /config/nofailovercalculation128.lb
 
-##
-## Compute a range of ROM that can be cached to speed up coreboot.
-## execution speed.
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##
 

diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb
index 2b88e344a75cc642f2afa9fddf6cd641a3af68f9..c014050fc42ba27e5d2ed1b44fe17d51fbf61831 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb
@@ -3,39 +3,8 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE       =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+include /config/nofailovercalculation128.lb
 
-##
-## Compute a range of ROM that can be cached to speed up coreboot.
-## execution speed.
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
 ## Set all of the defaults for an x86 architecture
 ##
 

diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb
index 5b83ab5ea46a71c93b5de7516497670cfeb032d5..048dc63613b84cd01a2c16b9d16684cd45720438 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb
@@ -3,39 +3,7 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture

diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
index 61204b73df7d030479578e5643b45f990b68fcd0..58f3835dbbb7c93b52316d9ed33740abd1361e61 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
@@ -3,39 +3,7 @@
 ##
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=131072
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation128.lb
 
 ##
 ## Set all of the defaults for an x86 architecture