Check to see if K8 processor is capable of changing FIDVID otherwise it will throw...

Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
index 6c8d9e3542b7c5427515c3548ba3ac6e11adb4c7..76ce93bf07f2f0a22093a86a8abb6d540906a927 100644 (file)
--- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
+++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
@@ -161,6 +161,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        int needs_reset = 0;
        u32 bsp_apicid = 0;
        msr_t msr;
+       struct cpuid_result cpuid1;
        struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 
@@ -197,16 +198,26 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs690_early_setup();
        sb600_early_setup();
 
-       msr=rdmsr(0xc0010042);
-       printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+       /* Check to see if processor is capable of changing FIDVID  */
+       /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+       cpuid1 = cpuid(0x80000007);
+       if( (cpuid1.edx & 0x6) == 0x6 ) {
 
-       enable_fid_change();
-       enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-       init_fidvid_bsp(bsp_apicid);
+               /* Read FIDVID_STATUS */
+               msr=rdmsr(0xc0010042);
+               printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
-       /* show final fid and vid */
-       msr=rdmsr(0xc0010042);
-       printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+               enable_fid_change();
+               enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+               init_fidvid_bsp(bsp_apicid);
+
+               /* show final fid and vid */
+               msr=rdmsr(0xc0010042);
+               printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+       } else {
+               printk_debug("Changing FIDVID not supported\n");
+       }
 
        needs_reset = optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);

diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c
index 52b5c0400af23af90a99daa954022cda8431ceee..c348a61f9de6950a775bd5cf56fa51246444cde5 100644 (file)
--- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c
+++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c
@@ -155,6 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        int needs_reset = 0;
        u32 bsp_apicid = 0;
        msr_t msr;
+       struct cpuid_result cpuid1;
        struct sys_info *sysinfo =
            (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
                                DCACHE_RAM_GLOBAL_VAR_SIZE);
@@ -198,16 +199,26 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x04);
 
-       msr = rdmsr(0xc0010042);
-       printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+       /* Check to see if processor is capable of changing FIDVID  */
+       /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+       cpuid1 = cpuid(0x80000007);
+       if( (cpuid1.edx & 0x6) == 0x6 ) {
 
-       enable_fid_change();
-       enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-       init_fidvid_bsp(bsp_apicid);
+               /* Read FIDVID_STATUS */
+               msr=rdmsr(0xc0010042);
+               printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
-       // show final fid and vid
-       msr = rdmsr(0xc0010042);
-       printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+               enable_fid_change();
+               enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+               init_fidvid_bsp(bsp_apicid);
+
+               /* show final fid and vid */
+               msr=rdmsr(0xc0010042);
+               printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+       } else {
+               printk_debug("Changing FIDVID not supported\n");
+       }
 
        post_code(0x05);
 

diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
index 5b217a671116e70642c7775a4bb8ce22ead92166..7e60c2c7a1ad224f64d5323568fd2353a85d695b 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
@@ -259,6 +259,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
+       struct cpuid_result cpuid1;
 
         if (bist == 0) {
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -311,8 +312,13 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
 #if K8_SET_FIDVID == 1
+       /* Check to see if processor is capable of changing FIDVID  */
+       /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+       cpuid1 = cpuid(0x80000007);
+       if( (cpuid1.edx & 0x6) == 0x6 ) {
 
         {
+               /* Read FIDVID_STATUS */
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
@@ -332,6 +338,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); 
 
         }
+
+       } else {
+               print_debug("Changing FIDVID not supported\n");
+       }
+
 #endif
 
 #if 1