+2007-06-07 Zoltan Varga <vargaz@gmail.com>
+
+ * mini-amd64.c (peephole_pass): Merge some small changes from the linear-ir
+ branch.
+
+ * cpu-amd64.md: Add long_and/or/xor opcodes.
+
2007-06-06 Wade Berrier <wberrier@novell.com>
* cpu-s390x.md (shr_imm): Correct the length of shr_imm instruction.
cond_exc_nc: len:8
cond_exc_iov: len:8
cond_exc_ic: len:8
+
long_add: dest:i src1:i src2:i len:3 clob:1
long_mul: dest:i src1:i src2:i clob:1 len:4
long_mul_imm: dest:i src1:i clob:1 len:12
long_div_un: dest:a src1:a src2:i len:16 clob:d
long_rem: dest:d src1:a src2:i len:16 clob:a
long_rem_un: dest:d src1:a src2:i len:16 clob:a
+long_and: dest:i src1:i src2:i len:3 clob:1
+long_or: dest:i src1:i src2:i len:3 clob:1
+long_xor: dest:i src1:i src2:i len:3 clob:1
long_shl: dest:i src1:i src2:s clob:1 len:31
long_shr: dest:i src1:i src2:s clob:1 len:32
long_shr_un: dest:i src1:i src2:s clob:1 len:32
+
long_conv_to_r4: dest:f src1:i len:8
long_conv_to_r8: dest:f src1:i len:8
long_conv_to_ovf_i: dest:i src1:i src2:i len:40
long_shr_imm: dest:i src1:i clob:1 len:11
long_shr_un_imm: dest:i src1:i clob:1 len:11
long_shl_imm: dest:i src1:i clob:1 len:11
+
float_beq: len:13
float_bne_un: len:18
float_blt: len:13
case OP_I8CONST:
/* reg = 0 -> XOR (reg, reg) */
/* XOR sets cflags on x86, so we cant do it always */
- if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode))) {
- ins->opcode = CEE_XOR;
+ if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
+ ins->opcode = OP_LXOR;
ins->sreg1 = ins->dreg;
ins->sreg2 = ins->dreg;
/* Fall through */
else
break;
case CEE_XOR:
+ case OP_LXOR:
if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
MonoInst *ins2;
}
}
break;
+ case OP_IADD_IMM:
+ if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
+ ins->opcode = OP_X86_INC_REG;
+ break;
+ case OP_ISUB_IMM:
+ if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
+ ins->opcode = OP_X86_DEC_REG;
+ break;
case OP_MUL_IMM:
/* remove unnecessary multiplication with 1 */
if (ins->inst_imm == 1) {
amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
break;
case CEE_XOR:
+ case OP_LXOR:
amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
break;
case OP_XOR_IMM: