atomic instructions

diff --git a/jit/powerpc/machine-instr.h b/jit/powerpc/machine-instr.h
index 7059b6d072d9a03f515c42b35c5a545e2e9b9202..10cf5b6225546a09630902017fbc163e1b05108e 100644 (file)
--- a/jit/powerpc/machine-instr.h
+++ b/jit/powerpc/machine-instr.h
@@ -1,24 +1,41 @@
 #ifndef _MACHINE_INSTR_H
 #define _MACHINE_INSTR_H
 
-static inline long compare_and_swap(long *p, long oldval, long newval)
+static inline void
+atomic_add(int *mem, int val)
 {
-    if (*p == oldval) {
-        *p = newval;
-        return oldval;
-    } else
-        return *p;
+       int temp;
+
+  __asm__ __volatile__ ("\n\
+1:  lwarx  %0,0,%2 \n\
+    add    %0,%0,%1 \n\
+       stwcx. %0,0,%2 \n\
+       bne-   1b \n\
+"   : "=&r"(temp)
+    : "r"(val), "r"(mem) : "cr0", "memory");
 }
 
-static inline void
-atomic_add(int *mem, int val)
+static inline long compare_and_swap(long *p, long oldval, long newval)
 {
-       *mem += val;
+  long ret, temp;
+
+  __asm__ __volatile__ ("\n\
+1:  lwarx  %0,0,%4 \n\
+    subf.  %1,%0,%2 \n\
+    bne-   2f \n\
+    or     %1,%3,%3 \n\
+    stwcx. %1,0,%4 \n\
+    bne-   1b \n\
+2: \n\
+"   : "=&r"(ret), "=&r"(temp)
+    : "r"(oldval), "r"(newval), "r"(p) : "cr0", "memory");
+
+  return ret;
 }
 
 #define STORE_ORDER_BARRIER() __asm__ __volatile__ ("" : : : "memory");
 #define MEMORY_BARRIER_BEFORE_ATOMIC() __asm__ __volatile__ ("sync" : : : "memory");
-#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("" : : : "memory");
+#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("isync" : : : "memory");
 #define MEMORY_BARRIER() __asm__ __volatile__ ( "sync" : : : "memory" );
 
 #endif

diff --git a/src/vm/jit/powerpc/machine-instr.h b/src/vm/jit/powerpc/machine-instr.h
index 7059b6d072d9a03f515c42b35c5a545e2e9b9202..10cf5b6225546a09630902017fbc163e1b05108e 100644 (file)
--- a/src/vm/jit/powerpc/machine-instr.h
+++ b/src/vm/jit/powerpc/machine-instr.h
@@ -1,24 +1,41 @@
 #ifndef _MACHINE_INSTR_H
 #define _MACHINE_INSTR_H
 
-static inline long compare_and_swap(long *p, long oldval, long newval)
+static inline void
+atomic_add(int *mem, int val)
 {
-    if (*p == oldval) {
-        *p = newval;
-        return oldval;
-    } else
-        return *p;
+       int temp;
+
+  __asm__ __volatile__ ("\n\
+1:  lwarx  %0,0,%2 \n\
+    add    %0,%0,%1 \n\
+       stwcx. %0,0,%2 \n\
+       bne-   1b \n\
+"   : "=&r"(temp)
+    : "r"(val), "r"(mem) : "cr0", "memory");
 }
 
-static inline void
-atomic_add(int *mem, int val)
+static inline long compare_and_swap(long *p, long oldval, long newval)
 {
-       *mem += val;
+  long ret, temp;
+
+  __asm__ __volatile__ ("\n\
+1:  lwarx  %0,0,%4 \n\
+    subf.  %1,%0,%2 \n\
+    bne-   2f \n\
+    or     %1,%3,%3 \n\
+    stwcx. %1,0,%4 \n\
+    bne-   1b \n\
+2: \n\
+"   : "=&r"(ret), "=&r"(temp)
+    : "r"(oldval), "r"(newval), "r"(p) : "cr0", "memory");
+
+  return ret;
 }
 
 #define STORE_ORDER_BARRIER() __asm__ __volatile__ ("" : : : "memory");
 #define MEMORY_BARRIER_BEFORE_ATOMIC() __asm__ __volatile__ ("sync" : : : "memory");
-#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("" : : : "memory");
+#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("isync" : : : "memory");
 #define MEMORY_BARRIER() __asm__ __volatile__ ( "sync" : : : "memory" );
 
 #endif