--- /dev/null
+#include <arch-generic/div64.h>
driver pci_bridge.c
arch ppc end
-cpu ppc/ppc4xx end
+chip cpu/ppc/ppc4xx device pnp 0.0 on end end
##
## Include the secondary Configuration files
##
-southbridge winbond/w83c553 end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
##
## Build the objects we have code for in this directory.
uses ISA_MEM_BASE
uses TTYS0_BASE
uses _IO_BASE
+
+uses CPU_OPT
+uses CROSS_COMPILE
+uses HAVE_OPTION_TABLE
+uses CONFIG_COMPRESS
+uses CONFIG_CHIP_CONFIGURE
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_USE_INIT
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD TTYS0_DIV
+uses NO_POST
+uses CONFIG_IDE
+uses CONFIG_FS_STREAM
+uses CONFIG_FS_EXT2
+uses CONFIG_FS_ISO9660
+uses CONFIG_FS_FAT
+uses AUTOBOOT_CMDLINE
+uses CONFIG_SYS_CLK_FREQ
+uses IDE_BOOT_DRIVE
+#uses IDE_SWAB
+uses IDE_OFFSET
+uses ROM_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+#uses _RAMSTART
+uses EMBEDDED_RAM_SIZE
+uses STACK_SIZE HEAP_SIZE
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
##
default TTYS0_BASE=0xef600300-ISA_IO_BASE
+## Enable PPC405 instructions
+default CPU_OPT="-Wa,-m405"
+default CPU_OPT=""
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## Use chip configuration
+default CONFIG_CHIP_CONFIGURE=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+# Divisor of 69 == 9600 baud due to weird clocking
+default TTYS0_DIV=69
+default TTYS0_BAUD=9600
+
+## Boot linux from IDE
+default CONFIG_IDE=1
+default CONFIG_FS_STREAM=1
+default CONFIG_FS_EXT2=1
+default CONFIG_FS_ISO9660=1
+default CONFIG_FS_FAT=1
+default AUTOBOOT_CMDLINE="hda1:/vmlinuz"
+
+default ROM_SIZE=1048576
+
+## Board has fixed size RAM
+default EMBEDDED_RAM_SIZE=64*1024*1024
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+
+##
+## Use a 64K stack
+##
+default STACK_SIZE=0x10000
+
+##
+## Use a 64K heap
+##
+default HEAP_SIZE=0x10000
+
+##
+## System clock
+##
+default CONFIG_SYS_CLK_FREQ=33
+
+##
+default _ROMBASE=0xfff00000
+
+## Reset vector address
+default _RESET=0xfffffffc
+
+## Exception vectors
+default _EXCEPTION_VECTORS=_ROMBASE+0x100
+
+## linuxBIOS ROM start address
+default _ROMSTART=0xfff03000
+
+## linuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+
+### End Options.lb
+end
arch ppc end
if CONFIG_SANDPOINT_ALTIMUS
- pmc altimus/mpc7410 end
-# pmc altimus/mpc7400 end
-# pmc altimus/mpc75x end
+ chip pmc/altimus/mpc7410 device pnp 0.0 on end end
+# chip pmc/altimus/mpc7400 device pnp 0.0 on end end
+# chip pmc/altimus/mpc75x device pnp 0.0 on end end
end
if CONFIG_SANDPOINT_TALUS
- pmc talus/mpc74x end
- pmc talus/mpc603 end
+ chip pmc/talus/mpc74x device pnp 0.0 on end end
+ chip pmc/talus/mpc603 device pnp 0.0 on end end
end
if CONFIG_SANDPOINT_UNITY
- pmc unity/mpc824x end
+ chip pmc/unity/mpc824x device pnp 0.0 on end end
end
if CONFIG_SANDPOINT_VALIS
- pmc valis/mpc745x end
+ chip pmc/valis/mpc745x device pnp 0.0 on end end
end
if CONFIG_SANDPOINT_GYRUS
- pmc gyrus/mpc744x end
+ chip pmc/gyrus/mpc744x device pnp 0.0 on end end
end
##
## Include the secondary Configuration files
##
-southbridge winbond/w83c553 end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
-superio NSC/pc97307 end
+chip superio/NSC/pc97307 device pnp 0.0 on end end
##
## Build the objects we have code for in this directory.
uses PNP_CFGADDR
uses PNP_CFGDATA
uses _IO_BASE
+
+uses CROSS_COMPILE
+uses HAVE_OPTION_TABLE
+uses CONFIG_SANDPOINT_ALTIMUS
+uses CONFIG_COMPRESS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_USE_INIT
+uses CONFIG_CHIP_CONFIGURE
+uses NO_POST
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BASE
+uses CONFIG_IDE
+uses CONFIG_FS_STREAM
+uses CONFIG_FS_EXT2
+uses CONFIG_FS_ISO9660
+uses CONFIG_FS_FAT
+uses AUTOBOOT_CMDLINE
+uses PAYLOAD_SIZE
+uses ROM_SIZE
+uses ROM_IMAGE_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+uses _RAMSTART
+uses STACK_SIZE
+uses HEAP_SIZE
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
default PNP_CFGADDR=0x15c
default PNP_CFGDATA=0x15d
default _IO_BASE=ISA_IO_BASE
+
+
+## use a cross compiler
+#default CROSS_COMPILE="powerpc-eabi-"
+#default CROSS_COMPILE="ppc_74xx-"
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## Use static configuration
+default CONFIG_CHIP_CONFIGURE=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+default TTYS0_BASE=0x3f8
+
+## Load payload using filo
+default CONFIG_IDE=1
+default CONFIG_FS_STREAM=1
+default CONFIG_FS_EXT2=1
+default CONFIG_FS_ISO9660=1
+default CONFIG_FS_FAT=1
+default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
+
+# LinuxBIOS must fit into 128KB
+default ROM_IMAGE_SIZE=131072
+default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
+default PAYLOAD_SIZE=262144
+
+# Set stack and heap sizes (stage 2)
+default STACK_SIZE=0x10000
+default HEAP_SIZE=0x10000
+
+# Sandpoint Demo Board
+## Base of ROM
+default _ROMBASE=0xfff00000
+
+## Sandpoint reset vector
+default _RESET=_ROMBASE+0x100
+
+## Exception vectors (other than reset vector)
+default _EXCEPTION_VECTORS=_RESET+0x100
+
+## Start of linuxBIOS in the boot rom
+## = _RESET + exeception vector table size
+default _ROMSTART=_RESET+0x3100
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+default _RAMSTART=0x00100000
+
+default CONFIG_SANDPOINT_ALTIMUS=1
+
+### End Options.lb
+end
arch ppc end
if CONFIG_BRIQ_750FX
- cpu ppc/ppc7xx end
+ chip cpu/ppc/ppc7xx device pnp 0.0 on end end
end
if CONFIG_BRIQ_7400
- cpu ppc/mpc74xx end
+ chip cpu/ppc/mpc74xx device pnp 0.0 on end end
end
##
## Include the secondary Configuration files
##
-northbridge ibm/cpc710 end
-southbridge winbond/w83c553 end
+chip northbridge/ibm/cpc710 device pnp 0.0 on end end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
##
## Build the objects we have code for in this directory.
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses _IO_BASE
+uses CROSS_COMPILE
+uses HAVE_OPTION_TABLE
+uses CONFIG_COMPRESS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_USE_INIT
+uses NO_POST
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_IDE_STREAM
+uses IDE_BOOT_DRIVE
+uses IDE_SWAB IDE_OFFSET
+uses ROM_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+uses _RAMSTART
+uses STACK_SIZE
+uses HEAP_SIZE
+uses CONFIG_BRIQ_750FX
+uses CONFIG_BRIQ_7400
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
## Set UART base address
##
default TTYS0_BASE=0x3f8
+
+## use a cross compiler
+#default CROSS_COMPILE="powerpc-eabi-"
+#default CROSS_COMPILE="ppc_74xx-"
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Boot linux from IDE
+default CONFIG_IDE_STREAM=1
+default IDE_BOOT_DRIVE=0
+default IDE_SWAB=1
+default IDE_OFFSET=0
+
+# ROM is 1Mb
+default ROM_SIZE=1048576
+
+# Set stack and heap sizes (stage 2)
+default STACK_SIZE=0x10000
+default HEAP_SIZE=0x10000
+
+# Sandpoint Demo Board
+## Base of ROM
+default _ROMBASE=0xfff00000
+
+## Sandpoint reset vector
+default _RESET=_ROMBASE+0x100
+
+## Exception vectors (other than reset vector)
+default _EXCEPTION_VECTORS=_RESET+0x100
+
+## Start of linuxBIOS in the boot rom
+## = _RESET + exeception vector table size
+default _ROMSTART=_RESET+0x3100
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+default _RAMSTART=0x00100000
+
+default CONFIG_BRIQ_750FX=1
+#default CONFIG_BRIQ_7400=1
+
+### End Options.lb
+end
##
## CPU initialization
##
-cpu ppc/mpc74xx end
+chip cpu/ppc/mpc74xx device pnp 0.0 on end end
##
## Include the secondary Configuration files
##
-northbridge motorola/mpc107 end
+chip northbridge/motorola/mpc107 device pnp 0.0 on end end
##
## Build the objects we have code for in this directory.
{
test "$verbose" == "true" && echo $*
}
-
+
function vendors
{
# make this a function so we can easily select
{
VENDOR=$1
MAINBOARD=$2
+ TARCH=$( architecture $VENDOR $MAINBOARD )
echo -n " Creating config file..."
mkdir -p $TARGET
( cat << EOF
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
+EOF
+ if [ $TARCH == i386 ] ; then
+ cat <<EOF
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x12000
option LINUXBIOS_EXTRA_VERSION=".0-fallback"
payload PAYLOAD
end
-
-buildrom ./VENDOR_MAINBOARD.rom ROM_SIZE "normal" "fallback"
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+EOF
+ else
+ cat <<EOF
+romimage "only"
+ option LINUXBIOS_EXTRA_VERSION=".0"
+ payload PAYLOAD
+end
+buildrom ./linuxbios.rom ROM_SIZE "only"
EOF
+ fi
) | sed -e s,VENDOR,$VENDOR,g \
-e s,MAINBOARD,$MAINBOARD,g \
-e s,PAYLOAD,$PAYLOAD,g \
TARCH=$( architecture $VENDOR $MAINBOARD )
# default setting
- CC="gcc"
- HOSTCC="gcc"
- CROSS_COMPILE=""
+ CC='$(CROSS_COMPILE)gcc'
+ HOSTCC='gcc'
+ CROSS_COMPILE=''
echo -n "Processing mainboard/$VENDOR/$MAINBOARD"
found_crosscompiler=true
fi
if [ "$found_crosscompiler" == "false" -a "$TARCH" == ppc ] ;then
- for prefix in powerpc-eabi- powerpc-linux- ; do
+ for prefix in powerpc-eabi- powerpc-linux- ppc_74xx- ; do
if ${prefix}gcc --version > /dev/null 2> /dev/null ; then
found_crosscompiler=true
CROSS_COMPILE=$prefix
echo
return 0
else
- echo " ($TARCH: ok, though we're $ARCH)"
+ echo " ($TARCH: ok, we're $ARCH)"
fi
fi
-
+
built_successfully $VENDOR $MAINBOARD && \
{
echo " ( mainboard/$VENDOR/$MAINBOARD previously ok )"
echo
return 0
}
-
+
build_broken $VENDOR $MAINBOARD || \
{
echo " ( broken mainboard/$VENDOR/$MAINBOARD skipped )"
case "$1" in
-t|--target) shift; target="$1"; shift;;
-a|--all) shift; buildall=true;;
- -b|--broken) shift; buildbroken=true;;
+ -b|--broken) shift; buildbroken=true;;
-v|--verbose) shift; verbose=true;;
-V|--version) shift; myversion; exit 0;;
-h|--help) shift; myhelp; exit 0;;
esac
done
+# /path/to/freebios2/
test -z "$1" || LBROOT=$1
debug "LBROOT=$LBROOT"
projects / coreboot.git / commitdiff