enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge.

Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb
index 8756d296b8691bcf5760b3fc005ebb64552821bb..e4de52b97032b412e5ce16455f3719c273225702 100644 (file)
--- a/src/mainboard/asus/mew-am/Config.lb
+++ b/src/mainboard/asus/mew-am/Config.lb
@@ -82,6 +82,9 @@ chip northbridge/intel/i82810         # Northbridge
     device pci 0.0 on end              # Graphics Memory Controller Hub (GMCH)
     device pci 1.0 on end              # Chipset Graphics Controller (CGC)
     chip southbridge/intel/i82801xx    # Southbridge
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
       device pci 1e.0 on end           # PCI bridge
       device pci 1f.0 on               # ISA bridge
         chip superio/smsc/smscsuperio  # Super I/O
@@ -126,8 +129,6 @@ chip northbridge/intel/i82810               # Northbridge
       device pci 1f.3 on end           # SMbus
       device pci 1f.5 off end          # AC'97 audio (N/A, uses CS4280 chip)
       device pci 1f.6 off end          # AC'97 modem (N/A)
-      #register "ide0_enable" = "1"
-      #register "ide1_enable" = "1"
     end
   end
 end

diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb
index a4a061bbe190dc76515e337f3e547e895fd220b1..cada58f7ae6bebb6ee745abfd74b6f2583a748e5 100644 (file)
--- a/src/mainboard/asus/mew-vm/Config.lb
+++ b/src/mainboard/asus/mew-vm/Config.lb
@@ -103,6 +103,9 @@ chip northbridge/intel/i82810
                        #end
                end
                chip southbridge/intel/i82801xx # Southbridge
+                       register "ide0_enable" = "1"
+                       register "ide1_enable" = "1"
+
                        device pci 1e.0 on # PCI Bridge
                                #chip drivers/pci/onboard
                                #       device pci 1.0 on end

diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb
index bfaf8f6f43fd7e66d2929f9a3dac3b5da2d72275..773d81392210675b630e4ee75d3c2a32025e0918 100644 (file)
--- a/src/mainboard/msi/ms6178/Config.lb
+++ b/src/mainboard/msi/ms6178/Config.lb
@@ -82,6 +82,9 @@ chip northbridge/intel/i82810                 # Northbridge
       # end
     end
     chip southbridge/intel/i82801xx            # Southbridge
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
       device pci 1e.0 on end                   # PCI bridge
       device pci 1f.0 on                       # ISA/LPC bridge
         chip superio/winbond/w83627hf          # Super I/O

diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb
index facf500b26936f0fde86146dba26314c8142705c..1388ea41d63e9d8403ba4500167f66cfddd0ef61 100644 (file)
--- a/src/mainboard/nec/powermate2000/Config.lb
+++ b/src/mainboard/nec/powermate2000/Config.lb
@@ -82,6 +82,9 @@ chip northbridge/intel/i82810                 # Northbridge
       # end
     end
     chip southbridge/intel/i82801xx            # Southbridge
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
       device pci 1e.0 on end                   # PCI bridge
       device pci 1f.0 on                       # ISA/LPC bridge
         chip superio/smsc/smscsuperio          # Super I/O (SMSC LPC47B27x)

diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb
index e11b4d19dc3d84f2d6d757a492e99b1daeff023b..458d44d23ca5fed4026380065dbf4a17526bb739 100644 (file)
--- a/src/mainboard/rca/rm4100/Config.lb
+++ b/src/mainboard/rca/rm4100/Config.lb
@@ -89,6 +89,9 @@ chip northbridge/intel/i82830         # Northbridge
       register "pirqg_routing" = "0x80"
       register "pirqh_routing" = "0x0b"
 
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
       device pci 1d.0 on end           # USB UHCI Controller #1
       device pci 1d.1 on end           # USB UHCI Controller #2
       device pci 1d.2 on end           # USB UHCI Controller #3

diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb
index f26ae532d2ebf984e569c1c0eea10b264bed6f76..5cb29aa7db6389d83d2c14ead615dbeffc338630 100644 (file)
--- a/src/mainboard/thomson/ip1000/Config.lb
+++ b/src/mainboard/thomson/ip1000/Config.lb
@@ -89,6 +89,9 @@ chip northbridge/intel/i82830         # Northbridge
       register "pirqg_routing" = "0x80"
       register "pirqh_routing" = "0x0b"
 
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
       device pci 1d.0 on end           # USB UHCI Controller #1
       device pci 1d.1 on end           # USB UHCI Controller #2
       device pci 1d.2 on end           # USB UHCI Controller #3

diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h
index d86c07e8e024b731d62ff0db410db272885d7d62..d159aa2be03b146639819fe19569d14925df5e51 100644 (file)
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801xx/chip.h
@@ -43,6 +43,8 @@ struct southbridge_intel_i82801xx_config {
        uint8_t pirqf_routing;
        uint8_t pirqg_routing;
        uint8_t pirqh_routing;
+       uint8_t ide0_enable;
+       uint8_t ide1_enable;
 };
 
 extern struct chip_operations southbridge_intel_i82801xx_ops;

diff --git a/src/southbridge/intel/i82801xx/i82801xx_ide.c b/src/southbridge/intel/i82801xx/i82801xx_ide.c
index f9ba3903e3fcfd834b850a72be665d87af899c74..4173cc6a756e6f1e6fe2e68a1cce8f61a4bd0e46 100644 (file)
--- a/src/southbridge/intel/i82801xx/i82801xx_ide.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_ide.c
@@ -27,29 +27,36 @@
 #include <device/pci_ids.h>
 #include "i82801xx.h"
 
+typedef struct southbridge_intel_i82801xx_config config_t;
+
 static void ide_init(struct device *dev)
 {
+       /* Get the chip configuration */
+       config_t *config = dev->chip_info; 
+
        /* TODO: Needs to be tested for compatibility with ICH5(R). */
        /* Enable IDE devices so the Linux IDE driver will work. */
        uint16_t ideTimingConfig;
-       int enable_primary = 1;
-       int enable_secondary = 1;
 
        ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
        ideTimingConfig &= ~IDE_DECODE_ENABLE;
-       if (enable_primary) {
+       if (!config || config->ide0_enable) {
                /* Enable primary IDE interface. */
                ideTimingConfig |= IDE_DECODE_ENABLE;
-               printk_debug("IDE0 ");
+               printk_debug("IDE0: Primary IDE interface is enabled\n");
+       } else {
+               printk_info("IDE0: Primary IDE interface is disabled\n");
        }
        pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
        ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
        ideTimingConfig &= ~IDE_DECODE_ENABLE;
-       if (enable_secondary) {
+       if (!config || config->ide1_enable) {
                /* Enable secondary IDE interface. */
                ideTimingConfig |= IDE_DECODE_ENABLE;
-               printk_debug("IDE1 ");
+               printk_debug("IDE1: Secondary IDE interface is enabled\n");
+       } else {
+               printk_info("IDE1: Secondary IDE interface is disabled\n");
        }
        pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }

diff --git a/targets/thomson/ip1000/Config.lb b/targets/thomson/ip1000/Config.lb
index 1e9e43ba028623f7cb0f390e755078c71c5f509e..aa507394d567b499ba9ae032cfb1fe64155d963a 100644 (file)
--- a/targets/thomson/ip1000/Config.lb
+++ b/targets/thomson/ip1000/Config.lb
@@ -51,7 +51,7 @@ option CONFIG_VIDEO_MB = 8
 ##
 ## Request this level of debugging output
 ##
-option DEFAULT_CONSOLE_LOGLEVEL = 9
+option DEFAULT_CONSOLE_LOGLEVEL = 7
 
 romimage "fallback"
        option USE_FALLBACK_IMAGE = 1