- With Xeon cpus it seems best to use the tsc calibrated with timer2 as
authorEric Biederman <ebiederm@xmission.com>
Sat, 23 Oct 2004 02:47:13 +0000 (02:47 +0000)
committerEric Biederman <ebiederm@xmission.com>
Sat, 23 Oct 2004 02:47:13 +0000 (02:47 +0000)
  the time source.  The apic timer also has a variable time base.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/intel/model_f2x/Config.lb
src/cpu/intel/model_f2x/apic_timer.c [deleted file]
src/mainboard/tyan/s2735/Options.lb

index b985ffc12dd4439d5806db43a8f1a155db5af508..e5121065b85a002510db5b0ef348f8882c14ec32 100644 (file)
@@ -1,5 +1,3 @@
-uses CONFIG_UDELAY_TSC
-
 dir /cpu/x86/mtrr
 dir /cpu/x86/fpu
 dir /cpu/x86/mmx
@@ -10,8 +8,3 @@ dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 driver model_f2x_init.o
 
-if CONFIG_UDELAY_TSC
-       dir /cpu/x86/tsc
-else
-       object apic_timer.o
-end
diff --git a/src/cpu/intel/model_f2x/apic_timer.c b/src/cpu/intel/model_f2x/apic_timer.c
deleted file mode 100644 (file)
index 5a81f91..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-
-void init_timer(void)
-{
-       /* Set the apic timer to no interrupts and periodic mode */
-       lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
-       /* Set the divider to 1, no divider */
-       lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
-       /* Set the initial counter to 0xffffffff */
-       lapic_write(LAPIC_TMICT, 0xffffffff);
-}
-
-void udelay(unsigned usecs)
-{
-       uint32_t start, value, ticks;
-       /* Calculate the number of ticks to run, our FSB runs a 200Mhz */
-       ticks = usecs * 200;
-       start = lapic_read(LAPIC_TMCCT);
-       do {
-               value = lapic_read(LAPIC_TMCCT);
-       } while((start - value) < ticks);
-       
-}
index cecb58bb9fe2305bb349873db5bca916c2c75fcd..c68fd37489224f41977b6641d80d700d62a920c2 100644 (file)
@@ -78,6 +78,12 @@ default HAVE_HARD_RESET=1
 #default HARD_RESET_DEVICE=4
 #default HARD_RESET_FUNCTION=0
 
+##
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
 ##
 ## Build code to export a programmable irq routing table
 ##