--- /dev/null
+#ifndef ARCH_MMIO_H
+#define ARCH_MMIO_H 1
+
+
+//extended read, GS is already set
+
+static inline __attribute__((always_inline)) uint8_t read8x(uint32_t addr)
+{
+ uint8_t value;
+ __asm__ volatile (
+ "movb %%gs:(%1), %0\n\t"
+ :"=a"(value): "b" (addr)
+ );
+ return value;
+}
+
+static inline __attribute__((always_inline)) uint16_t read16x(uint32_t addr)
+{
+ uint16_t value;
+ __asm__ volatile (
+ "movw %%gs:(%1), %0\n\t"
+ :"=a"(value): "b" (addr)
+ );
+
+ return value;
+
+}
+
+static inline __attribute__((always_inline)) uint32_t read32x(uint32_t addr)
+{
+ uint32_t value;
+ __asm__ volatile (
+ "movl %%gs:(%1), %0\n\t"
+ :"=a"(value): "b" (addr)
+ );
+
+ return value;
+
+}
+
+static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t value)
+{
+ __asm__ volatile (
+ "movb %1, %%gs:(%0)\n\t"
+ :: "b" (addr), "a" (value)
+ );
+
+}
+
+static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16_t value)
+{
+ __asm__ volatile (
+ "movw %1, %%gs:(%0)\n\t"
+ :: "b" (addr), "a" (value)
+ );
+
+}
+
+static inline __attribute__((always_inline)) void write32x(uint32_t addr, uint32_t value)
+{
+ __asm__ volatile (
+ "movl %1, %%gs:(%0)\n\t"
+ :: "b" (addr), "a" (value)
+ );
+}
+
+#endif /* ARCH_MMIO_H */
const struct pci_bus_operations pci_cf8_conf1;
const struct pci_bus_operations pci_cf8_conf2;
+#if MMCONF_SUPPORT==1
+const struct pci_bus_operations pci_ops_mmconf;
+#endif
+
void pci_set_method(device_t dev);
#endif /* ARCH_I386_PCI_OPS_H */
// inclusive of ANYTHING that uses a PCI bus.
#define PCI_CONF_REG_INDEX 0xcf8
#define PCI_CONF_REG_DATA 0xcfc
+
+#if PCI_IO_CFG_EXT == 0
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
+#else
+#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) )
+#endif
#endif
*((volatile uint32_t *)(addr)) = value;
}
+#if MMCONF_SUPPORT
+
+#include <arch/mmio_conf.h>
+
+#endif
+
static inline int log2(int value)
{
unsigned int r = 0;
#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
-typedef unsigned device_t;
+typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
+
+/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G,
+ * We don't need to set %fs, and %gs anymore
+ * Before that We need to use %gs, and leave %fs to other RAM access
+ */
static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
{
unsigned addr;
+#if PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where;
+#else
+ addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
+#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
return inb(0xCFC + (addr & 3));
}
+#if MMCONF_SUPPORT
+static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
+{
+ unsigned addr;
+ addr = dev | where;
+ return read8x(addr);
+}
+#endif
static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
{
+#if MMCONF_SUPPORT
+ return pci_mmio_read_config8(dev, where);
+#else
return pci_io_read_config8(dev, where);
+#endif
}
static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
{
unsigned addr;
+#if PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where;
+#else
+ addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
return inw(0xCFC + (addr & 2));
}
+#if MMCONF_SUPPORT
+static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
+{
+ unsigned addr;
+ addr = dev | where;
+ return read16x(addr);
+}
+#endif
+
static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
{
+#if MMCONF_SUPPORT
+ return pci_mmio_read_config16(dev, where);
+#else
return pci_io_read_config16(dev, where);
+#endif
}
static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
{
unsigned addr;
+#if PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where;
+#else
+ addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}
+#if MMCONF_SUPPORT
+static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
+{
+ unsigned addr;
+ addr = dev | where;
+ return read32x(addr);
+}
+#endif
+
static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
{
+#if MMCONF_SUPPORT
+ return pci_mmio_read_config32(dev, where);
+#else
return pci_io_read_config32(dev, where);
+#endif
}
static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
{
unsigned addr;
+#if PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where;
+#else
+ addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
}
+#if MMCONF_SUPPORT
+static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
+{
+ unsigned addr;
+ addr = dev | where;
+ write8x(addr, value);
+}
+#endif
+
static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
{
+#if MMCONF_SUPPORT
+ pci_mmio_write_config8(dev, where, value);
+#else
pci_io_write_config8(dev, where, value);
+#endif
}
static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
{
unsigned addr;
+#if PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where;
+#else
+ addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
outw(value, 0xCFC + (addr & 2));
}
+#if MMCONF_SUPPORT
+static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
+{
+ unsigned addr;
+ addr = dev | where;
+ write16x(addr, value);
+}
+#endif
+
static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
{
+#if MMCONF_SUPPORT
+ pci_mmio_write_config16(dev, where, value);
+#else
pci_io_write_config16(dev, where, value);
+#endif
}
static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
{
unsigned addr;
+#if PCI_IO_CFG_EXT == 0
addr = (dev>>4) | where;
+#else
+ addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
}
+#if MMCONF_SUPPORT
+static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
+{
+ unsigned addr;
+ addr = dev | where;
+ write32x(addr, value);
+}
+#endif
+
static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
{
+#if MMCONF_SUPPORT
+ pci_mmio_write_config32(dev, where, value);
+#else
pci_io_write_config32(dev, where, value);
+#endif
}
#define PCI_DEV_INVALID (0xffffffffU)
static device_t pci_locate_device(unsigned pci_id, device_t dev)
{
- for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
+ for(; dev <= PCI_DEV(255|(((1<<PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id) {
uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
object c_start.S
object cpu.c
object pci_ops_conf1.c
object pci_ops_conf2.c
+object pci_ops_mmconf.c
object pci_ops_auto.c
object exception.c
if CONFIG_USE_INIT
- initobject printk_init.o
+ if CONFIG_USE_PRINTK_IN_CAR
+ initobject printk_init.o
+ end
end
#include <console/loglevel.h>
-#if CONFIG_USE_INIT == 0
+#if CONFIG_USE_PRINTK_IN_CAR == 0
static void __console_tx_byte(unsigned char byte)
{
uart_tx_byte(byte);
* Functions for accessing PCI configuration space with type 1 accesses
*/
+#if PCI_IO_CFG_EXT == 0
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
+#else
+#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) )
+#endif
static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where)
{
--- /dev/null
+#if MMCONF_SUPPORT
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pciconf.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+
+/*
+ * Functions for accessing PCI configuration space with mmconf accesses
+ */
+
+#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \
+ (((SEGBUS) & 0xFFF) << 20) | \
+ (((DEVFN) & 0xFF) << 12) | \
+ ((WHERE) & 0xFFF))
+
+#include <arch/mmio_conf.h>
+
+static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where)
+{
+ return (read8x(PCI_MMIO_ADDR(bus, devfn, where)));
+}
+
+static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where)
+{
+ return (read16x(PCI_MMIO_ADDR(bus, devfn, where)));
+}
+
+static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where)
+{
+ return (read32x(PCI_MMIO_ADDR(bus, devfn, where)));
+}
+
+static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value)
+{
+ write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
+}
+
+static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value)
+{
+ write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
+}
+
+static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value)
+{
+ write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
+}
+
+
+const struct pci_bus_operations pci_ops_mmconf =
+{
+ .read8 = pci_mmconf_read_config8,
+ .read16 = pci_mmconf_read_config16,
+ .read32 = pci_mmconf_read_config32,
+ .write8 = pci_mmconf_write_config8,
+ .write16 = pci_mmconf_write_config16,
+ .write32 = pci_mmconf_write_config32,
+};
+
+#endif
export always
comment "Default flow control settings for the 8250 serial console uart"
end
+
+define CONFIG_USE_PRINTK_IN_CAR
+ default 0
+ export always
+ comment "use printk instead of print in CAR stage code"
+end
+
###############################################
# Mainboard options
# Options for memory mapped I/O
###############################################
+define PCI_IO_CFG_EXT
+ default 0
+ export always
+ comment "allow 4K register space via io CFG port"
+end
+
define PCIC0_CFGADDR
default none
format "0x%x"
comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
end
+define PCI_BUS_SEGN_BITS
+ default 0
+ export always
+ comment "It could be 0, 1, 2, 3 and 4 only"
+end
+
+define MMCONF_SUPPORT
+ default 0
+ export always
+ comment "enable mmconfig for pci conf"
+end
+
define HW_MEM_HOLE_SIZEK
default 0
export always
uses CONFIG_CONSOLE_BTEXT
uses CONFIG_CONSOLE_LOGBUF
uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
object printk.o
if CONFIG_CONSOLE_SERIAL8250
object vsprintf.o
if CONFIG_USE_INIT
+ if CONFIG_USE_PRINTK_IN_CAR
initobject vtxprintf.o
+ end
end
*/
static inline void print_debug_cp_run(const char *strval, uint32_t val)
{
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%08x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
/* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
+
__asm__ volatile (
/* We don't need cache as ram for now on */
);
}
-/* be warned, this file will be used core 0 / node 0 and ram stack is ready*/
static void disable_cache_as_ram_bsp(void)
{
- __asm__ volatile (
-
- "pushl %ecx\n\t"
- "pushl %edx\n\t"
- "pushl %eax\n\t"
-
+ __asm__ volatile (
+// "pushl %eax\n\t"
+ "pushl %edx\n\t"
+ "pushl %ecx\n\t"
);
disable_cache_as_ram();
-
- __asm__ volatile (
-
- "popl %eax\n\t"
- "popl %edx\n\t"
- "popl %ecx\n\t"
-
+ __asm__ volatile (
+ "popl %ecx\n\t"
+ "popl %edx\n\t"
+// "popl %eax\n\t"
);
}
-
static inline void print_debug_pcar(const char *strval, uint32_t val)
{
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%08x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
#if K8_SET_FIDVID == 1
-#define K8_SET_FIDVID_DEBUG 0
+#define K8_SET_FIDVID_DEBUG 0
+
+#define K8_SET_FIDVID_ONE_BY_ONE 1
#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
static inline void print_debug_fv(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
- #if CONFIG_USE_INIT==1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%x\r\n", str, val);
#else
print_debug(str); print_debug_hex32(val); print_debug("\r\n");
static inline void print_debug_fv_8(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
- #if CONFIG_USE_INIT==1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%02x\r\n", str, val);
#else
print_debug(str); print_debug_hex8(val); print_debug("\r\n");
static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
{
#if K8_SET_FIDVID_DEBUG == 1
- #if CONFIG_USE_INIT==1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%x%x\r\n", str, val, val2);
#else
print_debug(str); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
}
}
+#if K8_SET_FIDVID_ONE_BY_ONE == 0
+static unsigned set_fidvid_without_init(unsigned fidvid)
+{
+
+ msr_t msr;
+ uint32_t vid;
+ uint32_t fid;
+
+ fid = (fidvid >> 8) & 0x3f;
+ vid = (fidvid >> 16) & 0x3f;
+
+ // set new FID/VID
+ msr.hi = 1;
+ msr.lo = (vid<<8) | fid;
+ wrmsr(0xc0010041, msr);
+ return fidvid;
+}
+#endif
+
static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
{
//for (cur, new) there is one <1600MHz x8 to find out next_fid
apicidx = lapicid();
if(apicid!=apicidx) {
-#if CONFIG_USE_INIT == 1
+#if CONFIG_USE_PRINTK_IN_CAR
printk_err("wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
#else
print_err("wrong apicid, we want change "); print_err_hex8(apicid); print_err(" but it is "); print_err_hex8(apicidx); print_err("\r\n");
fidvid = (vid_cur<< 16) | (fid_cur<<8);
if(showmessage) {
- if((fid!=fid_cur) || (vid!=vid_cur)) {
- print_err("set fidvid failed\r\n");
+ if(vid!=vid_cur) {
+ print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n");
+ }
+ if(fid!=fid_cur) {
+ print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n");
}
}
{
uint32_t send;
- uint32_t readback;
+ uint32_t readback = 0;
+ unsigned timeout = 1;
msr_t msr;
uint32_t vid_cur;
uint32_t fid_cur;
send |= ((msr.hi>>(48-32)) & 0x3f) << 16; //max vid
send |= (apicid<<24); // ap apicid
+#if K8_SET_FIDVID_ONE_BY_ONE == 1
vid_cur = msr.hi & 0x3f;
fid_cur = msr.lo & 0x3f;
msr.hi = 1;
msr.lo = (vid_cur<<8) | (fid_cur);
wrmsr(0xc0010041, msr);
+#endif
- wait_cpu_state(bsp_apicid, 1);
+ timeout = wait_cpu_state(bsp_apicid, 1);
+ if(timeout) {
+ print_initcpu8("fidvid_ap_stage1: time out while reading from BSP on ", apicid);
+ }
//send signal to BSP about this AP max fid and vid
lapic_write(LAPIC_MSG_REG, send | 1); //AP at state 1 that sent our fid and vid
// wait_cpu_state(bsp_apicid, 2);// don't need we can use apicid directly
- loop = 100000;
+ loop = 1000000;
while(--loop>0) {
//remote read BSP signal that include vid and fid that need to set
if(lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback)!=0) continue;
}
if(loop>0) {
+ #if K8_SET_FIDVID_ONE_BY_ONE == 1
readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP
+ #else
+ readback = set_fidvid_without_init(readback & 0xffff00); // this AP
+ #endif
//send signal to BSP that this AP fid/vid is set // allow to change state2 is together with apicid
send = (apicid<<24) | (readback & 0x00ffff00); // AP at state that We set the requested fid/vid
+ } else {
+ print_initcpu8("fidvid_ap_stage2: time out while reading from BSP on ", apicid);
}
lapic_write(LAPIC_MSG_REG, send | 2);
- wait_cpu_state(bsp_apicid, 3);
+ timeout = wait_cpu_state(bsp_apicid, 3);
+ if(timeout) {
+ print_initcpu8("fidvid_ap_stage3: time out while reading from BSP on ", apicid);
+ }
}
static unsigned calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp )
{
- unsigned readback;
+ unsigned readback = 0;
+ unsigned timeout = 1;
struct fidvid_st *fvp = gp;
int loop;
print_debug_fv("state 1: ap_apicid=", ap_apicid);
- loop = 100000;
+ loop = 1000000;
while(--loop > 0) {
if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) continue;
- if((readback & 0xff) == 1) break; //target ap is in stage 1
+ if((readback & 0xff) == 1) {
+ timeout = 0;
+ break; //target ap is in stage 1
+ }
}
+ if(timeout) {
+ print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid);
+ return;
+ }
print_debug_fv("\treadback=", readback);
}
static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp)
{
- unsigned readback;
+ unsigned readback = 0;
+ unsigned timeout = 1;
struct fidvid_st *fvp = gp;
int loop;
lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid<<24) | 2); // all set to state2
- loop = 100000;
+ loop = 1000000;
while(--loop > 0) {
if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) continue;
- if((readback & 0xff) == 2) break; // target ap is stage 2, and it'd FID has beed set
+ if((readback & 0xff) == 2) {
+ timeout = 0;
+ break; // target ap is stage 2, and it'd FID has beed set
+ }
}
+ if(timeout) {
+ print_initcpu8("fidvid_bsp_stage2: time out while reading from ap ", ap_apicid);
+ return;
+ }
+
print_debug_fv("\treadback=", readback);
}
#endif
+#if K8_SET_FIDVID_ONE_BY_ONE == 1
// set BSP fid and vid
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
print_debug_fv("common_fidvid=", fv.common_fidvid);
+#endif
//for all APs ( We know the APIC ID of all AP even the APIC ID is lifted)
// send signal to the AP it could change it's fid/vid
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
#endif
+#if K8_SET_FIDVID_ONE_BY_ONE == 0
+ // set BSP fid and vid
+ print_debug_fv("bsp apicid=", bsp_apicid);
+ fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
+ print_debug_fv("common_fidvid=", fv.common_fidvid);
+
+#endif
+
lapic_write(LAPIC_MSG_REG, fv.common_fidvid | (bsp_apicid<<24) | 3); // clear the state
//here wait a while, so last ap could read pack, and stop it, don't call init_timer too early or just don't use init_timer
static inline void print_initcpu8 (const char *strval, unsigned val)
{
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%02x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
static inline void print_initcpu8_nocr (const char *strval, unsigned val)
{
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%02x", strval, val);
#else
print_debug(strval); print_debug_hex8(val);
static inline void print_initcpu16 (const char *strval, unsigned val)
{
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%04x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex16(val); print_debug("\r\n");
static inline void print_initcpu(const char *strval, unsigned val)
{
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%08x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
{
- #if CONFIG_USE_INIT == 0
+ #if CONFIG_USE_PRINTK_IN_CAR
+ printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
+ #else
print_debug(str);
print_debug(" ---- {APICID = "); print_debug_hex8(apicid);
print_debug(" NODEID = "), print_debug_hex8(id.nodeid); print_debug(" COREID = "), print_debug_hex8(id.coreid);
print_debug("} --- \r\n");
- #else
- printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
#endif
}
-static void wait_cpu_state(unsigned apicid, unsigned state)
+static unsigned wait_cpu_state(unsigned apicid, unsigned state)
{
- unsigned readback;
- int loop =100000;
+ unsigned readback = 0;
+ unsigned timeout = 1;
+ int loop = 2000000;
while(--loop>0) {
if(lapic_remote_read(apicid, LAPIC_MSG_REG, &readback)!=0) continue;
- if((readback & 0xff) == state) break; //target cpu is in stage started
+ if((readback & 0xff) == state) {
+ timeout = 0;
+ break; //target cpu is in stage started
+ }
}
+ if(timeout) {
+ if(readback) {
+ timeout = readback;
+ }
+ }
+
+ return timeout;
}
static void wait_ap_started(unsigned ap_apicid, void *gp )
{
- wait_cpu_state(ap_apicid, 0x33); // started
- print_initcpu8_nocr(" ", ap_apicid);
+ unsigned timeout;
+ timeout = wait_cpu_state(ap_apicid, 0x33); // started
+ if(timeout) {
+ print_initcpu8_nocr("*", ap_apicid);
+ print_initcpu("*", timeout);
+ }
+ else {
+ print_initcpu8_nocr(" ", ap_apicid);
+ }
}
static void wait_all_aps_started(unsigned bsp_apicid)
disable_cache_as_ram(); // inline
stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
}
-#if RAMINIT_SYSINFO == 1
-#if MEM_TRAIN_SEQ != 1
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) {}
-#else
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall);
+#ifndef MEM_TRAIN_SEQ
+#define MEM_TRAIN_SEQ 0
#endif
+
+#if MEM_TRAIN_SEQ == 1
+static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall);
#endif
#if RAMINIT_SYSINFO == 1
-
static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo)
#else
static unsigned init_cpus(unsigned cpu_init_detectedx)
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x33); // mark the cpu is started
if(apicid != bsp_apicid) {
+ unsigned timeout=1;
+ unsigned loop = 100;
#if K8_SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (K8_SET_FIDVID_CORE0_ONLY == 1)
if(id.coreid == 0 ) // only need set fid for core0
#endif
// We need to stop the CACHE as RAM for this CPU, really?
- wait_cpu_state(bsp_apicid, 0x44);
+ while(timeout && (loop-->0)) {
+ timeout = wait_cpu_state(bsp_apicid, 0x44);
+ }
+ if(timeout) {
+ print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid);
+ }
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
set_init_ram_access();
- #if RAMINIT_SYSINFO == 1
+ #if MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU);
#endif
{ X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */
{ X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */
{ X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */
+ { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 Socket AM2: Athlon64 */
{ X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */
{ X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */
{ X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */
+ { X86_VENDOR_AMD, 0xc0f13 }, /* AM2 : Athlon64 FX*/
+ { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 Socket AM2: Athlon64 */
#endif
{ 0, 0 },
memcpy(buffer, "Root Device", 12);
break;
case DEVICE_PATH_PCI:
+#if PCI_BUS_SEGN_BITS
+ sprintf(buffer, "PCI: %04x:%02x:%02x.%01x",
+ dev->bus->secondary>>8, dev->bus->secondary & 0xff,
+ PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+#else
sprintf(buffer, "PCI: %02x:%02x.%01x",
dev->bus->secondary,
PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+#endif
break;
case DEVICE_PATH_PNP:
sprintf(buffer, "PNP: %04x.%01x",
end = resource_end(resource);
buf[0] = '\0';
if (resource->flags & IORESOURCE_PCI_BRIDGE) {
+#if PCI_BUS_SEGN_BITS
+ sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link[0].secondary & 0xff);
+#else
sprintf(buf, "bus %02x ", dev->link[0].secondary);
+#endif
}
printk_debug(
"%s %02x <- [0x%010Lx - 0x%010Lx] %s%s%s\n",
return;
}
- printk_debug("%s: seeking driver for %x:%x class %x\n",
- __FUNCTION__, dev->vendor, dev->device, dev->class);
- /* Look through the list of setup drivers and find one for
+ /* Look through the list of setup drivers and find one for
* this pci device
*/
for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
device_t old_devices;
device_t child;
- printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
+#if PCI_BUS_SEGN_BITS
+ printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
+#else
+ printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
+#endif
old_devices = bus->children;
bus->children = 0;
*
* Return how far we've got finding sub-buses.
*/
- printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
+ printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
post_code(0x55);
return max;
}
if (!(result & CFG1_STRT)) {
printk_debug("ADM1027: monitoring would not enable\r\n");
}
+ printk_debug("ADM1027: monitoring enabled\r\n");
}
static void adm1027_init(device_t dev)
unsigned hc_possible_num;
unsigned pci1234[HC_POSSIBLE_NUM];
unsigned hcdn[HC_POSSIBLE_NUM];
+ unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type
unsigned sbdn;
unsigned sblk;
uses HAVE_FALLBACK_BOOT
uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
object clog2.o
object uart8250.o
makedefine .PHONY : version.o
if CONFIG_USE_INIT
+ if CONFIG_USE_PRINTK_IN_CAR
initobject uart8250.c
+ end
initobject memset.o
initobject memcpy.o
initobject memcmp.o
print_err("E\n");
enable_smbus();
-#if 1
+#if 0
dump_spd_registers(&cpu[0]);
#endif
print_err("F\n");
action "mv pci2.hex ssdt2.c"
end
object ./ssdt2.o
+ makerule ssdt3.c
+ depends "$(MAINBOARD)/dx/pci3.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
+ action "mv pci3.hex ssdt3.c"
+ end
+ object ./ssdt3.o
+ makerule ssdt4.c
+ depends "$(MAINBOARD)/dx/pci4.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
+ action "mv pci4.hex ssdt4.c"
+ end
+ object ./ssdt4.o
end
end
uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
+
###
### Build options
###
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
+
+##
+## for rev F training on AP purpose
+##
default CONFIG_AP_CODE_IN_CAR=1
default MEM_TRAIN_SEQ=1
-
default WAIT_BEFORE_CPUS_INIT=1
##
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc-3.4.5 -m32"
-default HOSTCC="gcc-3.4.5"
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
## The Serial Console
##
+default CONFIG_USE_PRINTK_IN_CAR=0
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
+++ /dev/null
-echo "Creating for ACPI hex for bus 1 Conf"
-cd dx
-iasl -tc dsdt_lb.dsl
-rm DSDT.aml
-mv dsdt_lb.hex ../dsdt.c
-iasl -tc pci2.asl
-rm SSDT2.aml
-perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex
-mv pci2.hex ../ssdt2.c
-cd ..
-echo "Creating for ACPI hex for bus 0 Conf"
-cd dx_bus0
-iasl -tc dsdt_lb.dsl
-rm DSDT.aml
-mv dsdt_lb.hex ../dsdt_bus0.c
-iasl -tc pci2.asl
-rm SSDT2.aml
-perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex
-mv pci2.hex ../ssdt2_bus0.c
-cd ..
-echo "Creating ssdt"
-iasl -tc ssdt_lb_x.dsl
-rm SSDT.aml
-perl -e 's/AmlCode/AmlCode_ssdt/g' -pi ssdt_lb_x.hex
-mv ssdt_lb_x.hex ssdt.c
#if ACPI_SSDTX_NUM >= 1
extern unsigned char AmlCode_ssdt2[];
-//extern unsigned char AmlCode_ssdt3[];
-//extern unsigned char AmlCode_ssdt4[];
-//extern unsigned char AmlCode_ssdt5[];
-//extern unsigned char AmlCode_ssdt6[];
-//extern unsigned char AmlCode_ssdt7[];
-//extern unsigned char AmlCode_ssdt8[];
+extern unsigned char AmlCode_ssdt3[];
+extern unsigned char AmlCode_ssdt4[];
#endif
#define IO_APIC_ADDR 0xfec00000UL
gsi_base+=7;
}
}
+
+ int i;
+ int j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ unsigned d;
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ // 8131 need to use +4
+
+ switch (sysconf.hcid[i]) {
+ case 1:
+ d = 7;
+ break;
+ case 3:
+ d = 4;
+ break;
+ }
+ switch (sysconf.hcid[i]) {
+ case 1:
+ case 3:
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
+ res->base, gsi_base );
+ gsi_base+=d;
+ }
+ }
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
+ res->base, gsi_base );
+ gsi_base+=d;
+
+ }
+ }
+ break;
+ }
+
+ j++;
+ }
+
}
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
extern void update_ssdt(void *ssdt);
+void update_ssdtx(void *ssdtx, int i)
+{
+ uint8_t *PCI;
+ uint8_t *HCIN;
+ uint8_t *UID;
+
+ PCI = ssdtx + 0x32;
+ HCIN = ssdtx + 0x39;
+ UID = ssdtx + 0x40;
+
+ if(i<7) {
+ *PCI = (uint8_t) ('4' + i - 1);
+ }
+ else {
+ *PCI = (uint8_t) ('A' + i - 1 - 6);
+ }
+ *HCIN = (uint8_t) i;
+ *UID = (uint8_t) (i+3);
+
+ /* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *ssdtx;
+ unsigned char *p;
unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
acpi_add_table(rsdt,ssdt);
#if ACPI_SSDTX_NUM >= 1
- // we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1]
- AmlCode_ssdtx[1] = AmlCode_ssdt2;
-// AmlCode_ssdtx[2] = AmlCode_ssdt3;
-// AmlCode_ssdtx[3] = AmlCode_ssdt4;
-// AmlCode_ssdtx[4] = AmlCode_ssdt5;
-// AmlCode_ssdtx[5] = AmlCode_ssdt6;
-// AmlCode_ssdtx[6] = AmlCode_ssdt7;
-// AmlCode_ssdtx[7] = AmlCode_ssdt8;
-
- //same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table
-
- for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
- if((sysconf.pci1234[i] & 1) != 1 ) continue;
- printk_debug("ACPI: * SSDT for PCI%d\n", i+1); //pci0 and pci1 are in dsdt
- ssdtx = (acpi_header_t *)current;
- current += ((acpi_header_t *)AmlCode_ssdtx[i])->length;
- memcpy((void *)ssdtx, (void *)AmlCode_ssdtx[i], ((acpi_header_t *)AmlCode_ssdtx[i])->length);
- acpi_add_table(rsdt,ssdtx);
- }
-#endif
+ //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
+
+ for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
+ if((sysconf.pci1234[i] & 1) != 1 ) continue;
+ uint8_t c;
+ if(i<7) {
+ c = (uint8_t) ('4' + i - 1);
+ }
+ else {
+ c = (uint8_t) ('A' + i - 1 - 6);
+ }
+ printk_debug("ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
+ current = ( current + 0x07) & -0x08;
+ ssdtx = (acpi_header_t *)current;
+ switch(sysconf.hcid[i]) {
+ case 1: //8132
+ p = AmlCode_ssdt2;
+ break;
+ case 2: //8151
+ p = AmlCode_ssdt3;
+ break;
+ case 3: //8131
+ p = AmlCode_ssdt4;
+ break;
+ default:
+ continue;
+ }
+ current += ((acpi_header_t *)p)->length;
+ memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length);
+ update_ssdtx((void *)ssdtx, i);
+ ssdtx->checksum = 0;
+ ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
+ acpi_add_table(rsdt,ssdtx);
+ }
+#endif
/* FACS */
printk_debug("ACPI: * FACS\n");
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+ #include "lib/memcpy.c"
+ #if CONFIG_USE_PRINTK_IN_CAR == 1
+ #include "lib/uart8250.c"
+ #include "console/vtxprintf.c"
+ #include "arch/i386/lib/printk_init.c"
+ #endif
+#endif
+
#include "arch/i386/lib/console.c"
#if 0
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
//#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
id = get_node_core_id_x();
+#if CONFIG_USE_PRINTK_IN_CAR
+ printk_debug("CODE IN CACHE ON NODE: %02x\n");
+#else
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+#endif
train_ram(id.nodeid, sysinfo, sysinfox);
+++ /dev/null
-rm dsdt.c
-rm ssdt2.c
-rm dsdt_bus0.c
-rm ssdt2_bus0.c
-rm ssdt.c
//used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define K8_SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
-//0: three for in bsp, only this one support F0_F1 workaround
-//1: on every core0
-//2: one for on bsp
-//#define MEM_TRAIN_SEQ 1
-
+#if K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
#include <stdint.h>
#include <device/pci_def.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "cpu/x86/bist.h"
#if USE_FAILOVER_IMAGE==0
+#include "cpu/x86/bist.h"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
+ #if CONFIG_USE_PRINTK_IN_CAR == 1
+ #include "lib/uart8250.c"
+ #include "console/vtxprintf.c"
+ #include "arch/i386/lib/printk_init.c"
+ #endif
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
return smbus_read_byte(device, address);
}
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit_f.c"
+#include "northbridge/amd/amdk8/raminit.c"
#include "sdram/generic_sdram.c"
unsigned bsp_apicid = 0;
if (bist == 0) {
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(CONFIG_MAX_PHYSICAL_CPUS, sysinfo->ctrl, spd_addr);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
- setup_serengeti_cheetah_resource_map();
+ setup_mb_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
allow_all_aps_stop(bsp_apicid);
-#if 0
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-#endif
enable_smbus();
External (\_SB.PCI0.LNKC, DeviceObj)
External (\_SB.PCI0.LNKD, DeviceObj)
- Device (PCI2)
+ Device (PCIX)
{
// BUS ? Second HT Chain
- Name (HCIN, 0x01) // HC2
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
Name (_HID, "PNP0A03")
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
{
- Return (DADD(GHCN(HCIN), 0x00180000))
+ Return (DADD(GHCN(HCIN), 0x00000000))
}
- Name (_UID, 0x03)
-
Method (_BBN, 0, NotSerialized)
{
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- Include ("amd8151.asl")
+ Include ("amd8132_2.asl")
static unsigned get_bus_conf_done = 0;
+static unsigned get_hcid(unsigned i)
+{
+ unsigned id = 0;
+
+ unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+
+ unsigned devn = sysconf.hcdn[i] & 0xff;
+
+ device_t dev;
+
+ dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+
+ switch (dev->device) {
+ case 0x7458: //8132
+ id = 1;
+ break;
+ case 0x7454: //8151
+ id = 2;
+ break;
+ case 0x7450: //8131
+ id = 3;
+ break;
+ }
+
+ // we may need more way to find out hcid: subsystem id? GPIO read ?
+
+ // we need use id for 1. bus num, 2. mptable, 3. acpi table
+
+ return id;
+}
+
void get_bus_conf(void)
{
unsigned apicid_base;
device_t dev;
- int i;
+ int i, j;
struct mb_sysconf_t *m;
if(get_bus_conf_done == 1) return; //do it only once
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
m->sbdn3 = sysconf.hcdn[0] & 0xff;
- m->sbdn5 = sysconf.hcdn[1] & 0xff;
m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
m->bus_8111_0 = m->bus_8132_0;
}
/* HT chain 1 */
- if((sysconf.pci1234[1] & 0x1) == 1) {
- m->bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff;
- /* 8151 */
- dev = dev_find_slot(m->bus_8151_0, PCI_DEVFN(m->sbdn5+1, 0));
-
- if (dev) {
- m->bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-// printk_debug("bus_8151_1=%d\n",bus_8151_1);
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- }
- else {
- printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151_0, m->sbdn5+1);
- }
+ j=0;
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+ // check hcid type here
+ sysconf.hcid[i] = get_hcid(i);
+
+ switch(sysconf.hcid[i]) {
+
+ case 1: //8132
+ case 3: //8131
+
+ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
+
+ m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
+
+ /* 8132-1 */
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0));
+ if (dev) {
+ m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
+ }
+
+ /* 8132-2 */
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
+ if (dev) {
+ m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ m->bus_isa++;
+ // printk_debug("bus_isa=%d\n",bus_isa);
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
+ }
+
+ break;
+
+ case 2: //8151
+
+ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
+ m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
+ /* 8151 */
+ dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0));
+
+ if (dev) {
+ m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ // printk_debug("bus_8151_1=%d\n",bus_8151[j][1]);
+ m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ m->bus_isa++;
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
+ }
+
+ break;
+ }
+
+ j++;
}
+
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(3);
m->apicid_8111 = apicid_base+0;
m->apicid_8132_1 = apicid_base+1;
m->apicid_8132_2 = apicid_base+2;
+ for(i=0;i<j;i++) {
+ m->apicid_8132a[i][0] = apicid_base + 3 + i*2;
+ m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1;
+ }
+
}
//pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
-
- if(sysconf.pci1234[1] & 0xf) {
- //agp bridge
- write_pirq_info(pirq_info, m->bus_8151_0, (m->sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- }
- pirq_info++; slot_num++;
-
+ int j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+ unsigned devn = sysconf.hcdn[i] & 0xff;
+
+ write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+ j++;
+
+ }
+
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
unsigned char bus_8132_2;
unsigned char bus_8111_0;
unsigned char bus_8111_1;
- unsigned char bus_8151_0;
- unsigned char bus_8151_1;
- unsigned apicid_8111;
- unsigned apicid_8132_1;
- unsigned apicid_8132_2;
-
- unsigned sbdn3;
- unsigned sbdn5;
+
+ unsigned char bus_8132a[7][3];
+
+ unsigned char bus_8151[7][2];
+
+ unsigned apicid_8111;
+ unsigned apicid_8132_1;
+ unsigned apicid_8132_2;
+ unsigned apicid_8132a[7][2];
+
+ unsigned sbdn3;
+ unsigned sbdn3a[7];
+ unsigned sbdn5[7];
+
};
#endif
struct mp_config_table *mc;
unsigned char bus_num;
- int i;
+ int i, j;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
}
}
+
+ j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+ switch(sysconf.hcid[i]) {
+ case 1: // 8132
+ case 3: // 8131
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ }
+ }
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ }
+ }
+ break;
+ }
+ j++;
+ }
+
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
// Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
- if(sysconf.pci1234[1] & 0xf) {
- // Slot AGP
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151_1, 0x0, m->apicid_8111, 0x11);
- }
-
//Slot 3 PCI 32
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
}
+ j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ int ii;
+ device_t dev;
+ struct resource *res;
+ switch(sysconf.hcid[i]) {
+ case 1:
+ case 3:
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ //Slot 1 PCI-X 133/100/66
+ for(ii=0;ii<4;ii++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+ }
+ }
+ }
+
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ //Slot 2 PCI-X 133/100/66
+ for(ii=0;ii<4;ii++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+ }
+ }
+ }
+
+ break;
+ case 2:
+
+ // Slot AGP
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
+ break;
+ }
+
+ j++;
+ }
+
+
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
/*
- * AMD serengeti_cheetah needs a different resource map
*
*/
-static void setup_serengeti_cheetah_resource_map(void)
+static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+if USE_FAILOVER_IMAGE
+ default ROM_SECTION_SIZE = FAILOVER_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+ else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
default ROM_SECTION_OFFSET = 0
+ end
end
##
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+if USE_FAILOVER_IMAGE
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+ if USE_FALLBACK_IMAGE
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+ else
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+ end
+end
arch i386 end
if HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
- if SB_HT_CHAIN_ON_BUS0
- makerule dsdt.c
- depends "$(MAINBOARD)/dx_bus0/dsdt_lb.dsl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/dsdt_lb.dsl"
- action "mv dsdt_lb.hex dsdt.c"
- end
- else
- makerule dsdt.c
- depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
- action "mv dsdt_lb.hex dsdt.c"
- end
+ makerule dsdt.c
+ depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+ action "mv dsdt_lb.hex dsdt.c"
end
object ./dsdt.o
- makerule ssdt.c
- depends "$(MAINBOARD)/ssdt_lb_x.dsl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl"
- action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex"
- action "mv ssdt_lb_x.hex ssdt.c"
- end
- object ./ssdt.o
+ #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
if ACPI_SSDTX_NUM
- if SB_HT_CHAIN_ON_BUS0
- makerule ssdt2.c
+ makerule ssdt2.c
depends "$(MAINBOARD)/dx/pci2.asl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
action "mv pci2.hex ssdt2.c"
- end
- else
- makerule ssdt2.c
- depends "$(MAINBOARD)/dx_bus0/pci2.asl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/dx_bus0/pci2.asl"
- action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
- action "mv pci2.hex ssdt2.c"
- end
- end
+ end
object ./ssdt2.o
end
end
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
else
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-
-if USE_FALLBACK_IMAGE
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
+ end
end
mainboardinit cpu/x86/32bit/entry32.inc
##
## Build our reset vector (This is where linuxBIOS is entered)
##
-if USE_FALLBACK_IMAGE
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
else
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
+ end
end
if USE_DCACHE_RAM
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover_failover.lds
+ end
+ end
+else
+ if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
+ end
end
###
uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
+uses USE_FAILOVER_IMAGE
+uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
+uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses CONFIG_PCI_64BIT_PREF_MEM
+uses CONFIG_LB_MEM_TOPK
+
+uses CONFIG_USE_PRINTK_IN_CAR
###
### Build options
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
-#256K
-default FALLBACK_SIZE=0x40000
+#default FALLBACK_SIZE=0x40000
+
+#FALLBACK: 256K-4K
+default FALLBACK_SIZE=0x3f000
+#FAILOVER: 4K
+default FAILOVER_SIZE=0x01000
+
+default CONFIG_LB_MEM_TOPK=2048
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
+default HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#default SERIAL_CPU_INIT=0
+default SERIAL_CPU_INIT=0
default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x8
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
-default HW_MEM_HOLE_SIZEK=0x200000
+#default HW_MEM_HOLE_SIZEK=0x200000
#1G
-#default HW_MEM_HOLE_SIZEK=0x100000
+default HW_MEM_HOLE_SIZEK=0x100000
#512M
#default HW_MEM_HOLE_SIZEK=0x80000
default CONFIG_PCI_ROM_RUN=1
#HT Unit ID offset
-default HT_CHAIN_UNITID_BASE=0x4
+default HT_CHAIN_UNITID_BASE=0xa
#real SB Unit ID
-default HT_CHAIN_END_UNITID_BASE=0x1
+default HT_CHAIN_END_UNITID_BASE=0x6
#make the SB HT chain on bus 0
-default SB_HT_CHAIN_ON_BUS0=1
+default SB_HT_CHAIN_ON_BUS0=2
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
## LinuxBIOS C code runs at this location in RAM
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32"
+default HOSTCC="gcc-4.0.2"
##
## Disable the gdb stub by default
##
## The Serial Console
##
+default CONFIG_USE_PRINTK_IN_CAR=1
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
-#define DUMP_ACPI_TABLES 1
+#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
static void dump_mem(unsigned start, unsigned end)
}
#endif
-#define HC_POSSIBLE_NUM 8
extern unsigned char AmlCode[];
extern unsigned char AmlCode_ssdt[];
extern unsigned apicid_8132_1;
extern unsigned apicid_8132_2;
-extern unsigned pci1234[];
-extern unsigned hc_possible_num;
-extern unsigned sblk;
-extern unsigned sbdn;
-extern unsigned hcdn[];
-
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int gsi_base=0x18;
{
device_t dev;
struct resource *res;
- dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0]&0xff), 1));
+ dev = dev_find_slot(bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
}
}
- dev = dev_find_slot(bus_8132_0, PCI_DEVFN((hcdn[0] & 0xff)+1, 1));
+ dev = dev_find_slot(bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
return current;
}
-//FIXME: next could be moved to northbridge/amd/amdk8/amdk8_acpi.c or cpu/amd/k8/k8_acpi.c begin
-static void int_to_stream(uint32_t val, uint8_t *dest)
-{
- int i;
- for(i=0;i<4;i++) {
- *(dest+i) = (val >> (8*i)) & 0xff;
- }
-}
-
extern void get_bus_conf(void);
-static void update_ssdt(void *ssdt)
-{
- uint8_t *BUSN;
- uint8_t *MMIO;
- uint8_t *PCIO;
- uint8_t *SBLK;
- uint8_t *TOM1;
- uint8_t *SBDN;
- uint8_t *HCLK;
- uint8_t *HCDN;
-
- int i;
- device_t dev;
- uint32_t dword;
- msr_t msr;
-
- BUSN = ssdt+0x3a; //+5 will be next BUSN
- MMIO = ssdt+0x57; //+5 will be next MMIO
- PCIO = ssdt+0xaf; //+5 will be next PCIO
- SBLK = ssdt+0xdc; // one byte
- TOM1 = ssdt+0xe3; //
- SBDN = ssdt+0xed;//
- HCLK = ssdt+0xfa; //+5 will be next HCLK
- HCDN = ssdt+0x12a; //+5 will be next HCDN
-
-
- dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-
- for(i=0;i<4;i++) {
- dword = pci_read_config32(dev, 0xe0+i*4);
- int_to_stream(dword, BUSN+i*5);
- }
-
- for(i=0;i<0x10;i++) {
- dword = pci_read_config32(dev, 0x80+i*4);
- int_to_stream(dword, MMIO+i*5);
- }
-
- for(i=0;i<0x08;i++) {
- dword = pci_read_config32(dev, 0xc0+i*4);
- int_to_stream(dword, PCIO+i*5);
- }
-
- *SBLK = (uint8_t)(sblk);
-
- msr = rdmsr(TOP_MEM);
- int_to_stream(msr.lo, TOM1);
-
- for(i=0;i<hc_possible_num;i++) {
- int_to_stream(pci1234[i], HCLK + i*5);
- int_to_stream(hcdn[i], HCDN + i*5);
- }
- for(i=hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
- int_to_stream(0x00000000, HCLK + i*5);
- int_to_stream(0x20202020, HCDN + i*5);
- }
-
- int_to_stream(sbdn, SBDN);
-
-}
-//end
+extern void update_ssdt(void *ssdt);
unsigned long write_acpi_tables(unsigned long start)
{
//same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table
- for(i=1;i<hc_possible_num;i++) { // 0: is hc sblink
- if((pci1234[i] & 1) != 1 ) continue;
+ for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
+ if((sysconf.pci1234[i] & 1) != 1 ) continue;
printk_debug("ACPI: * SSDT for PCI%d\n", i+1); //pci0 and pci1 are in dsdt
ssdtx = (acpi_header_t *)current;
current += ((acpi_header_t *)AmlCode_ssdtx[i])->length;
#endif
//use by raminit
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
//#define K8_SCAN_PCI_BUS 1
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
+
+#if USE_FAILOVER_IMAGE==0
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+ #if CONFIG_USE_PRINTK_IN_CAR == 1
+ #include "lib/uart8250.c"
+ #include "console/vtxprintf.c"
+ #include "arch/i386/lib/printk_init.c"
+ #endif
+#endif
+
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-#if USE_FALLBACK_IMAGE == 1
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
fallback_image:
// post_code(0x25);
+#if HAVE_FAILOVER_BOOT==1
+ __asm__ volatile ("jmp __fallback_image"
+ : /* outputs */
+ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+ )
+#endif
;
}
#endif
-
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
-#if USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
+#if HAVE_FAILOVER_BOOT==1
+ #if USE_FAILOVER_IMAGE==1
+ failover_process(bist, cpu_init_detectedx);
+ #else
+ real_main(bist, cpu_init_detectedx);
+ #endif
+#else
+ #if USE_FALLBACK_IMAGE == 1
+ failover_process(bist, cpu_init_detectedx);
+ #endif
+ real_main(bist, cpu_init_detectedx);
#endif
- real_main(bist, cpu_init_detectedx);
-
}
+#if USE_FAILOVER_IMAGE==0
+
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started();
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
+ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+ * So here need to make sure last core0 is started, esp for two way system,
+ * (there may be apic id conflicts in that case)
+ */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
-
+
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
post_cache_as_ram();
}
+
+#endif
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
+8 0 200Mhz
+8 1 166Mhz
+8 2 133Mhz
+8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
Name (PICM, Package (0x04)
{
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00}
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
})
Name (DNCG, Ones)
Name (PICM, Package (0x0C)
{
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
})
Method (_PRT, 0, NotSerialized)
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
- And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local0)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
Else { Return (0x0B) } //Enabled
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
- And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
- And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
}
Method (_CRS, 0, NotSerialized)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local3)
Store (0x00, Local4)
- And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
If (LNot (LEqual (Local1, 0x00)))
{ // Routing enable
If (LGreater (Local1, 0x07))
ShiftRight (Local0, 0x01, Local0)
}
- And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA)
- Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
}
}
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
- And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local0)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
- And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
- And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
}
Method (_CRS, 0, NotSerialized)
CreateByteField (BUFB, 0x02, IRB2)
Store (0x00, Local3)
Store (0x00, Local4)
- And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
ShiftRight (Local0, 0x01, Local0)
}
- And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
}
}
Name (_UID, 0x03)
Method (_STA, 0, NotSerialized)
{
- And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local0)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
- And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
{
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
- And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
}
Method (_CRS, 0, NotSerialized)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local3)
Store (0x00, Local4)
- And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
If (LGreater (Local1, 0x07))
ShiftRight (Local0, 0x01, Local0)
}
- And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC)
- Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
}
}
Name (_UID, 0x04)
Method (_STA, 0, NotSerialized)
{
- And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local0)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
If (LEqual (Local0, 0x00)) { Return (0x09) }
Else { Return (0x0B) }
}
Method (_DIS, 0, NotSerialized)
{
Store (0x01, Local3)
- And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
Store (Local1, Local2)
If (LGreater (Local1, 0x07))
ShiftLeft (Local3, Local1, Local3)
Not (Local3, Local3)
- And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
}
Method (_CRS, 0, NotSerialized)
CreateByteField (BUFB, 0x02, IRB2)
Store (0x00, Local3)
Store (0x00, Local4)
- And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNot (LEqual (Local1, 0x00)))
{
ShiftRight (Local0, 0x01, Local0)
}
- And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
}
}
})
Name (PICM, Package (0x14)
{
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
+ Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
})
Name (PICM, Package (0x04)
{
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
})
Name (PICM, Package (0x04)
{
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
})
Method (_PRT, 0, NotSerialized)
{
{
/* BUS0 root bus */
-/*
-//hardcode begin
- Name (BUSN, Package (0x04) { 0x04010003, 0x06050013, 0x00000000, 0x00000000 })
- Name (MMIO, Package (0x10) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00f43003, 0x00f44f01, 0x0000d003, 0x00efff01, 0x00f40003, 0x00f42f00, 0x00f45003, 0x00f44f00 })
- Name (PCIO, Package (0x08) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001003, 0x00001000, 0x00002003, 0x00002001 })
- Name (SBLK, 0x00)
- Name (TOM1, 0x40000000)
-
- // for AMD opteron we could have four chains, so we will have PCI1, PCI2, PCI3, PCI4
- // PCI1 must be SBLK Chain
- // If you have HT IO card that is connected to PCI2, PCI3, PCI4, then you man put Device in SSDT2, SSDT3, SSDT4,
- // in acpi_tables.c you can link those SSDT to RSDT according to it's presence.
- // Otherwise put the PCI2, PCI3, PCI4 in this dsdt
- Name (HCLK, Package (0x04) { 0x00000001, 0x00000011, 0x00000000, 0x00000000 }) //[0,3]=1 enable [4,7]=node_id, [8,15]=linkn
-
- Name (SBDN, 3) // 8111 UnitID Base
-//hardcode end
-*/
External (BUSN)
External (MMIO)
External (PCIO)
External (HCLK)
External (SBDN)
External (HCDN)
+ External (CBST)
+
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00180000)
Name (_UID, 0x01)
- Name (_BBN, 0)
-
- // define L1IC Link1 on node0 init completed, so node1 is installed
- // We must make sure our bus is 0 ?
- OperationRegion (LDT1, PCI_Config, 0xA4, 0x01)
- Field (LDT1, ByteAcc, Lock, Preserve)
- {
- , 5,
- L1IC, 1
- }
+ Name (HCIN, 0x00) // HC1
- }
-
- Device (PCI1)
- {
-
- Name (HCIN, 0x00) // HC1
- // BUS 1 first HT Chain
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000) // Fake
- Name (_UID, 0x02)
Method (_BBN, 0, NotSerialized)
{
- Return (GBUS (0x00, \_SB.PCI0.SBLK))
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_CRS, 0, NotSerialized)
Return (Local3)
}
- Include ("pci1_hc.asl")
+ Include ("pci0_hc.asl")
}
-/*
- Device (PCI2)
+ Device (PCI1)
{
-
- // BUS ? Second HT Chain
- Name (HCIN, 0x01) // HC2
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00180000))
- }
- Name (_UID, 0x03)
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
+ Name (_HID, "PNP0A03")
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
- Return (\_SB.GHCE(HCIN))
+ Return (\_SB.PCI0.CBST)
}
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci2_hc.asl")
+ Name (_BBN, 0x00)
}
-*/
+
}
{
Method (_L08, 0, NotSerialized)
{
- Notify (\_SB.PCI1, 0x02) //PME# Wakeup
+ Notify (\_SB.PCI0, 0x02) //PME# Wakeup
}
Method (_L0F, 0, NotSerialized)
{
- Notify (\_SB.PCI1.TP2P.USB0, 0x02) //USB Wakeup
+ Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
}
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
{
- Notify (\_SB.PCI1.PG0B, 0x02)
+ Notify (\_SB.PCI0.PG0B, 0x02)
}
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
{
- Notify (\_SB.PCI1.PG0A, 0x02)
+ Notify (\_SB.PCI0.PG0A, 0x02)
}
}
External (PICF)
- External (\_SB.PCI1.LNKA, DeviceObj)
- External (\_SB.PCI1.LNKB, DeviceObj)
- External (\_SB.PCI1.LNKC, DeviceObj)
- External (\_SB.PCI1.LNKD, DeviceObj)
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
Device (PCI2)
{
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
- })
-
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
-
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) {
- Return (PICM)
- }
- Else {
- Return (APIC)
- }
- }
-
- Device (SBC3)
- {
- /* acpi smbus it should be 0x00040003 if 8131 present */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
- Field (PIRQ, ByteAcc, Lock, Preserve)
- {
- PIBA, 8,
- PIDC, 8
- }
-/*
- OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
- Field (TS3_, DWordAcc, NoLock, Preserve)
- {
- PTS3, 16
- }
-*/
- }
-
- Device (HPET)
- {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
- }
-
- Include ("amd8111_pic.asl")
-
- Include ("amd8111_isa.asl")
-
- Device (TP2P)
- {
- /* 8111 P2P and it should 0x00030000 when 8131 present*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
- Else { Return (Package (0x02) { 0x08, 0x01 }) }
- }
-
- Device (USB0)
- {
- Name (_ADR, 0x00000000)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Device (USB1)
- {
- Name (_ADR, 0x00000001)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Name (APIC, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
-
- Name (PICM, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 4
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 3
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 isa
-
- Device (ISA)
- {
- /* lpc 0x00040000 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
-
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve)
- {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP, 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
-
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
-
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
-
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
-
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
- })
- }
-
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
-
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (SYR1, ResourceTemplate ()
- {
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- })
- Method (_CRS, 0, NotSerialized)
- {
- Return (SYR1)
- }
- }
-
- Device (MEM)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- })
- // Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQNoFlags () {12}
- })
- Method (_STA, 0, NotSerialized)
- {
- And (FLG0, 0x04, Local0)
- If (LEqual (Local0, 0x04)) { Return (0x0F) }
- Else { Return (0x00) }
- }
- }
-
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- }
- Include ("superio.asl")
-
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 pic LNKA B C D
-
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- { // Routing enable
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x14)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot A - PIRQ BCDA
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
-
- //Cypress Slot B - PIRQ CDAB
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
-
- //Cypress Slot C - PIRQ DABC
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
-
- //Cypress Slot D - PIRQ ABCD
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
- })
- Name (PICM, Package (0x14)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-// AMD8151
- Device (AGPB)
- {
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
-//AMD k8 util for BUSB and res range
-
- Scope (\_SB)
- {
-
- Name (OSTB, Ones)
- Method (OSTP, 0, NotSerialized)
- {
- If (LEqual (^OSTB, Ones))
- {
- Store (0x00, ^OSTB)
- }
-
- Return (^OSTB)
- }
-
- Method (SEQL, 2, Serialized)
- {
- Store (SizeOf (Arg0), Local0)
- Store (SizeOf (Arg1), Local1)
- If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
-
- Name (BUF0, Buffer (Local0) {})
- Store (Arg0, BUF0)
- Name (BUF1, Buffer (Local0) {})
- Store (Arg1, BUF1)
- Store (Zero, Local2)
- While (LLess (Local2, Local0))
- {
- Store (DerefOf (Index (BUF0, Local2)), Local3)
- Store (DerefOf (Index (BUF1, Local2)), Local4)
- If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
-
- Increment (Local2)
- }
-
- Return (One)
- }
-
-
- Method (DADD, 2, NotSerialized)
- {
- Store( Arg1, Local0)
- Store( Arg0, Local1)
- Add( ShiftLeft(Local1,16), Local0, Local0)
- Return (Local0)
- }
-
-
- Method (GHCE, 1, NotSerialized) // check if the HC enabled
- {
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
- Else { Return (0x00) }
- }
-
- Method (GHCN, 1, NotSerialized) // get the node num for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
- Return (Local0)
- }
-
- Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
- Return (Local0)
- }
-
- Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
- Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
- Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
- Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
- Return (Local0)
- }
-
- Method (GBUS, 2, NotSerialized)
- {
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (0x00)
- }
-
- Method (GWBN, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0000, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0000,,,)
- })
- CreateWordField (BUF0, 0x08, BMIN)
- CreateWordField (BUF0, 0x0A, BMAX)
- CreateWordField (BUF0, 0x0E, BLEN)
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
- Store (ShiftRight (Local1, 0x18), BMAX)
- Subtract (BMAX, BMIN, BLEN)
- Increment (BLEN)
- Return (RTAG (BUF0))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (RTAG (BUF0))
- }
-
- Method (GMEM, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , AddressRangeMemory, TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, MMIN)
- CreateDWordField (BUF0, 0x0E, MMAX)
- CreateDWordField (BUF0, 0x16, MLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x10))
- {
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, And (Local2, 0x07)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
- Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
- Or (MMAX, 0xFFFF, MMAX)
- Subtract (MMAX, MMIN, MLEN)
-
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
- {
- Store (\_SB.PCI0.TOM1, MMIN)
- Subtract (MMAX, MMIN, MLEN)
- Increment (MLEN)
- }
-
- Store (RTAG (BUF0), Local3)
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4))
- {
- Store (BUF0, Local3)
- }
-
- Return (Local3)
- }
-
- Method (GIOR, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, PMIN)
- CreateDWordField (BUF0, 0x0E, PMAX)
- CreateDWordField (BUF0, 0x16, PLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x08))
- {
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, And (Local2, 0x07)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- Store (And (Local1, 0x01FFF000), PMIN)
- Store (And (Local2, 0x01FFF000), PMAX)
- Or (PMAX, 0x0FFF, PMAX)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
-
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- If (LGreater (PMAX, PMIN))
- {
- If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
- {
- Store (0x0D00, PMIN)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
- }
-
- Store (RTAG (BUF0), Local3)
- Increment (Local4)
- }
-
- If (And (Local1, 0x10))
- {
- Store (0x03B0, PMIN)
- Store (0x03DF, PMAX)
- Store (0x30, PLEN)
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- Store (RTAG (BUF0), Local3)
- }
- }
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4))
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Return (Local3)
- }
-
- Method (RTAG, 1, NotSerialized)
- {
- Store (Arg0, Local0)
- Store (SizeOf (Local0), Local1)
- Subtract (Local1, 0x02, Local1)
- Multiply (Local1, 0x08, Local1)
- CreateField (Local0, 0x00, Local1, RETB)
- Store (RETB, Local2)
- Return (Local2)
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_PR)
- {
- Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
- Processor (CPU1, 0x01, 0x00000000, 0x00) {}
- Processor (CPU2, 0x02, 0x00000000, 0x00) {}
- Processor (CPU3, 0x03, 0x00000000, 0x00) {}
-
- }
-
- Method (FWSO, 0, NotSerialized) { }
-
- Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
- Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
- Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
- Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
-
- Scope (_SB)
- {
- Device (PCI0)
- {
- /* BUS0 root bus */
-
-/*
-//hardcode begin
- Name (BUSN, Package (0x04) { 0x04010003, 0x06050013, 0x00000000, 0x00000000 })
- Name (MMIO, Package (0x10) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00f43003, 0x00f44f01, 0x0000d003, 0x00efff01, 0x00f40003, 0x00f42f00, 0x00f45003, 0x00f44f00 })
- Name (PCIO, Package (0x08) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001003, 0x00001000, 0x00002003, 0x00002001 })
- Name (SBLK, 0x00)
- Name (TOM1, 0x40000000)
-
- // for AMD opteron we could have four chains, so we will have PCI1, PCI2, PCI3, PCI4
- // PCI1 must be SBLK Chain
- // If you have HT IO card that is connected to PCI2, PCI3, PCI4, then you man put Device in SSDT2, SSDT3, SSDT4,
- // in acpi_tables.c you can link those SSDT to RSDT according to it's presence.
- // Otherwise put the PCI2, PCI3, PCI4 in this dsdt
- Name (HCLK, Package (0x04) { 0x00000001, 0x00000011, 0x00000000, 0x00000000 }) //[0,3]=1 enable [4,7]=node_id, [8,15]=linkn
-
- Name (SBDN, 3) // 8111 UnitID Base
-//hardcode end
-*/
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_UID, 0x01)
- Name (_BBN, 0)
-
-
- // define L1IC Link1 on node0 init completed, so node1 is installed
- // We must make sure our bus is 0 ?
- OperationRegion (LDT1, PCI_Config, 0xA4, 0x01)
- Field (LDT1, ByteAcc, Lock, Preserve)
- {
- , 5,
- L1IC, 1
- }
-/*
-HT on Bus 0,So no PCI1
- }
-
- Device (PCI1)
- {
- // BUS 1 first HT Chain
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000) // Fake
- Name (_UID, 0x02)
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (0x00, \_SB.PCI0.SBLK))
- }
-
-*/
- Name (HCIN, 0x00) // HC1
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
-
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
-
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSTP ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci1_hc.asl")
-
- }
-/*
- Device (PCI2)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0x01) // HC2
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00180000))
- }
- Name (_UID, 0x03)
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci2_hc.asl")
- }
-*/
-
- }
-
- Scope (_GPE)
- {
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- }
-
- Method (_L0F, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- }
-
- Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
- {
- Notify (\_SB.PCI0.PG0B, 0x02)
- }
-
- Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
- {
- Notify (\_SB.PCI0.PG0A, 0x02)
- }
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG1)
- }
-/*
- Method (_WAK, 1, NotSerialized)
- {
- Or (Arg0, 0xE0, Local0)
- Store (Local0, DBG1)
- }
-*/
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
- {
- Store (Arg0, PICF)
- }
-
- OperationRegion (DEBG, SystemIO, 0x80, 0x01)
- Field (DEBG, ByteAcc, Lock, Preserve)
- {
- DBG1, 8
- }
-
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve)
- {
- AMEM, 32
- }
-
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve)
- {
- VGA1, 8
- }
-
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
-
- OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
- Field (GSTS, ByteAcc, NoLock, Preserve)
- {
- , 4,
- IRQR, 1
- }
-
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve)
- {
- Z008, 8
- }
-
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve)
- {
- Z00A, 8
- }
-
- Include ("amdk8_util.asl")
-
-}
-
+++ /dev/null
- Include ("amd8111.asl") //real SB at first
- Include ("amd8131.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCI2)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0x01) // HC2
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00180000))
- }
-
- Name (_UID, 0x03)
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci2_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8151.asl")
+++ /dev/null
-// Include ("w83627hf.asl")
#include <cpu/amd/dualcore.h>
#endif
+#include <cpu/amd/amdk8_sysconf.h>
+
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
unsigned char bus_isa = 7 ;
unsigned char bus_8132_0 = 1;
unsigned char bus_8132_1 = 2;
unsigned apicid_8132_1;
unsigned apicid_8132_2;
-unsigned sblk;
-unsigned pci1234[] =
+static unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
// 0x0000ff0,
// 0x0000ff0
};
-unsigned hc_possible_num;
-unsigned sbdn;
-unsigned hcdn[] =
+static unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
// 0x20202020,
// 0x20202020,
};
+
unsigned sbdn3;
unsigned sbdn5;
unsigned apicid_base;
device_t dev;
+ int i;
if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1;
- hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
+ sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ for(i=0;i<sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
get_sblk_pci1234();
- sbdn = (hcdn[0] >> 8) & 0xff;
- sbdn3 = hcdn[0] & 0xff;
- sbdn5 = hcdn[1] & 0xff;
+ sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
+ sbdn3 = sysconf.hcdn[0] & 0xff;
+ sbdn5 = sysconf.hcdn[1] & 0xff;
-// bus_8132_0 = node_link_to_bus(0, sblk);
- bus_8132_0 = (pci1234[0] >> 16) & 0xff;
+ bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
bus_8111_0 = bus_8132_0;
/* 8111 */
- dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
+ dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
#endif
}
else {
- printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8111_0, sysconf.sbdn);
}
/* 8132-1 */
dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3,0));
if (dev) {
bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk_debug("bus_isa=%d\n",bus_isa);
-#endif
}
else {
- printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8132_0);
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8132_0, sbdn3);
}
/* 8132-2 */
dev = dev_find_slot(bus_8132_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+// printk_debug("bus_isa=%d\n",bus_isa);
+#endif
}
else {
- printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8132_0);
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8132_0, sbdn3+1);
}
/* HT chain 1 */
- if((pci1234[1] & 0x1) == 1) {
- bus_8151_0 = (pci1234[1] >> 16) & 0xff;
+ if((sysconf.pci1234[1] & 0x1) == 1) {
+ bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8151 */
dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0));
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_8151_0, sbdn5+1);
+ }
}
/*I/O APICs: APIC ID Version State Address*/
#include <string.h>
#include <stdint.h>
#include <arch/pirq_routing.h>
+#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
extern unsigned char bus_8151_0;
extern unsigned char bus_8151_1;
-extern unsigned pci1234[];
-
-extern unsigned sbdn;
-extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdn5;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_8111_0;
- pirq->rtr_devfn = ((sbdn+1)<<3)|0;
+ pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
pirq->exclusive_irqs = 0;
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
//pci bridge
- write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//pcix bridge
// write_pirq_info(pirq_info, bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
- if(pci1234[1] & 0xf) {
+ if(sysconf.pci1234[1] & 0xf) {
//agp bridge
write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
}
#include <cpu/amd/dualcore.h>
#endif
+#include <cpu/amd/amdk8_sysconf.h>
+
extern unsigned char bus_isa;
extern unsigned char bus_8132_0;
extern unsigned char bus_8132_1;
extern unsigned apicid_8132_1;
extern unsigned apicid_8132_2;
-extern unsigned pci1234[];
-extern unsigned sbdn;
-extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdn5;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
//??? What
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
// Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
- if(pci1234[1] & 0xf) {
+ if(sysconf.pci1234[1] & 0xf) {
// Slot AGP
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x11);
}
#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
+#include "raminit.h"
+//struct definitions
+
+#if RAMINIT_SYSINFO==1
+struct link_pair_st {
+ device_t udev;
+ uint32_t upos;
+ uint32_t uoffs;
+ device_t dev;
+ uint32_t pos;
+ uint32_t offs;
+
+} __attribute__((packed));
+
+struct sys_info {
+ uint8_t ctrl_present[NODE_NUMS];
+ struct mem_controller ctrl[NODE_NUMS];
+
+ uint32_t nodes;
+ struct link_pair_st link_pair[16];// enough? only in_conherent
+ uint32_t link_pair_num;
+ uint32_t ht_c_num;
+ uint32_t sbdn;
+ uint32_t sblk;
+ uint32_t sbbusn;
+} __attribute__((packed));
+#endif
+
+
#endif
#endif /* AMDK8_H */
uint8_t ctrl_present[NODE_NUMS];
struct mem_info meminfo[NODE_NUMS];
struct mem_controller ctrl[NODE_NUMS];
- uint8_t mem_trained[NODE_NUMS];
+ uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
uint32_t tom_k;
uint32_t tom2_k;
uint32_t sbbusn;
} __attribute__((packed));
-#if MEM_TRAIN_SEQ == 1
+#ifdef __ROMCC__
+static void soft_reset(void);
+#endif
static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
{
+
int i;
uint32_t mask = 0;
+ unsigned needs_reset = 0;
+
if(sysinfo->nodes == 1) return; // in case only one cpu installed
for(i=1; i<sysinfo->nodes; i++) {
- if (!sysinfo->ctrl_present[ i ])
- continue;
-
/* Skip everything if I don't have any memory on this controller */
- if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if(sysinfo->mem_trained[i]==0x00) continue;
mask |= (1<<i);
i = 1;
while(1) {
if(mask & (1<<i)) {
- if((sysinfo->mem_trained[i])) {
+ if((sysinfo->mem_trained[i])!=0x80) {
mask &= ~(1<<i);
}
}
if(!mask) break;
+#if 0
/* cpu_relax */
__asm__ __volatile__("rep;nop": : :"memory");
+#endif
i++;
i%=sysinfo->nodes;
}
-}
+ for(i=0; i<sysinfo->nodes; i++) {
+#ifdef __ROMCC__
+ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
+#else
+ printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
#endif
+ switch(sysinfo->mem_trained[i]) {
+ case 0: //don't need train
+ case 1: //trained
+ break;
+ case 0x81: //recv1: fail
+ case 0x82: //Pos :fail
+ case 0x83: //recv2: fail
+ needs_reset = 1;
+ break;
+ }
+ }
+ if(needs_reset) {
+#ifdef __ROMCC__
+ print_debug("mem trained failed\r\n");
+ soft_reset();
+#else
+ printk_debug("mem trained failed\n");
+ hard_reset();
+#endif
+ }
+
+}
#endif /* AMDK8_F_H */
static inline void print_linkn (const char *strval, uint8_t byteval)
{
#if 1
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%02x\r\n", strval, byteval);
#else
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
freq_cap = pci_read_config16(dev, pos);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
-#if K8_REV_F_SUPPORT == 0
#if K8_HT_FREQ_1G_SUPPORT == 1
+ #if K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
+ #endif
{
return freq_cap;
}
-#endif
#endif
id = pci_read_config32(dev, 0);
nodes = setup_smp8();
#endif
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x nodes initialized.\r\n", nodes);
#else
print_debug_hex8(nodes);
*/
print_spew("coherent_ht_finalize\r\n");
-
#if K8_REV_F_SUPPORT == 0
rev_a0 = is_cpu_rev_a0();
#endif
-
for (node = 0; node < nodes; node++) {
device_t dev;
uint32_t val;
static inline void print_debug_addr(const char *str, void *val)
{
#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
- #if CONFIG_USE_INIT==1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("------Address debug: %s%x------\r\n", str, val);
#else
print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\r\n");
#if 1
static void print_debug_pci_dev(unsigned dev)
{
-#if CONFIG_USE_INIT
- printk_debug("PCI: %02x:%02x.%02x", (dev>>16) & 0xff, (dev>>11) & 0x1f, (dev>>8) & 0x7);
+#if CONFIG_USE_PRINTK_IN_CAR
+ printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
#else
print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
+ print_debug_hex8((dev >> 20) & 0xff);
print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
+ print_debug_hex8((dev >> 15) & 0x1f);
print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ print_debug_hex8((dev >> 12) & 7);
#endif
}
continue;
}
print_debug_pci_dev(dev);
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %04x:%04x\r\n", (id & 0xffff), (id>>16));
#else
print_debug(" ");
print_debug_hex32(id);
print_debug("\r\n");
#endif
- if(((dev>>8) & 0x07) == 0) {
+ if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
for(i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x:",i);
#else
print_debug("\r\n");
#endif
}
val = pci_read_config8(dev, i);
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %02x", val);
#else
print_debug_char(' ');
print_debug("\r\n");
}
+#if K8_REV_F_SUPPORT == 1
+static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
+static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
+{
+ int i;
+ print_debug_pci_dev(dev);
+ print_debug(" -- index_reg="); print_debug_hex32(index_reg);
+
+ for(i = 0; i < 0x40; i++) {
+ uint32_t val;
+ int j;
+#if CONFIG_USE_PRINTK_IN_CAR
+ printk_debug("\r\n%02x:",i);
+#else
+ print_debug("\r\n");
+ print_debug_hex8(i);
+ print_debug_char(':');
+#endif
+ val = pci_read_config32_index_wait(dev, index_reg, i);
+ for(j=0;j<4;j++) {
+#if CONFIG_USE_PRINTK_IN_CAR
+ printk_debug(" %02x", val & 0xff);
+#else
+ print_debug_char(' '); print_debug_hex8(val&0xff);
+#endif
+ val >>= 8;
+ }
+
+ }
+ print_debug("\r\n");
+}
+#endif
+
static void dump_pci_devices(void)
{
device_t dev;
}
dump_pci_device(dev);
- if(((dev>>8) & 0x07) == 0) {
+ if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
}
dump_pci_device(dev);
- if(((dev>>8) & 0x07) == 0) {
+ if(((dev>>12) & 0x07) == 0) {
uint8_t hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
if((hdr_type & 0x80) != 0x80) {
}
}
+#ifndef DEBUG_SMBUS
+#define DEBUG_SMBUS 0
+#endif
+
+#if DEBUG_SMBUS == 1
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
device = ctrl->channel0[i];
if (device) {
int j;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
break;
}
byte = status & 0xff;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
device = ctrl->channel1[i];
if (device) {
int j;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("dimm: %02x.1: %02x", i, device);
#else
print_debug("dimm: ");
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
break;
}
byte = status & 0xff;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("smbus: %02x", device);
#else
print_debug("smbus: ");
break;
}
if ((j & 0xf) == 0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%02x: ",j);
#else
print_debug("\r\n");
#endif
}
byte = status & 0xff;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug("\r\n");
}
}
+#endif
static void dump_io_resources(unsigned port)
{
int i;
udelay(2000);
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x:\r\n", port);
#else
print_debug_hex16(port);
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%02x:", i);
#else
print_debug_hex8(i);
#endif
}
val = inb(port);
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %02x",val);
#else
print_debug_char(' ');
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("\r\n%08x:", i);
#else
print_debug("\r\n");
print_debug(":");
#endif
}
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
dword &=0x0300;
dword |= 1;
sysconf.pci1234[0] = dword;
+ sysconf.hcid[0] = 0;
/*about hardcode numbering for HT_IO support
set the node_id and link_id that could have ht chain in the one array,
sysconf.pci1234[i] = 0;
sysconf.hcdn[i] = 0x20202020;
}
+ sysconf.hcid[i] = 0;
}
}
static inline void print_linkn_in (const char *strval, uint8_t byteval)
{
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%02x\r\n", strval, byteval);
#else
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
new_bus = bus;
#if 0
-#if CONFIG_USE_INIT == 1
+#if CONFIG_USE_PRINTK_IN_CAR
printk_debug("bus_num=%02x\r\n", bus);
#endif
#endif
class = pci_read_config16(dev, PCI_CLASS_DEVICE);
#if 0
-#if CONFIG_USE_INIT == 1
+#if CONFIG_USE_PRINTK_IN_CAR
if(hdr_type !=0xff ) {
printk_debug("dev=%02x fn=%02x hdr_type=%02x class=%04x\r\n",
(devfn>>3)& 0x1f, (devfn & 0x7), hdr_type, class);
2004.12 yhlu add D0 support
2005.02 yhlu add E0 memory hole support
*/
+#if K8_REV_F_SUPPORT == 1
+ #include "raminit_f.c"
+#else
#include <cpu/x86/mem.h>
#include <cpu/x86/cache.h>
unsigned where;
unsigned long reg;
#if 0
- #if CONFIG_USE_INIT
+ #if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_debug_hex32(register_values[i]);
return pci_read_config32(ctrl->f0, 0) == 0x11001022;
}
+#if RAMINIT_SYSINFO==1
+static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
+#else
static void sdram_set_registers(const struct mem_controller *ctrl)
+#endif
{
static const unsigned int register_values[] = {
unsigned where;
unsigned long reg;
#if 0
- #if CONFIG_USE_INIT
+ #if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_spew_hex32(register_values[i]);
return dimm_mask;
}
+#if RAMINIT_SYSINFO==1
+static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
+#else
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+#endif
{
struct spd_set_memclk_result result;
const struct mem_param *param;
#endif
#define TIMEOUT_LOOPS 300000
+#if RAMINIT_SYSINFO == 1
+static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
+#else
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+#endif
{
int i;
}
}
#endif
+
+#endif
static inline void print_raminit(const char *strval, uint32_t val)
{
-#if CONFIG_USE_INIT
- printk_debug("%s:%08x\r\n", strval, val);
+#if CONFIG_USE_PRINTK_IN_CAR
+ printk_debug("%s%08x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
#endif
for(i = 0; i < controllers; i++) {
sysinfo->mem_trained[i] = 0;
+
+ if (!sysinfo->ctrl_present[ i ])
+ continue;
+
+ /* Skip everything if I don't have any memory on this controller */
+ if(sysinfo->meminfo[i].dimm_mask==0x00)
+ continue;
+
+ sysinfo->mem_trained[i] = 0x80; // mem need to be trained
}
+#if 0
+ dump_pci_devices();
+ dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
+#endif
+
#if MEM_TRAIN_SEQ == 0
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
dqs_timing(controllers, ctrl, tsc0, sysinfo);
#endif
for(i = 0; i < controllers; i++) {
- if (!sysinfo->ctrl_present[ i ])
- continue;
-
/* Skip everything if I don't have any memory on this controller */
- if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if(sysinfo->mem_trained[i]!=0x80)
+ continue;
- dqs_timing(i, ctrl, sysinfo, 1);
+ dqs_timing(i, &ctrl[i], sysinfo, 1);
#if MEM_TRAIN_SEQ == 1
break; // only train the first node with ram
#endif
+#if MEM_TRAIN_SEQ != 1
+ wait_all_core0_mem_trained(sysinfo);
+#endif
+
+#if 0
+ dump_pci_devices();
+ dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
+#endif
}
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- #if CONFIG_USE_INIT == 1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%x\r\n", str, val);
#else
print_debug(str); print_debug_hex32(val); print_debug("\r\n");
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- #if CONFIG_USE_INIT == 1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2);
#else
print_debug(str); print_debug_hex32(val); print_debug(str2); print_debug_hex32(val2); print_debug("\r\n");
{
#if DQS_TRAIN_DEBUG > 0
if(DQS_TRAIN_DEBUG > level) {
- #if CONFIG_USE_INIT == 1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
#else
print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
{
- #if CONFIG_USE_INIT == 1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
#else
print_debug(str); print_debug("["); print_debug_hex8(i); print_debug("]="); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1
#endif
-static void TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
+static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
{
const static uint32_t TestPattern0[] = {
#if MEM_TRAIN_SEQ != 1
/* We need tidy output for type 1 */
- #if CONFIG_USE_INIT == 1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug(" CTLRMaxDelay=%02x", CTLRMaxDelay);
#else
print_debug(" CTLRMaxDelay="); print_debug_hex8(CTLRMaxDelay);
#endif
#endif
- if(CTLRMaxDelay==0xae) {
- soft_reset(); // try more or downgrade?
- }
+ return (CTLRMaxDelay==0xae)?1:0;
}
}
}
-static void train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
+static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
{
print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
- TrainRcvrEn(ctrl, Pass, sysinfo);
+ if(TrainRcvrEn(ctrl, Pass, sysinfo)) {
+ return 1;
+ }
print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
+ return 0;
}
-static void train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
+static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
{
print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
print_err("\r\nDQS Training Rd Wr failed ctrl"); print_err_hex8(ctrl->node_id); print_err("\r\n");
- soft_reset();
+ return 1;
}
else {
SetEccDQSRdWrPos(ctrl, sysinfo);
}
print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
+ return 0;
}
}
sizek = 1 << align;
#if MEM_TRAIN_SEQ != 1
- #if CONFIG_USE_INIT == 1
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
reg, range_startk >>10, sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"UC":
print_debug("DQS Training:RcvrEn:Pass1: ");
print_debug_hex8(i);
- train_DqsRcvrEn(ctrl+i, 1, sysinfo);
+ if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
print_debug(" done\r\n");
}
print_debug("DQS Training:DQSPos: ");
print_debug_hex8(i);
- train_DqsPos(ctrl+i, sysinfo);
+ if(train_DqsPos(ctrl+i, sysinfo)) goto out;
print_debug(" done\r\n");
}
print_debug("DQS Training:RcvrEn:Pass2: ");
print_debug_hex8(i);
- train_DqsRcvrEn(ctrl+i, 2, sysinfo);
+ if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
print_debug(" done\r\n");
sysinfo->mem_trained[i]=1;
}
+out:
tsc[4] = rdtsc();
clear_mtrr_dqs(sysinfo->tom2_k);
tsc_t tsc[4];
+ if(sysinfo->mem_trained[i] != 0x80) return;
#if MEM_TRAIN_SEQ == 1
- if(sysinfo->mem_trained[i]) return;
//need to enable mtrr, so dqs training could access the test address
setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
#endif
- fill_mem_cs_sysinfo(i, ctrl+i, sysinfo);
+ fill_mem_cs_sysinfo(i, ctrl, sysinfo);
if(v) {
tsc[0] = rdtsc();
print_debug("set DQS timing:RcvrEn:Pass1: ");
print_debug_hex8(i);
}
- train_DqsRcvrEn(ctrl+i, 1, sysinfo);
+ if(train_DqsRcvrEn(ctrl, 1, sysinfo)) {
+ sysinfo->mem_trained[i]=0x81; //
+ goto out;
+ }
if(v) {
print_debug(" done\r\n");
print_debug_hex8(i);
}
- train_DqsPos(ctrl+i, sysinfo);
+ if(train_DqsPos(ctrl, sysinfo)) {
+ sysinfo->mem_trained[i]=0x82; //
+ goto out;
+ }
if(v) {
print_debug(" done\r\n");
print_debug("set DQS timing:RcvrEn:Pass2: ");
print_debug_hex8(i);
}
- train_DqsRcvrEn(ctrl+i, 2, sysinfo);
+ if(train_DqsRcvrEn(ctrl, 2, sysinfo)){
+ sysinfo->mem_trained[i]=0x83; //
+ goto out;
+ }
if(v) {
print_debug(" done\r\n");
tsc[3] = rdtsc();
}
+out:
#if MEM_TRAIN_SEQ == 1
clear_mtrr_dqs(sysinfo->tom2_k);
#endif
print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo);
}
}
-
- sysinfo->mem_trained[i]=1;
+
+ if(sysinfo->mem_trained[i] == 0x80) {
+ sysinfo->mem_trained[i]=1;
+ }
}
#endif
#if MEM_TRAIN_SEQ == 1
static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox)
{
- dqs_timing(nodeid, sysinfo->ctrl,sysinfo, 0); // keep the output tidy
+ dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy
// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8);
// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9);
sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
wait_till_sysinfo_in_ram(); // use pci to get it
- if(sysinfox->mem_trained[nodeid] == 0) {
- if (sysinfox->ctrl_present[ nodeid ] && sysinfox->meminfo[nodeid].dimm_mask) {
- sysinfo->tom_k = sysinfox->tom_k;
- sysinfo->tom2_k = sysinfox->tom2_k;
- sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128;
- set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
- #if CONFIG_AP_CODE_IN_CAR == 0
- print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n");
- train_ram(nodeid, sysinfo, sysinfox);
- #else
- /* Can copy dqs_timing to ap cache and run from cache?
- * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ?
- */
- copy_and_run_ap_code_in_car(retcall);
- // will go back by jump
- #endif
- }
+ if(sysinfox->mem_trained[nodeid] == 0x80) {
+ sysinfo->tom_k = sysinfox->tom_k;
+ sysinfo->tom2_k = sysinfox->tom2_k;
+ sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128;
+ sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
+ memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
+ set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
+ #if CONFIG_AP_CODE_IN_CAR == 0
+ print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n");
+ train_ram(nodeid, sysinfo, sysinfox);
+ #else
+ /* Can copy dqs_timing to ap cache and run from cache?
+ * we need linuxbios_ap_car.rom? and treat it as linuxbios_ram.rom for ap ?
+ */
+ copy_and_run_ap_code_in_car(retcall);
+ // will go back by jump
+ #endif
}
}
#endif
unsigned where;
unsigned long reg;
#if 0
- #if CONFIG_USE_INIT
+ #if CONFIG_USE_PRINTK_IN_CAR
prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]);
#else
print_debug_hex32(register_values[i] + offset_pci_dev);
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
- #if CONFIG_USE_INIT
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i>>2, register_values[i],
register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
- #if CONFIG_USE_INIT
+ #if CONFIG_USE_PRINTK_IN_CAR
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#else
#include <arch/io.h>
#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFF) << 16) | \
- (((DEV) & 0x1f) << 11) | \
- (((FN) & 0x7) << 8))
+ (((BUS) & 0xFFF) << 20) | \
+ (((DEV) & 0x1F) << 15) | \
+ (((FN) & 0x7) << 12))
typedef unsigned device_t;
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
{
unsigned addr;
- addr = dev | where;
+ addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
}
static unsigned pci_read_config32(device_t dev, unsigned where)
{
unsigned addr;
- addr = dev | where;
+ addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}
projects / coreboot.git / commitdiff