project is now uncertain, and I can't invest the remaining time
needed to get it done.
Status is that memory is still not quite configured correctly. It is close
but here are DRAM Row Boundary registers.
Here is coreboot
60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00
This is close. But:
60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00
is the real hardware. So we are somehow missing those last slots. I think it's
because the SPD connections and the chip connections differ, some dumping
of RAM registers differ. But it's very close.
This is under serialice. Once we get to this point we get stuck here:
Copying coreboot to RAM.
Copying coreboot to RAM.
Copying coreboot to RAM.
Forever.
Here is the total config for 0:0.0 from coreboot:
PCI: 00:00.00
00: 86 80 90 35 06 00 90 00 0c 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00
50: 0c 60 2a 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00
70: 0a 0a 00 00 00 00 00 00 67 11 5e 55 1e 02 20 2c
80: 41 28 21 00 00 00 00 00 80 01 00 f0 00 00 00 00
90: 00 00 00 00 00 a1 04 39 aa aa 0c 30 5f 08 02 07
a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
b0: 32 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 44 c0 50 11 00 c0 ff 03 00 00 df 03 20 00 00 e0
d0: 02 28 00 0e 07 00 00 00 00 00 93 b5 00 00 00 00
e0: 00 00 00 00 00 00 00 00 36 3c 00 00 00 00 00 00
f0: 00 00 00 00 3a 01 42 00 80 0f 0c 00 00 00 00 00
And from factory:
00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09)
00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00
50: 0c 20 6a 00 00 00 00 00 00 10 11 11 01 00 00 10
60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00
70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c
80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00
90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07
a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00
c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0
d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00
e0: 00 00 00 00 00 00 00 00 3a 3c 00 00 00 00 00 00
f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00
I want to commit this because even if I get no further, someone else might.
Note that for serialice you need the following temporary patch as well:
Index: src/superio/nsc/pc8374/pc8374_early_init.c
===================================================================
--- src/superio/nsc/pc8374/pc8374_early_init.c (revision 4791)
+++ src/superio/nsc/pc8374/pc8374_early_init.c (working copy)
@@ -29,7 +29,8 @@
static void pc8374_enable_dev(device_t dev, unsigned iobase)
{
pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
+/* don't disable for now, it kills serialice */
+ pnp_set_enable(dev, 1);
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4796
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
default 0x016c
depends on BOARD_DELL_S1850
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1028
+ depends on BOARD_DELL_S1850
+
+
config MAX_CPUS
int
default 2
return smbus_read_byte(device, address);
}
+/* this is very highly mainboard dependent, related to wiring */
+/* from factory BIOS via lspci */
+#define DIMM_MAP_LOGICAL 0x2841
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ /* the wiring on this part is really messed up */
+ /* this is my best guess so far */
.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
}
#if 1
enable_smbus();
#endif
-#if 1
+#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
dump_spd_registers();
}
+#endif
+#if 1
+ show_dram_slots();
#endif
disable_watchdogs();
// dump_ipmi_registers();
mainboard_set_e7520_leds();
// memreset_setup();
+
sdram_initialize(ARRAY_SIZE(mch), mch);
-#if 1
+#if 0
dump_pci_devices();
#endif
#if 1
dump_pci_device(PCI_DEV(0, 0x00, 0));
- dump_bar14(PCI_DEV(0, 0x00, 0));
+// dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
#if 1 // temporarily disabled
}
}
-#if 0
-static void dump_spd_registers(const struct mem_controller *ctrl)
-{
- int i;
- print_debug("\r\n");
- for(i = 0; i < 4; i++) {
- unsigned device;
- device = ctrl->channel0[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\r\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\r\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\r\n");
- }
- device = ctrl->channel1[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\r\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = smbus_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\r\n");
- break;
- }
- byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
- }
- print_debug("\r\n");
- }
- }
-}
-#endif
-
void dump_spd_registers(void)
{
unsigned device;
}
}
+void show_dram_slots(void)
+{
+ unsigned device;
+ device = SMBUS_MEM_DEVICE_START;
+ while(device <= SMBUS_MEM_DEVICE_END) {
+ int status = 0;
+ int i;
+ print_debug("\r\n");
+ print_debug("dimm ");
+ print_debug_hex8(device);
+
+ status = smbus_read_byte(device, 0);
+ if (status < 0) {
+ print_debug("bad device: ");
+ } else {
+ print_debug("present: ");
+ }
+ print_debug_hex8(status);
+ print_debug("\r\n");
+ device += SMBUS_MEM_DEVICE_INC;
+ print_debug("\n");
+ }
+}
+
void dump_ipmi_registers(void)
{
unsigned device;
projects / coreboot.git / commitdiff