fixup

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index 74a36eb3ab040d28d10a3f8f141112376d988d24..1a1c66c5a022455d47e1877a7d30b82716d174fa 100644 (file)
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -14,12 +14,6 @@ uses CONFIG_BRIQ_7400
 default PCIC0_CFGADDR=0xff508000
 default PCIC0_CFGDATA=0xff508010
 
-##
-## Set IDE control registers
-##
-default PNP_CFGADDR=0x1f0
-default PNP_CFGDATA=0x1f1
-
 ##
 ## Set UART base address
 ##
@@ -28,8 +22,13 @@ default TTYS0_BASE=0x3f8
 ##
 ## Early board initialization, called from ppc_main()
 ##
-initobject init.c
-driver pci_bridge.c
+initobject init.o
+initobject clock.o
+
+##
+## Stage 2 timer support
+##
+object clock.o
 
 arch ppc end
 
@@ -43,6 +42,7 @@ end
 ##
 ## Include the secondary Configuration files 
 ##
+northbridge ibm/cpc710 end
 southbridge winbond/w83c553 end
 
 ##