Rename E7520 to e7520, and E7525 to e7525 in the code. The next commit

will then rename the E7520 and E7525 directories respectively.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb
index 50ab93c83ad973015e67f6c461e9a9092df76330..0640f389aba2843155dd9da93a2dc25bbb22228c 100644 (file)
--- a/src/mainboard/dell/s1850/Config.lb
+++ b/src/mainboard/dell/s1850/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520 # mch
+chip northbridge/intel/e7520 # mch
        device pci_domain 0 on 
                chip southbridge/intel/i82801er # i82801er
                        # USB ports

diff --git a/src/mainboard/dell/s1850/auto.c b/src/mainboard/dell/s1850/auto.c
index 406181342f024f1dee3378586bdbcf356fb043a2..78406138cba25a3efd455aa7a7efc21224712453 100644 (file)
--- a/src/mainboard/dell/s1850/auto.c
+++ b/src/mainboard/dell/s1850/auto.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "s2850_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 

diff --git a/src/mainboard/dell/s1850/failover.c b/src/mainboard/dell/s1850/failover.c
index 5029d986117bc02d8a2fd7235f9170af52ad9e1c..c5f3f8089dbd00188da351517db96655424c3a22 100644 (file)
--- a/src/mainboard/dell/s1850/failover.c
+++ b/src/mainboard/dell/s1850/failover.c
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {

diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
index c355640cc1716a92bec4ba4d34a3f3532fc97182..69795b00267ad10963cd1322e650e8498f2d89c2 100644 (file)
--- a/src/mainboard/intel/jarrell/Config.lb
+++ b/src/mainboard/intel/jarrell/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520
+chip northbridge/intel/e7520
        device pci_domain 0 on 
                device pci 00.0 on end
                device pci 00.1 on end

diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c
index f10274663672509d7ff5ce30dfd5ab76af79841b..d5e68e234334c5d04d8c0e0e0a262c1fcef53103 100644 (file)
--- a/src/mainboard/intel/jarrell/auto.c
+++ b/src/mainboard/intel/jarrell/auto.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "power_reset_check.c"
 #include "jarrell_fixups.c"
 #include "superio/nsc/pc87427/pc87427_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 #define SIO_GPIO_BASE 0x680
@@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 #include "debug.c"
 

diff --git a/src/mainboard/intel/jarrell/failover.c b/src/mainboard/intel/jarrell/failover.c
index 5029d986117bc02d8a2fd7235f9170af52ad9e1c..c5f3f8089dbd00188da351517db96655424c3a22 100644 (file)
--- a/src/mainboard/intel/jarrell/failover.c
+++ b/src/mainboard/intel/jarrell/failover.c
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {

diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb
index 8d4ada557b362be9d85f2cb067fd42e96b85ad33..a246f16e5cc3a4464706d604f4146dc6624afcb8 100644 (file)
--- a/src/mainboard/supermicro/x6dai_g/Config.lb
+++ b/src/mainboard/supermicro/x6dai_g/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7525 # mch
+chip northbridge/intel/e7525 # mch
        device pci_domain 0 on
                chip southbridge/intel/esb6300  # esb6300 
                        register "pirq_a_d" = "0x0b0a0a05"

diff --git a/src/mainboard/supermicro/x6dai_g/auto.c b/src/mainboard/supermicro/x6dai_g/auto.c
index f148a8c38b88a9e936eaa3a031e8e0feacd16102..9c5fce59a3e5728bb497917d3a2e77beefd1e8c2 100644 (file)
--- a/src/mainboard/supermicro/x6dai_g/auto.c
+++ b/src/mainboard/supermicro/x6dai_g/auto.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
-#include "northbridge/intel/E7525/raminit.h"
+#include "northbridge/intel/e7525/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -19,7 +19,7 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7525/memory_initialized.c"
+#include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -50,7 +50,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7525/raminit.c"
+#include "northbridge/intel/e7525/raminit.c"
 #include "sdram/generic_sdram.c"
 
 

diff --git a/src/mainboard/supermicro/x6dai_g/failover.c b/src/mainboard/supermicro/x6dai_g/failover.c
index 1a4a88ebfab6da1adcf2034b81cccda885996eb1..29b7eeda5f7444270f810fbe172ec6d9a575ad10 100644 (file)
--- a/src/mainboard/supermicro/x6dai_g/failover.c
+++ b/src/mainboard/supermicro/x6dai_g/failover.c
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7525/memory_initialized.c"
+#include "northbridge/intel/e7525/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {

diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb
index 672da8233c2efd549bb64472d69d6ab32d253ec0..60be506e287c68306e400b6b81e6705e6234a045 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520  # MCH
+chip northbridge/intel/e7520  # MCH
        chip drivers/generic/debug  # DEBUGGING
                device pnp 00.0 on end
                device pnp 00.1 off end

diff --git a/src/mainboard/supermicro/x6dhe_g/auto.c b/src/mainboard/supermicro/x6dhe_g/auto.c
index be5affc04cac261e6aff9d634764a9a52911b1a5..fd78ab43d3592c4fd58e62b1d185b1bb86fbf886 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g/auto.c
+++ b/src/mainboard/supermicro/x6dhe_g/auto.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhe_g_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 

diff --git a/src/mainboard/supermicro/x6dhe_g/failover.c b/src/mainboard/supermicro/x6dhe_g/failover.c
index 5029d986117bc02d8a2fd7235f9170af52ad9e1c..c5f3f8089dbd00188da351517db96655424c3a22 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g/failover.c
+++ b/src/mainboard/supermicro/x6dhe_g/failover.c
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {

diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb
index 92567883d2df87d6d343bbbffc1603511e61da26..37986b96057bb422dbbc70f80af2342700122701 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520  # MCH
+chip northbridge/intel/e7520  # MCH
        chip drivers/generic/debug  # DEBUGGING
                device pnp 00.0 off end
                device pnp 00.1 off end

diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.c b/src/mainboard/supermicro/x6dhe_g2/auto.c
index 854a74a132f027dd14e01a097a5e1ee3f77d097a..afd389c03efcd31d23cc24a44da4a939bc09f940 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/auto.c
+++ b/src/mainboard/supermicro/x6dhe_g2/auto.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhe_g2_fixups.c"
 #include "superio/nsc/pc87427/pc87427_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 

diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
index b4966a7f18b03537f1f5515601769931713e804e..934cdb4d283583d6bcfb7bfcde860d29ab58225a 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
+++ b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhe_g_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 

diff --git a/src/mainboard/supermicro/x6dhe_g2/failover.c b/src/mainboard/supermicro/x6dhe_g2/failover.c
index 5029d986117bc02d8a2fd7235f9170af52ad9e1c..c5f3f8089dbd00188da351517db96655424c3a22 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/failover.c
+++ b/src/mainboard/supermicro/x6dhe_g2/failover.c
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {

diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb
index 2fb4ac660254e2196745634ef7c3e64a7c0c4e7b..3b4826bdfcb2d4184592db97db25e7f8eb8ec862 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520 # mch
+chip northbridge/intel/e7520 # mch
        device pci_domain 0 on 
                chip southbridge/intel/i82801er # i82801er
                        # USB ports

diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c
index 6df3e66da028321c54b354eacbfe619a773010b1..41e85991ecc50d2331d2488b0d6065cc81bc6917 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig/auto.c
+++ b/src/mainboard/supermicro/x6dhr_ig/auto.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhr_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 

diff --git a/src/mainboard/supermicro/x6dhr_ig/failover.c b/src/mainboard/supermicro/x6dhr_ig/failover.c
index 5029d986117bc02d8a2fd7235f9170af52ad9e1c..c5f3f8089dbd00188da351517db96655424c3a22 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig/failover.c
+++ b/src/mainboard/supermicro/x6dhr_ig/failover.c
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {

diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
index bfc9c2180c5e83c41a66959921adda02490a7ac2..c3c6b9a8f91d0e3aede228b40b9dc4a6c8773d4e 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
@@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520 # mch
+chip northbridge/intel/e7520 # mch
        device pci_domain 0 on 
                chip southbridge/intel/i82801er # i82801er
                        # USB ports

diff --git a/src/mainboard/supermicro/x6dhr_ig2/auto.c b/src/mainboard/supermicro/x6dhr_ig2/auto.c
index 1998d34ab61b5bde0485bfc7e0f7f84b5234deab..70607d016bf5b683b3663f8a4739c1e52964cb59 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig2/auto.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/auto.c
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhr2_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 

diff --git a/src/mainboard/supermicro/x6dhr_ig2/failover.c b/src/mainboard/supermicro/x6dhr_ig2/failover.c
index 5029d986117bc02d8a2fd7235f9170af52ad9e1c..c5f3f8089dbd00188da351517db96655424c3a22 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig2/failover.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/failover.c
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {

diff --git a/src/northbridge/intel/E7520/chip.h b/src/northbridge/intel/E7520/chip.h
index e9ee0a2e1028cdb67f7afefc3cdb61c85e970568..b02b8b8ad780a5a10374d52ce6a507185c10e9a8 100644 (file)
--- a/src/northbridge/intel/E7520/chip.h
+++ b/src/northbridge/intel/E7520/chip.h
@@ -1,7 +1,7 @@
-struct northbridge_intel_E7520_config
+struct northbridge_intel_e7520_config
 {
         /* Interrupt line connect */
         unsigned int intrline;
 };
 
-extern struct chip_operations northbridge_intel_E7520_ops;
+extern struct chip_operations northbridge_intel_e7520_ops;

diff --git a/src/northbridge/intel/E7520/northbridge.c b/src/northbridge/intel/E7520/northbridge.c
index 44490861f802aef63da67fc1e1552707faf7d9bb..160c5a7d682e3cca08361978d8d18f89972b23a5 100644 (file)
--- a/src/northbridge/intel/E7520/northbridge.c
+++ b/src/northbridge/intel/E7520/northbridge.c
@@ -264,7 +264,7 @@ static void enable_dev(device_t dev)
        }
 }
 
-struct chip_operations northbridge_intel_E7520_ops = {
+struct chip_operations northbridge_intel_e7520_ops = {
        CHIP_NAME("Intel E7520 Northbridge")
        .enable_dev = enable_dev,
 };

diff --git a/src/northbridge/intel/E7520/pciexp_porta.c b/src/northbridge/intel/E7520/pciexp_porta.c
index 5443d66174dd9339f0533c92db1073ba7f00976f..a86917217a191d568ab5c955cc5fefbdd99e363a 100644 (file)
--- a/src/northbridge/intel/E7520/pciexp_porta.c
+++ b/src/northbridge/intel/E7520/pciexp_porta.c
@@ -8,7 +8,7 @@
 #include "chip.h"
 #include <part/hard_reset.h>
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {

diff --git a/src/northbridge/intel/E7520/pciexp_porta1.c b/src/northbridge/intel/E7520/pciexp_porta1.c
index b4dcb2fe152907fd9a7e96690419971d30f7690d..fd32919b193fe300837890386703237e13111757 100644 (file)
--- a/src/northbridge/intel/E7520/pciexp_porta1.c
+++ b/src/northbridge/intel/E7520/pciexp_porta1.c
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {

diff --git a/src/northbridge/intel/E7520/pciexp_portb.c b/src/northbridge/intel/E7520/pciexp_portb.c
index 7f1792521265b7ec4d648e08ed082b043c3fb29c..491a0751427c1b800e6e5dcc5376a52481daf1e5 100644 (file)
--- a/src/northbridge/intel/E7520/pciexp_portb.c
+++ b/src/northbridge/intel/E7520/pciexp_portb.c
@@ -8,7 +8,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {

diff --git a/src/northbridge/intel/E7520/pciexp_portc.c b/src/northbridge/intel/E7520/pciexp_portc.c
index c46610b06903ece0f88d08290434c0f4541606f3..82d876917d18990289834758b102dc0b4ff4846f 100644 (file)
--- a/src/northbridge/intel/E7520/pciexp_portc.c
+++ b/src/northbridge/intel/E7520/pciexp_portc.c
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {

diff --git a/src/northbridge/intel/E7525/chip.h b/src/northbridge/intel/E7525/chip.h
index 19d8c4e54c4c322868f00288454b253807d3ff84..7daadefefe59beb14c3382e3fb4f6be8bf7ea445 100644 (file)
--- a/src/northbridge/intel/E7525/chip.h
+++ b/src/northbridge/intel/E7525/chip.h
@@ -1,7 +1,7 @@
-struct northbridge_intel_E7525_config
+struct northbridge_intel_e7525_config
 {
         /* Interrupt line connect */
         unsigned int intrline;
 };
 
-extern struct chip_operations northbridge_intel_E7525_ops;
+extern struct chip_operations northbridge_intel_e7525_ops;

diff --git a/src/northbridge/intel/E7525/northbridge.c b/src/northbridge/intel/E7525/northbridge.c
index 71f17224dfb2c985b28dfa9dd17d56b0dce66814..2fa6678c0e11ec067300de257cd8923cacd2d0d7 100644 (file)
--- a/src/northbridge/intel/E7525/northbridge.c
+++ b/src/northbridge/intel/E7525/northbridge.c
@@ -264,7 +264,7 @@ static void enable_dev(device_t dev)
        }
 }
 
-struct chip_operations northbridge_intel_E7525_ops = {
+struct chip_operations northbridge_intel_e7525_ops = {
        CHIP_NAME("Intel E7525 Northbridge")
        .enable_dev = enable_dev,
 };

diff --git a/src/northbridge/intel/E7525/pciexp_porta.c b/src/northbridge/intel/E7525/pciexp_porta.c
index 093edec38f8134967f3383b1eb9471f44f708326..aea9ab0580b9420813e4f87058bc6f672c4d08fb 100644 (file)
--- a/src/northbridge/intel/E7525/pciexp_porta.c
+++ b/src/northbridge/intel/E7525/pciexp_porta.c
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {

diff --git a/src/northbridge/intel/E7525/pciexp_porta1.c b/src/northbridge/intel/E7525/pciexp_porta1.c
index 7118caa72f440801a6f25cf89445286b673e74ab..ac3c97c016fb2dd218149dff52f09452e8c31015 100644 (file)
--- a/src/northbridge/intel/E7525/pciexp_porta1.c
+++ b/src/northbridge/intel/E7525/pciexp_porta1.c
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {

diff --git a/src/northbridge/intel/E7525/pciexp_portb.c b/src/northbridge/intel/E7525/pciexp_portb.c
index f623a54416f38211f6d249362a37413bf9becbc0..e207c6c696a7724bfaf575a6c720b8f6826fd994 100644 (file)
--- a/src/northbridge/intel/E7525/pciexp_portb.c
+++ b/src/northbridge/intel/E7525/pciexp_portb.c
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {

diff --git a/src/northbridge/intel/E7525/pciexp_portc.c b/src/northbridge/intel/E7525/pciexp_portc.c
index 05e0b68863eb82364b8326555b8bee273f00a782..f211f3a4a2e244f2e90f9f9bb2a556bdc55f0f32 100644 (file)
--- a/src/northbridge/intel/E7525/pciexp_portc.c
+++ b/src/northbridge/intel/E7525/pciexp_portc.c
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {