#include "../../../northbridge/amd/amdk8/amdk8.h"
#include <cpu/amd/model_fxx_rev.h>
+#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
}
-extern void model_fxx_update_microcode(unsigned cpu_deviceid);
-
#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
#endif
#define CPU_AMD_MICORCODE_H
void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id);
+void model_fxx_update_microcode(unsigned cpu_deviceid);
#endif /* CPU_AMD_MICROCODE_H */
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
extern void update_ssdt(void *ssdt);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
u8 *PCI;
u8 *HCIN;
current += ((acpi_header_t *)AmlCode)->length;
memcpy((void *)dsdt,(void *)AmlCode, \
((acpi_header_t *)AmlCode)->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+ printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08;
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
acpi_header_t *ssdtx;
unsigned char *p;
- unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
-
int i;
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
current += ((acpi_header_t *)AmlCode)->length;
memcpy((void *)dsdt,(void *)AmlCode, \
((acpi_header_t *)AmlCode)->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+ printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FDAT */
printk_debug("ACPI: * FADT\n");
extern void update_ssdt(void *ssdt);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
u8 *PCI;
u8 *HCIN;
current += ((acpi_header_t *)AmlCode)->length;
memcpy((void *)dsdt,(void *)AmlCode, \
((acpi_header_t *)AmlCode)->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+ printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08;
((acpi_header_t *) AmlCode)->length);
dsdt->checksum = 0; /* Don't trust iasl to get this right. */
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
printk_debug("ACPI: * FADT\n");
((acpi_header_t *) AmlCode)->length);
dsdt->checksum = 0; /* Don't trust iasl to get this right. */
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
printk_debug("ACPI: * FADT\n");
((acpi_header_t *) AmlCode)->length);
dsdt->checksum = 0; /* Don't trust iasl to get this right. */
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
printk_debug("ACPI: * FADT\n");
int j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) {
- unsigned d;
+ unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
acpi_header_t *ssdtx;
unsigned char *p;
- unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
-
int i;
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
current += ((acpi_header_t *)AmlCode)->length;
memcpy((void *)dsdt,(void *)AmlCode, \
((acpi_header_t *)AmlCode)->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+ printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FDAT */
printk_debug("ACPI: * FADT\n");
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
- printk_info("Writing IRQ routing tables to 0x%x...", addr);
+ printk_info("Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);
extern void get_bus_conf(void);
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "IWILL ";
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
((acpi_header_t *) AmlCode)->length);
dsdt->checksum = 0; /* Don't trust iasl to get this right. */
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
printk_debug("ACPI: * FADT\n");
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
extern void get_bus_conf(void);
-void update_ssdtx(void *ssdtx, int i)
+static void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+ printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
((acpi_header_t *) AmlCode_dsdt)->length);
dsdt->checksum = 0; /* Don't trust iasl to get this right. */
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length);
dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+ printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
#endif
- printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
printk_debug("ACPI: * FADT\n");
static void acpi_init(struct device *dev)
{
uint8_t byte;
- uint16_t word;
uint16_t pm10_bar;
uint32_t dword;
int on;
#if 0
+ uint16_t word;
printk_debug("ACPI: disabling NMI watchdog.. ");
byte = pci_read_config8(dev, 0x49);
pci_write_config8(dev, 0x49, byte | (1<<2));
word = pci_read_config16(dev, 0x46);
pci_write_config16(dev, 0x46, word | (1<<9));
printk_debug("done.\n");
-
-
#endif
+
/* To enable the register 0xcf9 in the IO space
* bit [D5] is set in the amd8111 configuration register.
* The config. reg. is devBx41. Register 0xcf9 allows
/* Hard Reset PHY */
printk_debug("Reseting PHY... ");
if (conf->phy_lowreset) {
- write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
+ write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
} else {
- write32((void *)(mmio + CMD3), VAL0 | RESET_PHY);
+ write32((mmio + CMD3), VAL0 | RESET_PHY);
}
mdelay(15);
- write32((void *)(mmio + CMD3), RESET_PHY);
+ write32((mmio + CMD3), RESET_PHY);
printk_debug("Done\n");
}
return inb(port_base + 1);
}
+#if CONFIG_EXPERT
static void w83627hf_16_bit_addr_qual(device_t dev)
{
int port = dev->path.pnp.port >> 8;
outb(inb(port + 1) | 0x80, port + 1);
pnp_exit_ext_func_mode(dev);
}
+#endif
static void enable_hwm_smbus(device_t dev)
{