2008-12-05 Rodrigo Kumpera <rkumpera@novell.com>

	* simd-intrinsics.c: Add support for operator == and != to Vector8(u)s and Vector16(s)b.

svn path=/trunk/mono/; revision=120916

diff --git a/mono/mini/ChangeLog b/mono/mini/ChangeLog
index 4821bda7bc89a78fa2b858d4dea91c5f656f54d3..f0f9d3cd0027e671491828eb68879dfe5d5d35e2 100644 (file)
--- a/mono/mini/ChangeLog
+++ b/mono/mini/ChangeLog
@@ -74,6 +74,10 @@
        Removed FIRST/LAST_[GF]REG macros, to make merging PPC64 with PPC
        code easier.
 
+2008-12-05  Rodrigo Kumpera  <rkumpera@novell.com>
+
+       * simd-intrinsics.c: Add support for operator == and != to Vector8(u)s and Vector16(s)b.
+
 2008-12-05  Rodrigo Kumpera  <rkumpera@novell.com>
 
        * basic-simd.cs: Tests for operator == and != on Vector4f.

diff --git a/mono/mini/simd-intrinsics.c b/mono/mini/simd-intrinsics.c
index f84fbc2682d8bb51cbf26f50d5d1f7f0320d23a4..c81619d7cc4688417de834b2d0b7c87813b8bdb9 100644 (file)
--- a/mono/mini/simd-intrinsics.c
+++ b/mono/mini/simd-intrinsics.c
@@ -379,8 +379,10 @@ static const SimdIntrinsc vector8us_intrinsics[] = {
        { SN_op_Addition, OP_PADDW, SIMD_EMIT_BINARY },
        { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
        { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+       { SN_op_Equality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
        { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
        { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+       { SN_op_Inequality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
        { SN_op_LeftShift, OP_PSHLW, SIMD_EMIT_SHIFT },
        { SN_op_Multiply, OP_PMULW, SIMD_EMIT_BINARY },
        { SN_op_RightShift, OP_PSHRW, SIMD_EMIT_SHIFT },
@@ -428,8 +430,10 @@ static const SimdIntrinsc vector8s_intrinsics[] = {
        { SN_op_Addition, OP_PADDW, SIMD_EMIT_BINARY },
        { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
        { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+       { SN_op_Equality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
        { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
        { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+       { SN_op_Inequality, OP_PCMPEQW, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
        { SN_op_LeftShift, OP_PSHLW, SIMD_EMIT_SHIFT },
        { SN_op_Multiply, OP_PMULW, SIMD_EMIT_BINARY },
        { SN_op_RightShift, OP_PSARW, SIMD_EMIT_SHIFT },
@@ -481,8 +485,10 @@ static const SimdIntrinsc vector16b_intrinsics[] = {
        { SN_op_Addition, OP_PADDB, SIMD_EMIT_BINARY },
        { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
        { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+       { SN_op_Equality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
        { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
        { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+       { SN_op_Inequality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
        { SN_op_Subtraction, OP_PSUBB, SIMD_EMIT_BINARY },
        { SN_set_V0, 0, SIMD_EMIT_SETTER },
        { SN_set_V1, 1, SIMD_EMIT_SETTER },
@@ -542,8 +548,10 @@ static const SimdIntrinsc vector16sb_intrinsics[] = {
        { SN_op_Addition, OP_PADDB, SIMD_EMIT_BINARY },
        { SN_op_BitwiseAnd, OP_PAND, SIMD_EMIT_BINARY },
        { SN_op_BitwiseOr, OP_POR, SIMD_EMIT_BINARY },
+       { SN_op_Equality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_EQ },
        { SN_op_ExclusiveOr, OP_PXOR, SIMD_EMIT_BINARY },
        { SN_op_Explicit, 0, SIMD_EMIT_CAST },
+       { SN_op_Inequality, OP_PCMPEQB, SIMD_EMIT_EQUALITY, SIMD_VERSION_SSE1, SIMD_COMP_NEQ },
        { SN_op_Subtraction, OP_PSUBB, SIMD_EMIT_BINARY },
        { SN_set_V0, 0, SIMD_EMIT_SETTER },
        { SN_set_V1, 1, SIMD_EMIT_SETTER },