pci 0:18.2
pci 0:18.3
southbridge amd/amd8111 "amd8111" link 2
- pci 0:0.0 on
+ pci 0:0.0
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:19.1
pci 0:19.2
pci 0:19.3
- southbridge amd/amd8131 "amd8131" link 1
+ southbridge amd/amd8131 "amd8131_0" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
- southbridge amd/amd8131 "amd8131" link 1
+ southbridge amd/amd8131 "amd8131_1" link 1
pci 0:0.0
pci 0:0.1
pci 0:1.0
#define ASSEMBLY 1
-#define MAXIMUM_CONSOLE_LOGLEVEL 9
-#define DEFAULT_CONSOLE_LOGLEVEL 9
+// #define MAXIMUM_CONSOLE_LOGLEVEL 9
+// #define DEFAULT_CONSOLE_LOGLEVEL 9
#include <stdint.h>
#include <device/pci_def.h>
return ret;
}
-static inline int spd_read_byte(unsigned device, unsigned address)
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x30
- unsigned hub = device >> 8;
-
- device &= 0xff;
- smbus_write_byte(SMBUS_HUB, 0x01, 1<<hub);
- smbus_write_byte(SMBUS_HUB, 0x03, 0);
+ unsigned device=(ctrl->channel0[0])>>8;
+ smbus_write_byte(SMBUS_HUB | (0x01<<8), device);
+ smbus_write_byte(SMBUS_HUB | (0x03<<8), 0);
+}
- return smbus_read_byte(device, address);
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device & 0xff, address);
}
/* no specific code here. this should go away completely */
pnp_set_iobase0(SIO_BASE, 0x3f8);
}
-#define RC0 (0<<8)
-#define RC1 (1<<8)
-#define RC2 (2<<8)
-#define RC3 (3<<8)
+#define RC0 ((1<<0)<<8)
+#define RC1 ((1<<1)<<8)
+#define RC2 ((1<<2)<<8)
+#define RC3 ((1<<3)<<8)
#define DIMM0 0xa0
#define DIMM1 0xa2