Handle RS690 quirks for 1 GHz noncoherent HyperTransport.

The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.

Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.

Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
index b691223b6da46c39acf8984a0b0df3f58eed6dae..6c8d9e3542b7c5427515c3548ba3ac6e11adb4c7 100644 (file)
--- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
+++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
@@ -210,6 +210,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        needs_reset = optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+       rs690_htinit();
        printk_debug("needs_reset=0x%x\n", needs_reset);
 
 

diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c
index 4ae241a7efc7b979083ea4bbe2a87023a3daf1a9..52b5c0400af23af90a99daa954022cda8431ceee 100644 (file)
--- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c
+++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c
@@ -213,6 +213,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        needs_reset = optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+       rs690_htinit();
        printk_debug("needs_reset=0x%x\n", needs_reset);
 
        post_code(0x06);

diff --git a/src/southbridge/amd/rs690/rs690_early_setup.c b/src/southbridge/amd/rs690/rs690_early_setup.c
index 08ce2515c4d3f0c76a5a4d1d11f9056b632e011e..d253f0d868178ceda40e92044fe9439036d4c3cc 100644 (file)
--- a/src/southbridge/amd/rs690/rs690_early_setup.c
+++ b/src/southbridge/amd/rs690/rs690_early_setup.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -175,8 +176,9 @@ static void rs690_htinit()
        /*
         * About HT, it has been done in enumerate_ht_chain().
         */
-       device_t k8_f0;
+       device_t k8_f0, rs690_f0;
        u32 reg;
+       u8 reg8;
        u8 k8_ht_freq;
 
        k8_f0 = PCI_DEV(0, 0x18, 0);
@@ -195,7 +197,22 @@ static void rs690_htinit()
        ************************/
        reg = pci_read_config32(k8_f0, 0x88);
        k8_ht_freq = (reg & 0xf00) >> 8;
-       printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq);
+       printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+       rs690_f0 = PCI_DEV(0, 0, 0);
+       reg8 = pci_read_config8(rs690_f0, 0x9c);
+       printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+       /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
+        * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
+        */
+       if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
+               printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+               reg8 |= 0x1;
+               pci_write_config8(rs690_f0, 0x9c, reg8);
+       } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
+               printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+               reg8 &= ~0x1;
+               pci_write_config8(rs690_f0, 0x9c, reg8);
+       }
 }
 
 /*******************************************************
@@ -462,7 +479,6 @@ static void rs690_early_setup()
                break;
        }
 
-       rs690_htinit();
        k8_optimization();
        rs690_por_init(nb_dev);
 }