codegen_reg_of_var.
* src/vm/jit/powerpc64/emit.c (emit_copy): Likewise.
* src/vm/jit/mips/codegen.c (codegen): Define varindex.
* src/vm/jit/powerpc64/codegen.c (codegen): Likewise. Fixed arguments
to codegen_reg_of_var. Replaced codegen_reg_of_var with
codegen_reg_of_dst.
--HG--
branch : unified_variables
This module generates MIPS machine code for a sequence of
intermediate code commands (ICMDs).
- $Id: codegen.c 5615 2006-10-01 22:55:11Z edwin $
+ $Id: codegen.c 5619 2006-10-01 23:51:23Z edwin $
*/
unresolved_field *uf;
rplpoint *replacementpoint;
s4 fieldtype;
+ s4 varindex;
/* get required compiler data */
order of getting the destination register and the load. */
if (IS_INMEMORY(src->flags)) {
- d = codegen_reg_of_var(rd, iptr->opc, dst, REG_IFTMP);
+ d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
s1 = emit_load(jd, iptr, src, d);
}
else {
s1 = emit_load(jd, iptr, src, REG_IFTMP);
- d = codegen_reg_of_var(rd, iptr->opc, dst, s1);
+ d = codegen_reg_of_var(iptr->opc, dst, s1);
}
if (s1 != d) {
Christian Ullrich
Edwin Steiner
- $Id: codegen.c 5618 2006-10-01 23:37:04Z edwin $
+ $Id: codegen.c 5619 2006-10-01 23:51:23Z edwin $
*/
methoddesc *md;
rplpoint *replacementpoint;
s4 fieldtype;
+ s4 varindex;
/* get required compiler data */
len--;
var = VAR(bptr->invars[len]);
if ((len == bptr->indepth-1) && (bptr->type != BBTYPE_STD)) {
- d = codegen_reg_of_var(rd, 0, var, REG_ITMP1);
+ d = codegen_reg_of_var(0, var, REG_ITMP1);
M_INTMOVE(REG_ITMP1, d);
emit_store(jd, NULL, var, d);
} else {
s1 = emit_load_s1(jd, iptr, REG_ITMP1);
s2 = emit_load_s2(jd, iptr, REG_ITMP2);
- d = codegen_reg_of_var(rd, iptr->opc, iptr->dst.var, PACK_REGS(REG_ITMP2, REG_ITMP1));
+ d = codegen_reg_of_dst(jd, iptr, PACK_REGS(REG_ITMP2, REG_ITMP1));
if (INSTRUCTION_MUST_CHECK(iptr)) {
gen_nullptr_check(s1);
gen_bound_check;
M_ILD_INTERN(d, REG_ITMP1, 0);
break;
case TYPE_LNG:
- d = codegen_reg_of_var(rd, iptr->opc, iptr->dst.var, PACK_REGS(REG_ITMP2, REG_ITMP1));
+ d = codegen_reg_of_dst(jd, iptr, PACK_REGS(REG_ITMP2, REG_ITMP1));
M_ILD_INTERN(GET_LOW_REG(d), REG_ITMP1, 4);/* keep this order */
M_ILD_INTERN(GET_HIGH_REG(d), REG_ITMP1, 0);/*keep this order */
break;
order of getting the destination register and the load. */
if (IS_INMEMORY(src->flags)) {
- d = codegen_reg_of_var(rd, iptr->opc, dst, REG_IFTMP);
+ d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
s1 = emit_load(jd, iptr, src, d);
}
else {
s1 = emit_load(jd, iptr, src, REG_IFTMP);
- d = codegen_reg_of_var(rd, iptr->opc, dst, s1);
+ d = codegen_reg_of_var(iptr->opc, dst, s1);
}
if (s1 != d) {