updated for v2

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb
index 34e1040596dd34f4f0100366846c5a723a7d20f6..ad0d5ac67137dd018527dc77865b19f43835f437 100644 (file)
--- a/src/cpu/ppc/mpc74xx/Config.lb
+++ b/src/cpu/ppc/mpc74xx/Config.lb
@@ -1,7 +1,21 @@
 ##
 ## CPU initialization
 ##
-initinclude "EARLY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
+uses _RAMBASE
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 
+##
+## Use cache ram for initial setup
+##
+default USE_DCACHE_RAM=1
+## Set dcache ram above linuxbios image
+default DCACHE_RAM_BASE=_RAMBASE+0x100000
+## Dcache size is 16Kb
+default DCACHE_RAM_SIZE=16384
+
+initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
 object clock.o
+initobject clock.o
 

diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc
index 6d23c3ad7e3c34911187698439ec7deac0d6da3a..5f6cee20dc54e511af5fac05f79c226fab135920 100644 (file)
--- a/src/cpu/ppc/mpc74xx/mpc74xx.inc
+++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc
@@ -89,13 +89,6 @@
        mtsr    15, r0
        isync
 
-       /*
-        * Initialize northbridge. This has to happen early because it
-        * resets memory. Memory is on at this point, albeit with
-        * pessimistic settings. We reconfigure later using I2C.
-        */
-       bl      bsp_init_northbridge
-
         /*
         * Set up DBATs 
         *
@@ -183,8 +176,3 @@ tlblp:
         ori     r2, r2, HID0_ICE | HID0_ICFI
        isync
         mtspr   HID0, r2
-
-       /*
-        * Must branch to start_payload once CPU initialization is completed
-        */
-       b       start_payload