Fix register typo for core 2 cpus (trivial)

This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 2395f4d4fcb62a34d1ea46daefaca26630a7d8c8..d04274046db3a833295b6288c95b5e2787cec2a3 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -39,7 +39,7 @@ cache_as_ram:
         movl   %eax, (%esi)
 
        /* Disable prefetchers */
-       movl    $0x01a0, %eax
+       movl    $0x01a0, %ecx
        rdmsr
        orl     $((1 << 9) | (1 << 19)), %eax
        orl     $((1 << 5) | (1 << 7)), %edx