shl_imm: dest:i src1:i len:8
shr_imm: dest:i src1:i len:8
shr_un_imm: dest:i src1:i len:8
-cond_exc_eq: len:16
-cond_exc_ne_un: len:16
-cond_exc_lt: len:16
-cond_exc_lt_un: len:16
-cond_exc_gt: len:16
-cond_exc_gt_un: len:16
-cond_exc_ge: len:16
-cond_exc_ge_un: len:16
-cond_exc_le: len:16
-cond_exc_le_un: len:16
-cond_exc_ov: len:16
+cond_exc_eq: len:8
+cond_exc_ne_un: len:8
+cond_exc_lt: len:8
+cond_exc_lt_un: len:8
+cond_exc_gt: len:8
+cond_exc_gt_un: len:8
+cond_exc_ge: len:8
+cond_exc_ge_un: len:8
+cond_exc_le: len:8
+cond_exc_le_un: len:8
+cond_exc_ov: len:12
cond_exc_no: len:8
-cond_exc_c: len:16
+cond_exc_c: len:12
cond_exc_nc: len:8
#float_beq: src1:f src2:f len:20
#float_bne_un: src1:f src2:f len:20
ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
} else { \
mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
- code = mono_arm_patchable_b (code, (condcode)); \
+ ARM_B_COND (code, (condcode), 0); \
}
#define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
#define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
do { \
mono_add_patch_info (cfg, code - cfg->native_code, \
- MONO_PATCH_INFO_EXC, exc_name); \
- code = mono_arm_patchable_bl (code, (condcode)); \
+ MONO_PATCH_INFO_EXC, exc_name); \
+ ARM_BL_COND (code, (condcode), 0); \
} while (0);
#define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))