libgc: Use GCC atomics on ARM.

This is to ensure that if the runtime is compiled for e.g.
ARM v4 or v5, it will use the correct atomics on v6 and v7.

diff --git a/libgc/include/private/gc_locks.h b/libgc/include/private/gc_locks.h
index 5cd03552cb9ceaa10edc888f0b1793158dddb65f..e3c89c1fe9bb4a0e14d52d041efc84bf6d4d3cdd 100644 (file)
--- a/libgc/include/private/gc_locks.h
+++ b/libgc/include/private/gc_locks.h
@@ -231,46 +231,12 @@
 #          define NACL_ALIGN()
 #       endif
         inline static int GC_test_and_set(volatile unsigned int *addr) {
-#if defined(__native_client__) || defined(HAVE_ARMV7)
-          int ret, tmp;
-          __asm__ __volatile__ (
-                                 "1:\n"
-                                 NACL_ALIGN()
-                                 MASK_REGISTER("%3", "al")
-                                 "ldrex %0, [%3]\n"
-                                 MASK_REGISTER("%3", "al")
-                                 "strex %1, %2, [%3]\n" 
-                                 "teq %1, #0\n"
-                                 "bne 1b\n"
-                                 : "=&r" (ret), "=&r" (tmp)
-                                 : "r" (1), "r" (addr)
-                                 : "memory", "cc");
-          return ret;
-#else
-          int oldval;
-          /* SWP on ARM is very similar to XCHG on x86.  Doesn't lock the
-           * bus because there are no SMP ARM machines.  If/when there are,
-           * this code will likely need to be updated. */
-          /* See linuxthreads/sysdeps/arm/pt-machine.h in glibc-2.1 */
-          __asm__ __volatile__(MASK_REGISTER("%2", "al")
-                               "swp %0, %1, [%2]"
-                            : "=&r"(oldval)
-                            : "r"(1), "r"(addr)
-                            : "memory");
-          return oldval;
-#endif
+                 __sync_lock_test_and_set (addr, 1);
         }
 #       define GC_TEST_AND_SET_DEFINED
       inline static void GC_clear(volatile unsigned int *addr) {
-                 /* Memory barrier */
-#if defined(__native_client__) || defined(HAVE_ARMV7)
-                 /* NaCl requires ARMv7 CPUs. */
-                 __asm__ __volatile__("dsb" : : : "memory");
-#elif defined(HAVE_ARMV6)
-                 __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
-#else
-                 /* No barrier required on pre-v6. */
-#endif
+                 __sync_synchronize ();
+
                  *(addr) = 0;
       }
 #     define GC_CLEAR_DEFINED