//TODO Reorganize SSE opcode defines.
-/* Move gpr <-> xmm */
-
-#define amd64_movq_xmm_reg(inst,dreg,reg) \
- do { \
- amd64_codegen_pre((inst)); \
- x86_prefix((inst), X86_OPERAND_PREFIX); \
- amd64_emit_rex((inst), 8, (dreg), 0, (reg)); \
- *(inst)++ = (unsigned char)0x0f; \
- *(inst)++ = (unsigned char)0x6e; \
- x86_reg_emit((inst), (dreg), (reg)); \
- amd64_codegen_post((inst)); \
- } while (0)
-
-#define amd64_movq_reg_xmm(inst,dreg,reg) \
- do { \
- amd64_codegen_pre((inst)); \
- x86_prefix((inst), X86_OPERAND_PREFIX); \
- amd64_emit_rex((inst), 8, (reg), 0, (dreg)); \
- *(inst)++ = (unsigned char)0x0f; \
- *(inst)++ = (unsigned char)0x7e; \
- x86_reg_emit((inst), (reg), (dreg)); \
- amd64_codegen_post((inst)); \
- } while (0)
-
/* Two opcode SSE defines */
#define emit_sse_reg_reg_op2_size(inst,dreg,reg,op1,op2,size) do { \
float_clt_un_membase: dest:i src1:f src2:b len:42
float_conv_to_u: dest:i src1:f len:46
fmove: dest:f src1:f len:8
-move_f_to_i4: dest:i src1:f len:9
-move_i4_to_f: dest:f src1:i len:9
+move_f_to_i4: dest:i src1:f len:16
+move_i4_to_f: dest:f src1:i len:16
move_f_to_i8: dest:i src1:f len:5
move_i8_to_f: dest:f src1:i len:5
call_handler: len:14 clob:c nacl:52
break;
case OP_MOVE_F_TO_I4:
amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
- amd64_movq_reg_xmm (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
+ amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
break;
case OP_MOVE_I4_TO_F:
- amd64_movq_xmm_reg (code, ins->dreg, ins->sreg1);
+ amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
break;
case OP_MOVE_F_TO_I8:
- amd64_movq_reg_xmm (code, ins->dreg, ins->sreg1);
+ amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
break;
case OP_MOVE_I8_TO_F:
- amd64_movq_xmm_reg (code, ins->dreg, ins->sreg1);
+ amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
break;
case OP_FADD:
amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);