AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.

Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index c56576aa6c9772f5062972f66ef5855ca36527d4..afeb4e98d21f22a5499184999653b39590c43fd2 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3461,9 +3461,10 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
                i = 0; /* use i for the dct setting required */
                if (pDCTstat->MAdimms[0] < 4)
                        i = 1;
-               if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4))
+               if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) {
                        dword &= 0xF18FFF18;
                        index_reg = 0x98;       /* force dct = 0 */
+               }
        }
 
        Set_NB32_index_wait(dev, index_reg, 0x0a, dword);

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 0e187621b41d4188c9df16285b47976b80261df6..09ade32f4688f9455bfbc007dd38873441721a9f 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -3127,9 +3127,10 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
                i = 0; /* use i for the dct setting required */
                if (pDCTstat->MAdimms[0] < 4)
                        i = 1;
-               if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4))
+               if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) {
                        dword &= 0xF18FFF18;
                        index_reg = 0x98;       /* force dct = 0 */
+               }
        }
 
        Set_NB32_index_wait(dev, index_reg, 0x0a, dword);