subdirs-y += pci
+subdirs-y += generic/debug
subdirs-y += ati/ragexl
--- /dev/null
+obj-$(CONFIG_DRIVERS_GENERIC_DEBUG) += debug_dev.o
prompt "Mainboard model"
depends on VENDOR_AMD
-source "src/mainboard/amd/serengeti_cheetah/Kconfig"
+source "src/mainboard/amd/db800/Kconfig"
+source "src/mainboard/amd/dbm690t/Kconfig"
+source "src/mainboard/amd/norwich/Kconfig"
+source "src/mainboard/amd/pistachio/Kconfig"
source "src/mainboard/amd/rumba/Kconfig"
+source "src/mainboard/amd/serengeti_cheetah/Kconfig"
+source "src/mainboard/amd/serengeti_cheetah_fam10/Kconfig"
endchoice
--- /dev/null
+config BOARD_AMD_DB800
+ bool "DB800"
+ select ARCH_X86
+ select CPU_AMD_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
+
+config MAINBOARD_DIR
+ string
+ default amd/db800
+ depends on BOARD_AMD_DB800
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "DB800"
+ depends on BOARD_AMD_DB800
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_AMD_DB800
+
+config IRQ_SLOT_COUNT
+ int
+ default 6
+ depends on BOARD_AMD_DB800
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_AMD_DB800
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_AMD_DB800
+
+config RAMBASE
+ hex
+ default 0x4000
+ depends on BOARD_AMD_DB800
--- /dev/null
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
--- /dev/null
+config BOARD_AMD_DBM690T
+ bool "DBM690T"
+ select ARCH_X86
+ select CPU_AMD_K8
+ select CPU_AMD_SOCKET_S1G1
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_AMD_RS690
+ select SOUTHBRIDGE_AMD_SB600
+ select SUPERIO_ITE_IT8712F
+ select HAVE_PIRQ_TABLE
+ select USE_PRINTK_IN_CAR
+ select USE_DCACHE_RAM
+ select HAVE_HARD_RESET
+ select IOAPIC
+ select AP_CODE_IN_CAR
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select WAIT_BEFORE_CPUS_INIT
+ select HAVE_ACPI_TABLES
+
+config MAINBOARD_DIR
+ string
+ default amd/dbm690t
+ depends on BOARD_AMD_DBM690T
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_AMD_DBM690T
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x08000
+ depends on BOARD_AMD_DBM690T
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x01000
+ depends on BOARD_AMD_DBM690T
+
+config APIC_ID_OFFSET
+ hex
+ default 0x8
+ depends on BOARD_AMD_DBM690T
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_AMD_DBM690T
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_AMD_DBM690T
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "DBM690T"
+ depends on BOARD_AMD_DBM690T
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x100000
+ depends on BOARD_AMD_DBM690T
+
+config MAX_CPUS
+ int
+ default 2
+ depends on BOARD_AMD_DBM690T
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+ depends on BOARD_AMD_DBM690T
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+ depends on BOARD_AMD_DBM690T
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_AMD_DBM690T
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x6
+ depends on BOARD_AMD_DBM690T
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0xa
+ depends on BOARD_AMD_DBM690T
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_AMD_DBM690T
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+ depends on BOARD_AMD_DBM690T
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
+ iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
+ mv $(obj)/dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
--- /dev/null
+config BOARD_AMD_NORWICH
+ bool "Norwich"
+ select ARCH_X86
+ select CPU_AMD_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
+
+config MAINBOARD_DIR
+ string
+ default amd/norwich
+ depends on BOARD_AMD_NORWICH
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "NORWICH"
+ depends on BOARD_AMD_NORWICH
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_AMD_NORWICH
+
+config IRQ_SLOT_COUNT
+ int
+ default 6
+ depends on BOARD_AMD_NORWICH
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_AMD_NORWICH
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_AMD_NORWICH
+
+config RAMBASE
+ hex
+ default 0x4000
+ depends on BOARD_AMD_NORWICH
--- /dev/null
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
--- /dev/null
+config BOARD_AMD_PISTACHIO
+ bool "Pistachio"
+ select ARCH_X86
+ select CPU_AMD_K8
+ select CPU_AMD_SOCKET_AM2
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_AMD_RS690
+ select SOUTHBRIDGE_AMD_SB600
+ select HAVE_PIRQ_TABLE
+ select USE_PRINTK_IN_CAR
+ select USE_DCACHE_RAM
+ select HAVE_HARD_RESET
+ select IOAPIC
+ select AP_CODE_IN_CAR
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select WAIT_BEFORE_CPUS_INIT
+ select HAVE_ACPI_TABLES
+
+config MAINBOARD_DIR
+ string
+ default amd/pistachio
+ depends on BOARD_AMD_PISTACHIO
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_AMD_PISTACHIO
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x08000
+ depends on BOARD_AMD_PISTACHIO
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x01000
+ depends on BOARD_AMD_PISTACHIO
+
+config APIC_ID_OFFSET
+ hex
+ default 0x8
+ depends on BOARD_AMD_PISTACHIO
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_AMD_PISTACHIO
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_AMD_PISTACHIO
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PISTACHIO"
+ depends on BOARD_AMD_PISTACHIO
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x100000
+ depends on BOARD_AMD_PISTACHIO
+
+config MAX_CPUS
+ int
+ default 2
+ depends on BOARD_AMD_PISTACHIO
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+ depends on BOARD_AMD_PISTACHIO
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+ depends on BOARD_AMD_PISTACHIO
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_AMD_PISTACHIO
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x6
+ depends on BOARD_AMD_PISTACHIO
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0xa
+ depends on BOARD_AMD_PISTACHIO
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_AMD_PISTACHIO
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+ depends on BOARD_AMD_PISTACHIO
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
+ iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl
+ mv $(obj)/dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
--- /dev/null
+config BOARD_AMD_SERENGETI_CHEETAH_FAM10
+ bool "Serengeti Cheetah (Fam10)"
+ select ARCH_X86
+ select CPU_AMD_FAM10
+ select CPU_AMD_SOCKET_F_1207
+ select NORTHBRIDGE_AMD_AMDFAM10
+ select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
+ select SOUTHBRIDGE_AMD_AMD8111
+ select SOUTHBRIDGE_AMD_AMD8132
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select USE_PRINTK_IN_CAR
+ select USE_DCACHE_RAM
+ select HAVE_HARD_RESET
+ select IOAPIC
+ select AP_CODE_IN_CAR
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select WAIT_BEFORE_CPUS_INIT
+ select AMDMCT
+
+config MAINBOARD_DIR
+ string
+ default amd/serengeti_cheetah_fam10
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x08000
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x01000
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config APIC_ID_OFFSET
+ hex
+ default 0x8
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Serengeti-Cheetah-Fam10"
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x100000
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+# 6 * MAX_PHYSICAL_CPUS
+config MAX_CPUS
+ int
+ default 48
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 8
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x6
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0xa
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config SERIAL_CPU_INIT
+ bool
+ default n
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
+config AMD_UCODE_PATCH_FILE
+ string
+ default "mc_patch_01000095.h"
+ depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
+
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+
+# ./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt4.o
+driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+ iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+ mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+ iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+ perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+ mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+ iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+ mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
-#
+choice
+ prompt "Mainboard model"
+ depends on VENDOR_DIGITAL_LOGIC
+
+source "src/mainboard/digitallogic/adl855pc/Kconfig"
+source "src/mainboard/digitallogic/msm586seg/Kconfig"
+source "src/mainboard/digitallogic/msm800sev/Kconfig"
+
+endchoice
+
--- /dev/null
+config BOARD_DIGITALLOGIC_ADL855PC
+ bool "ADL855PC"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_MPGA479M
+ select NORTHBRIDGE_INTEL_I855PM
+ select SOUTHBRIDGE_INTEL_I82801DBM
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select UDELAY_TSC
+
+config MAINBOARD_DIR
+ string
+ default digitallogic/adl855pc
+ depends on BOARD_DIGITALLOGIC_ADL855PC
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ADL855PC"
+ depends on BOARD_DIGITALLOGIC_ADL855PC
+
+config IRQ_SLOT_COUNT
+ int
+ default 5
+ depends on BOARD_DIGITALLOGIC_ADL855PC
--- /dev/null
+ROMCCFLAGS := -mcpu=p3 -O
+include $(src)/mainboard/Makefile.romccboard.inc
+
--- /dev/null
+config BOARD_DIGITALLOGIC_MSM586SEG
+ bool "MSM586SEG"
+ select ARCH_X86
+ select CPU_AMD_SC520
+ select HAVE_PIRQ_TABLE
+
+config MAINBOARD_DIR
+ string
+ default digitallogic/msm586seg
+ depends on BOARD_DIGITALLOGIC_MSM586SEG
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "TS5300"
+ depends on BOARD_DIGITALLOGIC_MSM586SEG
+
+config IRQ_SLOT_COUNT
+ int
+ default 2
+ depends on BOARD_DIGITALLOGIC_MSM586SEG
+
--- /dev/null
+ROMCCFLAGS := -mcpu=i386 -O
+include $(src)/mainboard/Makefile.romccboard.inc
+
--- /dev/null
+config BOARD_DIGITALLOGIC_MSM800SEV
+ bool "MSM800SEV"
+ select ARCH_X86
+ select CPU_AMD_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+ select USE_DCACHE_RAM
+ select USE_PRINTK_IN_CAR
+
+config MAINBOARD_DIR
+ string
+ default digitallogic/msm800sev
+ depends on BOARD_DIGITALLOGIC_MSM800SEV
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MSM800SEV"
+ depends on BOARD_DIGITALLOGIC_MSM800SEV
+
+config HAVE_OPTION_TABLE
+ bool
+ default n
+ depends on BOARD_DIGITALLOGIC_MSM800SEV
+
+config IRQ_SLOT_COUNT
+ int
+ default 7
+ depends on BOARD_DIGITALLOGIC_MSM800SEV
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_DIGITALLOGIC_MSM800SEV
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_DIGITALLOGIC_MSM800SEV
+
+config RAMBASE
+ hex
+ default 0x4000
+ depends on BOARD_DIGITALLOGIC_MSM800SEV
--- /dev/null
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
depends on VENDOR_SUPERMICRO
source "src/mainboard/supermicro/h8dme/Kconfig"
-#source "src/mainboard/supermicro/h8dmr/Kconfig"
-#source "src/mainboard/supermicro/x6dai_g/Kconfig"
-#source "src/mainboard/supermicro/x6dhe_g/Kconfig"
-#source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
-#source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
-#source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
+source "src/mainboard/supermicro/h8dmr/Kconfig"
+source "src/mainboard/supermicro/h8dmr_fam10/Kconfig"
+source "src/mainboard/supermicro/x6dai_g/Kconfig"
+source "src/mainboard/supermicro/x6dhe_g/Kconfig"
+source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
+source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
+source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
endchoice
config MAINBOARD_PART_NUMBER
string
- default "ultra40"
+ default "H8DME"
depends on BOARD_SUPERMICRO_H8DME
config HW_MEM_HOLE_SIZEK
--- /dev/null
+config BOARD_SUPERMICRO_H8DMR
+ bool "H8DMR"
+ select ARCH_X86
+ select CPU_AMD_K8
+ select CPU_AMD_SOCKET_F
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_NVIDIA_MCP55
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select USE_PRINTK_IN_CAR
+ select USE_DCACHE_RAM
+ select HAVE_HARD_RESET
+ select IOAPIC
+
+config MAINBOARD_DIR
+ string
+ default supermicro/h8dmr
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x08000
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x01000
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config APIC_ID_OFFSET
+ hex
+ default 0x10
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H8DMR"
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x100000
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 2
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x0
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_SUPERMICRO_H8DMR
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+ depends on BOARD_SUPERMICRO_H8DMR
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+ iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+ mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+ iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+ perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+ mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+ iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+ mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
--- /dev/null
+config BOARD_SUPERMICRO_H8DMR_FAM10
+ bool "H8DMR_FAM10 (Fam10)"
+ select ARCH_X86
+ select CPU_AMD_FAM10
+ select CPU_AMD_SOCKET_F_1207
+ select NORTHBRIDGE_AMD_AMDFAM10
+ select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
+ select SOUTHBRIDGE_NVIDIA_MCP55
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select USE_PRINTK_IN_CAR
+ select USE_DCACHE_RAM
+ select HAVE_HARD_RESET
+ select IOAPIC
+ select AMDMCT
+
+config MAINBOARD_DIR
+ string
+ default supermicro/h8dmr_fam10
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc8000
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x08000
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x01000
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config APIC_ID_OFFSET
+ hex
+ default 0x10
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H8DMR_FAM10 FAM10"
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x100000
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 2
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x0
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 2
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config AMD_UCODE_PATCH_FILE
+ string
+ default "mc_patch_0100009f.h"
+ depends on BOARD_SUPERMICRO_H8DMR_FAM10
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+ iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+ mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+ iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+ perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+ mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+ iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+ mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
--- /dev/null
+config BOARD_SUPERMICRO_X6DAI_G
+ bool "X6DAI-G"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_MPGA604
+ select NORTHBRIDGE_INTEL_E7525
+ select SOUTHBRIDGE_INTEL_ESB6300
+ select SUPERIO_WINBOND_W83627HF
+ select PIRQ_TABLE
+
+config MAINBOARD_DIR
+ string
+ default supermicro/x6dai_g
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X6DAI_G"
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x15d9
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x6780
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_X6DAI_G
+
+config IRQ_SLOT_COUNT
+ int
+ default 15
+ depends on BOARD_SUPERMICRO_X6DAI_G
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ROMCCFLAGS=-mcpu=p4 -O2
+
+include $(src)/mainboard/Makefile.romccboard.inc
+
--- /dev/null
+config BOARD_SUPERMICRO_X6DHE_G
+ bool "X6DHE-G"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_MPGA604
+ select NORTHBRIDGE_INTEL_E7520
+ select SOUTHBRIDGE_INTEL_ESB6300
+ select SOUTHBRIDGE_INTEL_PXHD
+ select SUPERIO_WINBOND_W83627HF
+ select PIRQ_TABLE
+
+config MAINBOARD_DIR
+ string
+ default supermicro/x6dhe_g
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X6DHE_G"
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x15d9
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x6780
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config IRQ_SLOT_COUNT
+ int
+ default 15
+ depends on BOARD_SUPERMICRO_X6DHE_G
+
+config DRIVERS_GENERIC_DEBUG
+ bool
+ default y
+ depends on BOARD_SUPERMICRO_X6DHE_G
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ROMCCFLAGS=-mcpu=p4 -O2
+
+include $(src)/mainboard/Makefile.romccboard.inc
+
--- /dev/null
+config BOARD_SUPERMICRO_X6DHE_G2
+ bool "X6DAI-G"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_MPGA604
+ select NORTHBRIDGE_INTEL_E7520
+ select SOUTHBRIDGE_INTEL_I82801ER
+ select SOUTHBRIDGE_INTEL_PXHD
+ select SUPERIO_NSC_PC87427
+ select PIRQ_TABLE
+
+config MAINBOARD_DIR
+ string
+ default supermicro/x6dhe_g2
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X6DHE_G2"
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x15d9
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x6780
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config IRQ_SLOT_COUNT
+ int
+ default 15
+ depends on BOARD_SUPERMICRO_X6DHE_G2
+
+config DRIVERS_GENERIC_DEBUG
+ bool
+ default y
+ depends on BOARD_SUPERMICRO_X6DHE_G2
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ROMCCFLAGS=-mcpu=p4 -O2
+
+include $(src)/mainboard/Makefile.romccboard.inc
+
--- /dev/null
+config BOARD_SUPERMICRO_X6DHR_IG
+ bool "X6DHR-IG"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_MPGA604
+ select NORTHBRIDGE_INTEL_E7520
+ select SOUTHBRIDGE_INTEL_I82801ER
+ select SOUTHBRIDGE_INTEL_PXHD
+ select SUPERIO_WINBOND_W83627HF
+ select PIRQ_TABLE
+
+config MAINBOARD_DIR
+ string
+ default supermicro/x6dhr_ig
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X6DHR_IG"
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x15d9
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x6780
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_X6DHR_IG
+
+config IRQ_SLOT_COUNT
+ int
+ default 15
+ depends on BOARD_SUPERMICRO_X6DHR_IG
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ROMCCFLAGS=-mcpu=p4 -O2
+
+include $(src)/mainboard/Makefile.romccboard.inc
+
--- /dev/null
+config BOARD_SUPERMICRO_X6DHR_IG2
+ bool "X6DHR-IG"
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_MPGA604
+ select NORTHBRIDGE_INTEL_E7520
+ select SOUTHBRIDGE_INTEL_I82801ER
+ select SOUTHBRIDGE_INTEL_PXHD
+ select SUPERIO_WINBOND_W83627HF
+ select PIRQ_TABLE
+
+config MAINBOARD_DIR
+ string
+ default supermicro/x6dhr_ig2
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config LB_CKS_RANGE_END
+ int
+ default 122
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config LB_CKS_LOC
+ int
+ default 123
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X6DHR_IG2"
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x15d9
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x6780
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config MAX_CPUS
+ int
+ default 4
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config USE_INIT
+ bool
+ default n
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
+
+config IRQ_SLOT_COUNT
+ int
+ default 15
+ depends on BOARD_SUPERMICRO_X6DHR_IG2
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ROMCCFLAGS=-mcpu=p4 -O2
+
+include $(src)/mainboard/Makefile.romccboard.inc
+
projects / coreboot.git / commitdiff